Re: [casper] Help with setting up RFSoC

[Heystek Grobler]

Hey Mitch. 

Thank you for the reply. 

The Python version that my system is returning is 3.7.13. 

Should I rather use Python 3.8? I have noticed that matlab2021a does not 
support python3.9. 

Thank you 
-
Heystek Grobler

0832721009
heystekgrob...@gmail.com


> On 14 Nov 2023, at 18:23, Mitchell Burnett  wrote:
> 
> Hi Haystek,
> 
> This most likely is a python version conflict. When you activate your Python 
> environment, what is the version of Python that `python -V` returns? For me, 
> my casper dev env returns Python 3.8.2.
> 
> The second tutorial incorporates the RFDC yellow block. When the back end 
> tool encounters this block there is additional code that is triggered to 
> support the software defined capabilities of the RFDC in the on-chip 
> processor. This is why running the first tutorial this may go unnoticed but 
> encountered when building subsequent models for RFSoC.
> 
> Hope this helps,
> Mitch
> 
>> On Nov 14, 2023, at 6:21 AM, Heystek Grobler > <mailto:heystekgrob...@gmail.com>> wrote:
>> 
>> Good day everyone. 
>> 
>> I have some good news. 
>> 
>> I have gotten the first tutorial from the RFSoC ZCU111 to compile on both of 
>> my machines without any issues. Thank you everyone for all the help! I 
>> really appreciate it! 
>> 
>> I have tried to compile the second tutorial and I get the same error message 
>> on both of my machines. The screenshot is attached below. 
>> 
>> 
>> I have no idea why the first tutorial compiles but the second one doesn't. 
>> 
>> Does anyone have an idea what might be going on? 
>> 
>> Thank you so much for the help. 
>> 
>> Heystek
>> 
>> -
>> Heystek Grobler
>> 
>> 0832721009
>> heystekgrob...@gmail.com <mailto:heystekgrob...@gmail.com>
>> 
>> 
>> On Wed, Nov 1, 2023 at 7:39 PM Mitch Burnett > <mailto:mitch.burn...@byu.edu>> wrote:
>>> Hi Heystek,
>>> 
>>> I think it better if you used 20.04. Is the first machine (18.04) the one 
>>> that crashes and that when you have had Matlab working that comes from your 
>>> second machine (20.04)?
>>> 
>>> I just did some tests and was able to reproduce your issue with generating 
>>> the dtbo. In your xilinx device tree repo, checkout the `xlnx_rel_v2021.1` 
>>> branch. This is not in the "Getting Started with RFSoC” guide, and now 
>>> needs to be. We will need to make sure to get this change documented.
>>> 
>>> Additionally, I also now realize that mlib_devel `m2021a` branch will not 
>>> work with the most recent tutorials that were recently updated for new 
>>> changes that fixes a slew of issues with the rfdc yellow block. This is 
>>> because those changes are in the `m2021a-dev` branch of mlib_devel and yet 
>>> to be merged into `m2021a`. Hopefully we can do that soon. But, for now, 
>>> please be sure to also checkout the `m2021a-dev` branch of your mlib_devel 
>>> repo before moving into the subsequent tutorials that use the rfdc (the adc 
>>> interface and spectrometer tutorials).
>>> 
>>> Best,
>>> Mitch
>>> 
>>>> On Nov 1, 2023, at 4:33 AM, Heystek Grobler >>> <mailto:heystekgrob...@gmail.com>> wrote:
>>>> 
>>>> 
>>>> Hey Mitch and everyone. 
>>>> 
>>>> Thank you so much for the help! I really appreciate it! 
>>>> 
>>>> I am trying to set up the toolflow on two machines. 
>>>> 
>>>> The first machine is:
>>>> Ubuntu 18.04 LTS
>>>> Vitis/Vivado 2021.1
>>>> 
>>>> The second machine:
>>>> Ubuntu 20.04 LTS
>>>> Vitis/Vivado 2021.1
>>>> 
>>>> I am currently busy with the setup on the first machine (Ubuntu 18.04) 
>>>> since the second machine is having issues regarding the university 
>>>> firewall. If needed I can update the first machine to Ubuntu 20.04. 
>>>> 
>>>> I downloaded the Xilinx device tree repo by making use of (I assume it is 
>>>> the current master branch commit1a5881d 
>>>> <https://github.com/Xilinx/device-tree-xlnx/commit/1a5881d00406fa4f68eee63064799b8e5b28a41a>):
>>>>  git clone https://github.com/xilinx/device-tree-xlnx.git
>>>> 
>>>> Below are screenshots of the Matlab crash at startup:
>>>> 
>>>> 
>>>> 
>>>>

Re: [casper] Help with setting up RFSoC

[Heystek Grobler]

Hey Jack and Kaj.

Thank you so much for the help and guidance. So the license I got with the
RFSoC ZSU111 does not contain the Xilinx ML Enterprise Edition and it also
does not contain SysGen.

My University (The University of Pretoria) is reaching out to Xilinx to buy
the appropriate licence. Will it suffice if the University gets the Xilinx
ML Enterprise Edition and SysGen or should something else be added to it?

Thank you for the help!

Heystek
-
Heystek Grobler

0832721009
heystekgrob...@gmail.com



On Sun, Oct 1, 2023 at 6:09 PM Jack Hickish  wrote:

> I would suggest trying to get the new license. I'm suspect that Vivado
> 2020 supports the RFSoC chips you want (though I haven't checked) but using
> an older version than the toolflow suggests will almost certainly lead to
> other issues. Swimming against the CASPER version-tide is never a
> particularly fun thing to do :)
>
>
> On Sun, 1 Oct 2023 at 13:22, Heystek Grobler 
> wrote:
>
>> Hey Jack.
>>
>> Should I then try to get a SysGen/ModelComposer license for 2021.1 or is
>> there a way to still use Vivado 2020.06 with the RFSoC?
>>
>> Thank you for the help!
>>
>> Heystek
>>
>> -
>> Heystek Grobler
>>
>> 0832721009
>> heystekgrob...@gmail.com
>>
>>
>> On 01 Oct 2023, at 14:12, Jack Hickish  wrote:
>>
>> Not quite sure what to make of this, but I don't see anything for SysGen
>> / ModelComposer newer than 2020.06, which wouldn't be valid with Vivado
>> 2021.1
>>
>> On Sun, 1 Oct 2023 at 12:47, Heystek Grobler 
>> wrote:
>>
>>> Hey Jack.
>>>
>>> Thank you so much for the email.
>>>
>>> I have included screenshots of the licence manager below:
>>>
>>> 
>>>
>>> 
>>>
>>> 
>>>
>>> Do I need another/different licence from Xilinx or is there a way around
>>> this?
>>>
>>> Thank you for the help.
>>>
>>> Heystek
>>> -
>>> Heystek Grobler
>>>
>>> 0832721009
>>> heystekgrob...@gmail.com
>>>
>>>
>>>
>>> On Sun, Oct 1, 2023 at 1:10 PM Jack Hickish 
>>> wrote:
>>>
>>>> Hi Heystek,
>>>>
>>>> As the error in the diagnostic viewer suggests -- you don't seem to
>>>> have an appropriate sysgen license, in either the default search paths (I
>>>> think at least one of these is ~/.Xilinx/Xilinx.lic) or specified with an
>>>> environment variable. Do you think you have a license the system isn't
>>>> finding or is it possible you just need to get one from Xilinx?
>>>>
>>>> Also, the "Could not find Vitis installation" at the start of the
>>>> MATLAB prompt is concerning, but I don't think that's the current issue.
>>>>
>>>> Cheers
>>>> Jack
>>>>
>>>> On Sun, 1 Oct 2023 at 11:58, Heystek Grobler 
>>>> wrote:
>>>>
>>>>> Good day everyone.
>>>>>
>>>>> I hope that this email finds you well.
>>>>>
>>>>> I am used to working with a ROACH2 and have now started with an RFSoC
>>>>> ZCU111. I followed the instructions on the CASPER Read The Docs Page and
>>>>> installed Ubuntu 20.04, Matlab 2021a and Vivado 2021.1.
>>>>>
>>>>> When I try to compile the first tutorial with jasper I get the
>>>>> following two errors (screenshots provided).
>>>>>
>>>>> 
>>>>>
>>>>> 
>>>>>
>>>>> Does anyone perhaps know how I can solve this?
>>>>>
>>>>> Thank you for the help.
>>>>>
>>>>> Heystek
>>>>>
>>>>>
>>>>> -
>>>>> Heystek Grobler
>>>>>
>>>>> 0832721009
>>>>> heystekgrob...@gmail.com
>>>>>
>>>>>
>>>>> --
>>>>> You received this message because you are subscribed to the Google
>>>>> Groups "casper@lists.berkeley.edu" group.
>>>>> To unsubscribe from this group and stop receiving emails from it, send
>>>>> an email to casper+unsubscr...@lists.berkeley.edu.
>>>>> To view this discussion on the web

Re: [casper] Help with setting up RFSoC

[Heystek Grobler]

Hey Jack. 

Should I then try to get a SysGen/ModelComposer license for 2021.1 or is there 
a way to still use Vivado 2020.06 with the RFSoC? 

Thank you for the help! 

Heystek

-
Heystek Grobler

0832721009
heystekgrob...@gmail.com


> On 01 Oct 2023, at 14:12, Jack Hickish  wrote:
> 
> Not quite sure what to make of this, but I don't see anything for SysGen / 
> ModelComposer newer than 2020.06, which wouldn't be valid with Vivado 2021.1
> 
> On Sun, 1 Oct 2023 at 12:47, Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
>> Hey Jack. 
>> 
>> Thank you so much for the email. 
>> 
>> I have included screenshots of the licence manager below:
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> Do I need another/different licence from Xilinx or is there a way around 
>> this? 
>> 
>> Thank you for the help. 
>> 
>> Heystek
>> -
>> Heystek Grobler
>> 
>> 0832721009
>> heystekgrob...@gmail.com <mailto:heystekgrob...@gmail.com>
>> 
>> 
>> On Sun, Oct 1, 2023 at 1:10 PM Jack Hickish > <mailto:jackhick...@gmail.com>> wrote:
>>> Hi Heystek,
>>> 
>>> As the error in the diagnostic viewer suggests -- you don't seem to have an 
>>> appropriate sysgen license, in either the default search paths (I think at 
>>> least one of these is ~/.Xilinx/Xilinx.lic) or specified with an 
>>> environment variable. Do you think you have a license the system isn't 
>>> finding or is it possible you just need to get one from Xilinx?
>>> 
>>> Also, the "Could not find Vitis installation" at the start of the MATLAB 
>>> prompt is concerning, but I don't think that's the current issue.
>>> 
>>> Cheers
>>> Jack
>>> 
>>> On Sun, 1 Oct 2023 at 11:58, Heystek Grobler >> <mailto:heystekgrob...@gmail.com>> wrote:
>>>> Good day everyone. 
>>>> 
>>>> I hope that this email finds you well. 
>>>> 
>>>> I am used to working with a ROACH2 and have now started with an RFSoC 
>>>> ZCU111. I followed the instructions on the CASPER Read The Docs Page and 
>>>> installed Ubuntu 20.04, Matlab 2021a and Vivado 2021.1.  
>>>> 
>>>> When I try to compile the first tutorial with jasper I get the following 
>>>> two errors (screenshots provided).
>>>> 
>>>> 
>>>> 
>>>> 
>>>> 
>>>> Does anyone perhaps know how I can solve this? 
>>>> 
>>>> Thank you for the help. 
>>>> 
>>>> Heystek
>>>> 
>>>> 
>>>> -
>>>> Heystek Grobler
>>>> 
>>>> 0832721009
>>>> heystekgrob...@gmail.com <mailto:heystekgrob...@gmail.com>
>>>> 
>>>> -- 
>>>> You received this message because you are subscribed to the Google Groups 
>>>> "casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>" group.
>>>> To unsubscribe from this group and stop receiving emails from it, send an 
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>>>>  
>>>> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CALWRf%3DTL3FSr%3DJuDgdckj_Euj12y9bo_CWw_KpE_fF9D6aEg%2BA%40mail.gmail.com?utm_medium=email_source=footer>.
>>> 
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Re: [casper] Used to operate the ROACH2 operating system

[Heystek Grobler]

Hey Wang. 

It is a pleasure. 

Contributing to Michaels VM. I also have an Ubuntu VM that I run on a Macbook 
Pro that works well with a ROACH2. With my VM I don’t have to setup anything 
special, I just run my VM and it works. 

A few years back I was in the same predicament as you and learned my way around 
the casper stuff. 

I hope it helps. 

Heystek 



> On 13 Jun 2022, at 14:42, 王钊  wrote:
> 
> Thank you much Heystek!
> 
> You've been very helpful to me.
> 
> Heystek Grobler mailto:heystekgrob...@gmail.com>> 
> 于2022年6月13日周一 19:33写道：
> Hey Wang
> 
> It is a pleasure. 
> 
> Yes, ISE14.7 works with Ubuntu 18.04 LTS without any problems. 
> 
> I do not use netboot or dnsmasq. My /etc/exports fie is also empty. 
> 
> Here is screenshots of my interfaces and ifconfig:
> 
> 
> 
> 
> 
> I hope it helps. 
> 
> Heystek 
> 
> -
> Heystek Grobler
> 
> 0832721009
> heystekgrob...@gmail.com <mailto:heystekgrob...@gmail.com>
> 
> 
> 
> 
> 
>> On 13 Jun 2022, at 12:18, 王钊 > <mailto:sandang19990...@gmail.com>> wrote:
>> 
>> Hi Heystek,
>> 
>> Thank you for your reply!
>> 
>> Can you use ISE14.7 when using Ubuntu 18.04?  I think the official website 
>> says this version is not supported.
>> 
>> I was using Ubuntu 16.04 and had a problem with NFS mount on netboot.
>> 
>> 
>> In terms of hardware, I consulted the after-sale technician of the computer 
>> and they said that my computer does not support CentOS6.5 and Fedora23.
>> 
>> I would like to take a look at your Ubuntu 18 file Settings, could you 
>> please take a screenshot?
>> 
>> 1.dnsmasq.conf  2.exports 3.interfaces  and ifconfig
>> 
>> BW
>> Wang
>> 
>> Heystek Grobler mailto:heystekgrob...@gmail.com>> 
>> 于2022年6月13日周一 17:40写道：
>> Good day Wang. 
>> 
>> I use Ubuntu 18.04 LTS with Matlab 2012b with my ROACH2 and it is working 
>> fine. 
>> 
>> What are the problems that you are encountering with booting up? What are 
>> the hardware that you are running? 
>> 
>> Have a great day!
>> 
>> Heystek 
>> 
>> -
>> Heystek Grobler
>> 
>> 0832721009
>> heystekgrob...@gmail.com <mailto:heystekgrob...@gmail.com>
>> 
>> 
>> 
>> 
>> 
>>> On 13 Jun 2022, at 05:32, Wang >> <mailto:sandang19990...@gmail.com>> wrote:
>>> 
>>> Hello CASPER,
>>> 
>>> How's it going?I am currently using ROACH2.
>>> 
>>> However, there are always some problems when booting up, and I want to try 
>>> another Linux system.
>>> 
>>> I tried installing CentOS6.5 and Fedora23, but my computer couldn't install 
>>> it due to hardware problems. When I used Ubuntu14.04, my computer was very 
>>> slow, which affected my operation.
>>> 
>>> What version of Linux system can you recommend?
>>> 
>>> Thanks.
>>> 
>>> Regards.
>>> 
>>> Wang
>>> 
>>> 
>>> 
>>> -- 
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>>>  
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>> 
>> 
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Re: [casper] Used to operate the ROACH2 operating system

[Heystek Grobler]

Good day Wang. 

I use Ubuntu 18.04 LTS with Matlab 2012b with my ROACH2 and it is working fine. 

What are the problems that you are encountering with booting up? What are the 
hardware that you are running? 

Have a great day!

Heystek 

-
Heystek Grobler

0832721009
heystekgrob...@gmail.com





> On 13 Jun 2022, at 05:32, Wang  wrote:
> 
> Hello CASPER,
> 
> How's it going?I am currently using ROACH2.
> 
> However, there are always some problems when booting up, and I want to try 
> another Linux system.
> 
> I tried installing CentOS6.5 and Fedora23, but my computer couldn't install 
> it due to hardware problems. When I used Ubuntu14.04, my computer was very 
> slow, which affected my operation.
> 
> What version of Linux system can you recommend?
> 
> Thanks.
> 
> Regards.
> 
> Wang
> 
> 
> 
> -- 
> You received this message because you are subscribed to the Google Groups 
> "casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an 
> email to casper+unsubscr...@lists.berkeley.edu 
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> To view this discussion on the web visit 
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>  
> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/86e7ec24-1a8c-4965-b8e4-94f2b64b7ee0n%40lists.berkeley.edu?utm_medium=email_source=footer>.

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Re: [casper] Help with packing data

[Heystek Grobler]

Hey Andrew

Yes, you read correctly, it is 602 million data points. I perhaps thought that 
I might had to shorten the amount of data points. I played around and the bram 
can comfortably handle 6020 data points and that still gives me a decent sine 
wave if I plot it. 

I would I implement a lookup table for interest sake?

Thanks for the help! 

I really appreciate it! 

Heystek 

> On 26 Nov 2021, at 16:02, Andrew van der Byl  wrote:
> 
> Hi Heystek,
> 
> It's a Friday afternoon so perhaps my eyes are deceiving me, but it looks 
> like you are wanting to store 602 million data points in BRAM? don't think 
> you are going to have too much luck with that. You could generate a 
> relatively fine grained cosine wave and only store the first 1/4 wave of it. 
> When doing the lookup you can reuse the values (essentially just flipping or 
> swapping to form the remaining 2nd,3rd and 4th quarters) as needed to form a 
> full waveform. To change frequency you scale your counter value to skip 
> lookup entries (so essentially you work through the lookup faster and hence 
> get a shorter period sinusoid). This way you will use far less memory and can 
> generate different frequencies with the same lookup table. Amplitude can be 
> scaled as needed.
> 
> Hope this helps.
> 
> Regards,
> Andrew
> 
> On Fri, Nov 26, 2021 at 3:49 PM Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
> Hey Andrew
> 
> Thank you so much for the explanation. 
> 
> Is there a way to get around it by using a similar kind of block? Or should I 
> rethink the sine wave that I generated that makes use of 602 000 000 data 
> points? 
> 
> Thanks for the help!
> 
> Heystek   
> 
>> On 26 Nov 2021, at 15:46, Andrew Martens > <mailto:and...@sarao.ac.za>> wrote:
>> 
>> Hi Heystek
>> 
>> Simulink has a maximum BRAM size of 64k (16 bits address size). A 32 bit 
>> address size would equate to 4G addresses, which is far larger than the 
>> amount of BRAM available in the FPGA.
>> 
>> Regards
>> Andrew
>> 
>> On Fri, Nov 26, 2021 at 3:40 PM Heystek Grobler > <mailto:heystekgrob...@gmail.com>> wrote:
>> Hey everyone. 
>> 
>> I have one last question regarding the BRAM. For my application I need an 
>> address width of 32, but I get the error that  the maximum allowable address 
>> width is 16. Is there away around this problem or a way to get the BRAM to 
>> use an address width of 32? 
>> 
>> Thanks for the help!
>> 
>> Heystek 
>> 
>>> On 25 Nov 2021, at 21:28, Dan Werthimer >> <mailto:d...@ssl.berkeley.edu>> wrote:
>>> 
>>> 
>>> hi morag. 
>>> 
>>> thanks for helping everyone.
>>> 
>>> best wishes,
>>> 
>>> dan
>>> 
>>> 
>>> 
>>> 
>>> On Thu, Nov 25, 2021 at 11:25 AM Morag Brown >> <mailto:mbr...@sarao.ac.za>> wrote:
>>> Happy to help :)
>>> 
>>> On Thu, Nov 25, 2021 at 9:19 PM Heystek Grobler >> <mailto:heystekgrob...@gmail.com>> wrote:
>>> Hey Morag! 
>>> 
>>> Know I understand! 
>>> 
>>> It is working. 
>>> 
>>> 
>>> 
>>> Thank you so much for the help!!! 
>>> 
>>> Heystek 
>>> 
>>>> On 25 Nov 2021, at 21:08, Morag Brown >>> <mailto:mbr...@sarao.ac.za>> wrote:
>>>> 
>>>> Hi Heystek,
>>>> 
>>>> Great!
>>>> 
>>>> I think Jack mentioned in an earlier email that the maximum number that 
>>>> can be represented by a <32,31> fixed point system is 1 - 2^-31. Reducing 
>>>> the magnitude of your sinusoid so that the peak value is below this 
>>>> maximum would work. Or alternatively, scaling your values by an amount 
>>>> less than 2^31 would have the same effect.
>>>> 
>>>> Morag
>>>> 
>>>> On Thu, Nov 25, 2021 at 8:59 PM Heystek Grobler >>> <mailto:heystekgrob...@gmail.com>> wrote:
>>>> Hey Morag
>>>> 
>>>> That worked! 
>>>> 
>>>> When I read the packed sine wave from the BRAM, unpack it and plot it, I 
>>>> get this:
>>>> 
>>>> 
>>>> 
>>>> I assume there is one data point that is causing problems at 1 or -1 that 
>>>> is overflowing? Any idea how I can fix that? 
>>>> 
>>>> Heystek 
>>>> 
>>>>> On 25 Nov 2021, at 20:22, Morag Brown >>>> <mail

Re: [casper] Help with packing data

[Heystek Grobler]

Hey Andrew

Thank you so much for the explanation. 

Is there a way to get around it by using a similar kind of block? Or should I 
rethink the sine wave that I generated that makes use of 602 000 000 data 
points? 

Thanks for the help!

Heystek   

> On 26 Nov 2021, at 15:46, Andrew Martens  wrote:
> 
> Hi Heystek
> 
> Simulink has a maximum BRAM size of 64k (16 bits address size). A 32 bit 
> address size would equate to 4G addresses, which is far larger than the 
> amount of BRAM available in the FPGA.
> 
> Regards
> Andrew
> 
> On Fri, Nov 26, 2021 at 3:40 PM Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
> Hey everyone. 
> 
> I have one last question regarding the BRAM. For my application I need an 
> address width of 32, but I get the error that  the maximum allowable address 
> width is 16. Is there away around this problem or a way to get the BRAM to 
> use an address width of 32? 
> 
> Thanks for the help!
> 
> Heystek 
> 
>> On 25 Nov 2021, at 21:28, Dan Werthimer > <mailto:d...@ssl.berkeley.edu>> wrote:
>> 
>> 
>> hi morag. 
>> 
>> thanks for helping everyone.
>> 
>> best wishes,
>> 
>> dan
>> 
>> 
>> 
>> 
>> On Thu, Nov 25, 2021 at 11:25 AM Morag Brown > <mailto:mbr...@sarao.ac.za>> wrote:
>> Happy to help :)
>> 
>> On Thu, Nov 25, 2021 at 9:19 PM Heystek Grobler > <mailto:heystekgrob...@gmail.com>> wrote:
>> Hey Morag! 
>> 
>> Know I understand! 
>> 
>> It is working. 
>> 
>> 
>> 
>> Thank you so much for the help!!! 
>> 
>> Heystek 
>> 
>>> On 25 Nov 2021, at 21:08, Morag Brown >> <mailto:mbr...@sarao.ac.za>> wrote:
>>> 
>>> Hi Heystek,
>>> 
>>> Great!
>>> 
>>> I think Jack mentioned in an earlier email that the maximum number that can 
>>> be represented by a <32,31> fixed point system is 1 - 2^-31. Reducing the 
>>> magnitude of your sinusoid so that the peak value is below this maximum 
>>> would work. Or alternatively, scaling your values by an amount less than 
>>> 2^31 would have the same effect.
>>> 
>>> Morag
>>> 
>>> On Thu, Nov 25, 2021 at 8:59 PM Heystek Grobler >> <mailto:heystekgrob...@gmail.com>> wrote:
>>> Hey Morag
>>> 
>>> That worked! 
>>> 
>>> When I read the packed sine wave from the BRAM, unpack it and plot it, I 
>>> get this:
>>> 
>>> 
>>> 
>>> I assume there is one data point that is causing problems at 1 or -1 that 
>>> is overflowing? Any idea how I can fix that? 
>>> 
>>> Heystek 
>>> 
>>>> On 25 Nov 2021, at 20:22, Morag Brown >>> <mailto:mbr...@sarao.ac.za>> wrote:
>>>> 
>>>> Hi Heystek,
>>>> 
>>>> You would need to increase the BRAM depth to one that can store all your 
>>>> data - currently, because the address width is 10, it can only store 2^10 
>>>> (1024) points and you're trying to write 6020. So you would need to 
>>>> increase the address width to an appropriate size. 
>>>> 
>>>> Morag
>>>> 
>>>> On Thu, Nov 25, 2021 at 8:05 PM Heystek Grobler >>> <mailto:heystekgrob...@gmail.com>> wrote:
>>>> Hey Morag
>>>> 
>>>> The BRAM has an address width 10 and a data width of 32. 
>>>> 
>>>> Should I increase it?
>>>> 
>>>> Heystek 
>>>> 
>>>>> On 25 Nov 2021, at 19:52, Morag Brown >>>> <mailto:mbr...@sarao.ac.za>> wrote:
>>>>> 
>>>>> Hi Heystek,
>>>>> 
>>>>> How big is the BRAM in your design? Does it have enough space to 
>>>>> accommodate the amount of data you're trying to write to it?
>>>>> 
>>>>> Morag
>>>>> 
>>>>> On Thu, Nov 25, 2021 at 6:59 PM Heystek Grobler >>>> <mailto:heystekgrob...@gmail.com>> wrote:
>>>>> Hey Morag and Jack
>>>>> 
>>>>> Thank you for the suggestions. 
>>>>> 
>>>>> I played around a little bit. if I create the sine wave the same as you 
>>>>> Morag, then it works. I am able to write it to the bram, read it back 
>>>>> from the bram, unpack it and get the same signal back. As soon as I use 
>>>>> the sine wave that I require for my application, then it breaks again

Re: [casper] Help with packing data

[Heystek Grobler]

Hey everyone. 

I have one last question regarding the BRAM. For my application I need an 
address width of 32, but I get the error that  the maximum allowable address 
width is 16. Is there away around this problem or a way to get the BRAM to use 
an address width of 32? 

Thanks for the help!

Heystek 

> On 25 Nov 2021, at 21:28, Dan Werthimer  wrote:
> 
> 
> hi morag. 
> 
> thanks for helping everyone.
> 
> best wishes,
> 
> dan
> 
> 
> 
> 
> On Thu, Nov 25, 2021 at 11:25 AM Morag Brown  <mailto:mbr...@sarao.ac.za>> wrote:
> Happy to help :)
> 
> On Thu, Nov 25, 2021 at 9:19 PM Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
> Hey Morag! 
> 
> Know I understand! 
> 
> It is working. 
> 
> 
> 
> Thank you so much for the help!!! 
> 
> Heystek 
> 
>> On 25 Nov 2021, at 21:08, Morag Brown > <mailto:mbr...@sarao.ac.za>> wrote:
>> 
>> Hi Heystek,
>> 
>> Great!
>> 
>> I think Jack mentioned in an earlier email that the maximum number that can 
>> be represented by a <32,31> fixed point system is 1 - 2^-31. Reducing the 
>> magnitude of your sinusoid so that the peak value is below this maximum 
>> would work. Or alternatively, scaling your values by an amount less than 
>> 2^31 would have the same effect.
>> 
>> Morag
>> 
>> On Thu, Nov 25, 2021 at 8:59 PM Heystek Grobler > <mailto:heystekgrob...@gmail.com>> wrote:
>> Hey Morag
>> 
>> That worked! 
>> 
>> When I read the packed sine wave from the BRAM, unpack it and plot it, I get 
>> this:
>> 
>> 
>> 
>> I assume there is one data point that is causing problems at 1 or -1 that is 
>> overflowing? Any idea how I can fix that? 
>> 
>> Heystek 
>> 
>>> On 25 Nov 2021, at 20:22, Morag Brown >> <mailto:mbr...@sarao.ac.za>> wrote:
>>> 
>>> Hi Heystek,
>>> 
>>> You would need to increase the BRAM depth to one that can store all your 
>>> data - currently, because the address width is 10, it can only store 2^10 
>>> (1024) points and you're trying to write 6020. So you would need to 
>>> increase the address width to an appropriate size. 
>>> 
>>> Morag
>>> 
>>> On Thu, Nov 25, 2021 at 8:05 PM Heystek Grobler >> <mailto:heystekgrob...@gmail.com>> wrote:
>>> Hey Morag
>>> 
>>> The BRAM has an address width 10 and a data width of 32. 
>>> 
>>> Should I increase it?
>>> 
>>> Heystek 
>>> 
>>>> On 25 Nov 2021, at 19:52, Morag Brown >>> <mailto:mbr...@sarao.ac.za>> wrote:
>>>> 
>>>> Hi Heystek,
>>>> 
>>>> How big is the BRAM in your design? Does it have enough space to 
>>>> accommodate the amount of data you're trying to write to it?
>>>> 
>>>> Morag
>>>> 
>>>> On Thu, Nov 25, 2021 at 6:59 PM Heystek Grobler >>> <mailto:heystekgrob...@gmail.com>> wrote:
>>>> Hey Morag and Jack
>>>> 
>>>> Thank you for the suggestions. 
>>>> 
>>>> I played around a little bit. if I create the sine wave the same as you 
>>>> Morag, then it works. I am able to write it to the bram, read it back from 
>>>> the bram, unpack it and get the same signal back. As soon as I use the 
>>>> sine wave that I require for my application, then it breaks again. 
>>>> 
>>>> Here is what I achieved using your sine wave Morag (ps iI changed my 
>>>> design to 32 bit):
>>>> 
>>>> 
>>>> 
>>>> 
>>>> 
>>>> 
>>>> 
>>>> 
>>>> When I use my sign wave, then it does not work:
>>>> 
>>>> 
>>>> 
>>>> 
>>>> 
>>>> 
>>>> 
>>>> 
>>>> 
>>>> The only thing that changed is the sine wave. is there something that I am 
>>>> missing? 
>>>> 
>>>> Thanks for the help! I really appreciate it! 
>>>> 
>>>> Heystek 
>>>> 
>>>> 
>>>>> On 25 Nov 2021, at 14:57, Morag Brown >>>> <mailto:mbr...@sarao.ac.za>> wrote:
>>>>> 
>>>>> I think that's because the functions used in both In[15] and In[16] do 
>>>>> the same thing. See the screenshots below to see what I mean. So you 
>>>>> construct the raw bytes data in In[15] and then 

Re: [casper] Help with packing data

[Heystek Grobler]

Hey Morag

The BRAM has an address width 10 and a data width of 32. 

Should I increase it?

Heystek 

> On 25 Nov 2021, at 19:52, Morag Brown  wrote:
> 
> Hi Heystek,
> 
> How big is the BRAM in your design? Does it have enough space to accommodate 
> the amount of data you're trying to write to it?
> 
> Morag
> 
> On Thu, Nov 25, 2021 at 6:59 PM Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
> Hey Morag and Jack
> 
> Thank you for the suggestions. 
> 
> I played around a little bit. if I create the sine wave the same as you 
> Morag, then it works. I am able to write it to the bram, read it back from 
> the bram, unpack it and get the same signal back. As soon as I use the sine 
> wave that I require for my application, then it breaks again. 
> 
> Here is what I achieved using your sine wave Morag (ps iI changed my design 
> to 32 bit):
> 
> 
> 
> 
> 
> 
> 
> 
> When I use my sign wave, then it does not work:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> The only thing that changed is the sine wave. is there something that I am 
> missing? 
> 
> Thanks for the help! I really appreciate it! 
> 
> Heystek 
> 
> 
>> On 25 Nov 2021, at 14:57, Morag Brown > <mailto:mbr...@sarao.ac.za>> wrote:
>> 
>> I think that's because the functions used in both In[15] and In[16] do the 
>> same thing. See the screenshots below to see what I mean. So you construct 
>> the raw bytes data in In[15] and then try to pack that as an integer in 
>> In]16}, which won't work because struct.pack('>i',A_y) expects data of type 
>> int while you're actually giving it data of type bytes. To pack the data 
>> using struct.pack() you would need to pass it an int (or array of ints and 
>> tell it how many points you're packing). I think (someone please correct me 
>> if I'm wrong) that you only need to do one or the other to get the correct 
>> raw data to be written to BRAM.
>> 
>> 
>> 
>> 
>> I also see you're scaling up by 2^31, but I think your BRAM is data width is 
>> 16 bits, so you'd likely want to scale by 2^15?
>> 
>> Morag
>> 
>> On Thu, Nov 25, 2021 at 12:46 PM Heystek Grobler > <mailto:heystekgrob...@gmail.com>> wrote:
>> Hey Jack and Morag
>> 
>> thank you for the advice and help! i am still getting errors and is stuck. 
>> Below is the new errors:
>> 
>> 
>> 
>> 
>> 
>> I have also attached the new script I am working on. 
>> 
>> Could it be that I am generating the sine wave incorrectly? I have about 600 
>> 000 000 points that I am working with. 
>> 
>> I keep getting “cannot convert argument to integer when running struct.pack.
>> 
>> Thanks for the help!
>> 
>> Heystek 
>> 
>> 
>>> On 23 Nov 2021, at 14:31, Jack Hickish >> <mailto:jackhick...@gmail.com>> wrote:
>>> 
>>> Hi Heystek,
>>> 
>>> Assuming your BRAM is set for 32-bit wide, you probably want to be writing 
>>> the values with 31 bits below the binary point -- i.e. normalized to the 
>>> range [-1, 1)  (aka simulink FIx32_31). In this case the packed values 
>>> would be:
>>> 
>>> struct.pack('>i', int(floating_point_sine_value * 2**31))
>>> 
>>> Though, be careful, because +1.0 isn't included in this number 
>>> representation (the maximum is 1 - 2**-31) , so you might want to include 
>>> some saturation logic (or scale up by a value less than 2**31).
>>> 
>>> For what it's worth, you can pack an entire numpy array with: 
>>> floating_point_numpy_array.astype('>i').tobytes() ,which saves looping and 
>>> appending to a binary string.
>>> 
>>> Does that help?
>>> 
>>> Cheers
>>> Jack
>>> 
>>> On Mon, 22 Nov 2021 at 18:10, Heystek Grobler >> <mailto:heystekgrob...@gmail.com>> wrote:
>>> Hey Jack
>>> 
>>> I am also well thank you. We are starting to go back to the observatory 
>>> (HartRAO) again. 
>>> 
>>> Here is  a snippets of the python code that I am using as well as my 
>>> simulink design:
>>> 
>>> The first nipped is where I create the sine wave:
>>> 
>>> The second snipped is where I plot the sine wave:
>>> 
>>> 
>>> The third snipped is where I pack the sine wave array:
>>> 
>>> 
>>> The fourth snipped is where I write the packed data to the BRAM:
>>> 
>>> 
>>> Snipped 5 is where I want to use

Re: [casper] Help to program BRAM blocks.

[Heystek Grobler]

Good day everyone

I have spent some time on this and it comes down to one final error. It seems 
that I am not packing the array correctly in binary form. 

I have used these methods:

sinA_x=np.arange(0,2*np.pi,step_size)
sinA_y=np.sin(sinA_x)
sinA_y

array_l=len(sinA_y)

ss0 = []
for i in a_sin[0:array_l:10]:
ss0.append(i)

#sp0 = struct.pack('%f',ss0)
#sp0 = struct.pack('%sf' % len(ss0), *ss0)
#sp0 = struct.pack(f'{len(ss0)}f', *ss0)
#sp0 = struct.pack('f' * len(ss0), *ss0)
#sp0 = struct.pack('f' * len(ss0), *ss0)
#sp0 = struct.pack(str(len(ss0)) + 'f', *ss0)
#sp0 = struct.pack("{0}f".format(len(ss0)), *ss0)
#sp0 = struct.pack("%sf" % len(ss0), *ss0)
#sp0 = struct.pack(f'{len(ss0)}f', *ss0)

buf = bytes()
for val in ss0:
   buf += struct.pack('f', val)

Then I use:

fpga.write('bram_a_sin',buf,0)

But I keep getting the following error:

KatcpRequestFail  Traceback (most recent call last)
 in ()
> 1 fpga.write('bram_a_sin',buf,0)

/home/dserver/anaconda2/lib/python2.7/site-packages/casperfpga/casperfpga.pyc 
in write(self, device_name, data, offset)
227 :return:
228 """
--> 229 self.blindwrite(device_name, data, offset)
230 new_data = self.read(device_name, len(data), offset)
231 if new_data != data:

/home/dserver/anaconda2/lib/python2.7/site-packages/casperfpga/katcp_fpga.pyc 
in blindwrite(self, device_name, data, offset)
269 self.katcprequest(name='write', request_timeout=self._timeout,
270   require_ok=True,
--> 271   request_args=(device_name, str(offset), data))
272 
273 def bulkread(self, device_name, size, offset=0):

/home/dserver/anaconda2/lib/python2.7/site-packages/casperfpga/katcp_fpga.pyc 
in katcprequest(self, name, request_timeout, require_ok, request_args)
161 'Request %s on host %s failed.\n\t'
162 'Request: %s\n\tReply: %s' %
--> 163 (request.name, self.host, request, reply))
164 elif reply.arguments[0] == katcp.Message.INVALID:
165 raise KatcpRequestInvalid(

KatcpRequestFail: Request write on host 192.168.33.11 failed.
Am I missing the way the array should be packed? All that I want to to do is to 
give a sine wave to the bram. 

Thank you for the help!

Heystek  

> On 19 Oct 2021, at 14:17, duanxuef...@xao.ac.cn wrote:
> 
> 
> Hi, Heystek,
> 
> I tried to use the Sine Wave module in the xilinx blockset to generate a 
> positive or cosine signal, and then use the casper snapshot module to read 
> the generated signal value and verify the result. I think you can start with 
> a simple example like this. the bram details are as David said.
> 
> Hope this helps,
> Duan
> 
> 段雪峰(Duan Xuefeng)
> 中国科学院新疆天文台
> Xinjiang Astronomical Observatory (XAO), CAS
> 乌鲁木齐市新市区科学一街150号，830011
> 150 Science 1-Street, Urumqi, 830011, China
> 电话(Tel):0991-3689068 15719983612 
> 
>  
> From: David Harold Edward MacMahon <mailto:dav...@berkeley.edu>
> Date: 2021-10-19 19:37
> To: casper <mailto:casper@lists.berkeley.edu>
> CC: fvdheever <mailto:fvdhee...@sarao.ac.za>
> Subject: Re: [casper] Help to program BRAM blocks.
> Hi, Heystek,
> 
> The CPU/KATCP/CasperFpga data path to the "Shared BRAM" is 32 bits wide, so 
> in the end you will be writing/sending an array of 32 bit integers.  The data 
> path on the FPGA side of the "shared BRAM" may be wider (e.g. 64 bits) or 
> narrower (e.g  8 or 16 bits) or the same (i.e. 32 bits).  Thing are most 
> straightforward when the FPGA data path is 32 bits since location 0 is the 
> same for either side, but one important detail is that the values in the 
> Shared BRAM are stored in "big endian" format (aka "network byte order"), 
> which is opposite from the x86_64 convention.  When the widths differ between 
> the two sides, some care is required to ensure that the data is ordered 
> properly to get the desired output order.  The "Block RAM Address Mapping" 
> section of UG363 
> (https://www.xilinx.com/content/dam/xilinx/support/documentation/user_guides/ug363.pdf
>  
> <https://www.xilinx.com/content/dam/xilinx/support/documentation/user_guides/ug363.pdf>)
>  describes this mapping.  The one detail that is not covered there is when 
> the FPGA data port is 64 bits wide.  In that case, you need to convert the 
> 64-bit value to big endian, but then swap the low 32-bits and high-32 bits, 
> though sometimes the gateware designer will be "clever" and do this swap for 
> you (which is convenient if you know about it).
> 
> Hope this helps,
> Dave
> 
>> On Oct 19, 2021

[casper] Help to program BRAM blocks.

[Heystek Grobler]

Good day everyone.

I was hoping that someone can perhaps help me or can point me in the right
direction.

I want to write sine and cosine waves to BRAM blocks in order to implement
a local oscillator. I have a basic idea of how to do this by making use of
a struct that needs to be packed, but in practice I have not done this
before and can't seem to find a good example to follow.

Thank you for the help!

Heystek

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Re: [casper] Weird python problem

[Heystek Grobler]

Hey Mike

Thanks for your reply. I have tried that as well. Even if I run it straight out 
of the home directory it still gives the same error.  This have been 
frustrating me for the last week. 

Heystek 

> On 04 Sep 2020, at 12:40, Michael D'Cruze  
> wrote:
> 
> Hi Heystek,
>  
> I haven’t seen this before. Is there anything in your working directory that 
> the import statement could be confusing with your desired module? Perhaps try 
> changing your working directory. 
>  
> GL
> Mike
>  
> From: Heystek Grobler [mailto:heystekgrob...@gmail.com] 
> Sent: 04 September 2020 11:37
> To: 'Siddharth Savyasachi Malu' via casper@lists.berkeley.edu
> Subject: [casper] Weird python problem
>  
> Good day everyone. 
>  
> I have encountered a weird problem. I have a python script that makes use of 
> pylab. When importinf pylab, I get this error:
>  
> PyUnicodeUCS4_FromString
> 
> 
> I have tried to use import matplotlib.pyplot as plt and I get the same error. 
> I have googled it, but nothing seems to help. 
> 
> 
> I am using python 2.7
> 
> 
> Thanks for the help. 
> 
> 
> Heystek 
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[casper] Weird python problem

[Heystek Grobler]

Good day everyone. 

I have encountered a weird problem. I have a python script that makes use of 
pylab. When importinf pylab, I get this error:

PyUnicodeUCS4_FromString

I have tried to use import matplotlib.pyplot as plt and I get the same error. I 
have googled it, but nothing seems to help. 

I am using python 2.7

Thanks for the help. 

Heystek 

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Re: [casper] Help with timing constraint

[Heystek Grobler]

Hey Andrew and James and everyone.

After probed around and the following timing constraint is not met:

TS_sys_clk_n

I assume that my system clock is not running at an appropriate frequency?

Thanks for the help!

Heystek



On Wed, Aug 26, 2020 at 10:59 AM Andrew Martens  wrote:

> Hi Heystek
>
> Output reports and their location change over versions, between ISE and
> Vivado etc. I think the output reports for ISE are located in the
> 'implementation' folder. I think the timing related ones have 'timing' in
> the name... A quick Google search of the error will help.
>
> Note that there are archives of the mailing list available at
> https://www.mail-archive.com/casper@lists.berkeley.edu/ - your problem
> has probably been answered already previously.
>
> Regards
> Andrew
>
> On Wed, Aug 26, 2020 at 10:49 AM Andrew van der Byl 
> wrote:
>
>> Hi Heystek,
>>
>> It's possible that you then have another issue that causes the build
>> process to exit prior to generating that file. You'll need to debug that
>> first.
>>
>> Regards,
>> Andrew
>>
>> On Wed, Aug 26, 2020 at 10:40 AM Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hey Andrew
>>>
>>> It is strange, I cant seem to locate top_timing_summary_routed.rpt
>>>
>>> I am running Matlab 2012B with ISE 14.7
>>>
>>>
>>>
>>> On 26 Aug 2020, at 10:27, Andrew van der Byl  wrote:
>>>
>>> Hi Heystek,
>>>
>>> 1) Navigate to your project folder
>>> 2) Then go to and open: /myproj/myproj.runs/impl_1/
>>> top_timing_summary_routed.rpt
>>>
>>> Just a note - this file is usually fairly large as text files go ~20MB.
>>>
>>> Regards,
>>> Andrew
>>>
>>> On Wed, Aug 26, 2020 at 10:22 AM Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>>
>>>> Hey James and Andrew
>>>>
>>>> Thank you so much for the advice!
>>>>
>>>> @Andrew, this might be a stupid question, but where do I locate the 
>>>> top_timing_summary_routed.rpt
>>>> file?
>>>>
>>>> Heystek
>>>>
>>>>
>>>> On 26 Aug 2020, at 10:17, Andrew van der Byl  wrote:
>>>>
>>>> Hi Heystek,
>>>>
>>>> Have a look in top_timing_summary_routed.rpt and search for 'VIOLATED'
>>>> - this usually shows up which paths are hurting your design. Then, as James
>>>> said, start pipeling your design.
>>>>
>>>> Hope this helps.
>>>>
>>>> Regards,
>>>> Andrew
>>>>
>>>> On Wed, Aug 26, 2020 at 10:13 AM James Smith  wrote:
>>>>
>>>>> Hello Heystek,
>>>>>
>>>>> You will have to go through the timing reports and see which signal
>>>>> path is failing timing, and by how much.
>>>>>
>>>>> Once you have an idea, you will need to sprinkle delay blocks and / or
>>>>> adjust latencies in your logic to get to a point where the place-and-route
>>>>> can find a layout that satisfies timing requirements.
>>>>>
>>>>> It's a bit of a black art, always hit and miss for me.
>>>>>
>>>>> Regards,
>>>>> James
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler <
>>>>> heystekgrob...@gmail.com> wrote:
>>>>>
>>>>>> Good day everyone
>>>>>>
>>>>>> I am running a design but ran into this problem:
>>>>>>
>>>>>> xflow done!
>>>>>> touch __xps/system_routed
>>>>>> xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl
>>>>>> -error yes implementation/system.par
>>>>>> Analyzing implementation/system.par
>>>>>>
>>>>>> 
>>>>>> ERROR: 1 constraint not met.
>>>>>>
>>>>>> PAR could not meet all timing constraints. A bitstream will not be
>>>>>> generated.
>>>>>>
>>>>>> To disable the PAR timing check:
>>>>>>
>>>>>> 1> Disable the "Treat timing closure failure as error" option from
>>>>>> the Project Options dialog 

Re: [casper] Help with timing constraint

[Heystek Grobler]

Hey Andrew

It is strange, I cant seem to locate top_timing_summary_routed.rpt

I am running Matlab 2012B with ISE 14.7 



> On 26 Aug 2020, at 10:27, Andrew van der Byl  wrote:
> 
> Hi Heystek,
> 
> 1) Navigate to your project folder
> 2) Then go to and open: 
> /myproj/myproj.runs/impl_1/top_timing_summary_routed.rpt
> 
> Just a note - this file is usually fairly large as text files go ~20MB.
> 
> Regards,
> Andrew
> 
> On Wed, Aug 26, 2020 at 10:22 AM Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
> Hey James and Andrew
> 
> Thank you so much for the advice! 
> 
> @Andrew, this might be a stupid question, but where do I locate the 
> top_timing_summary_routed.rpt file? 
> 
> Heystek 
> 
> 
>> On 26 Aug 2020, at 10:17, Andrew van der Byl > <mailto:avd...@gmail.com>> wrote:
>> 
>> Hi Heystek,
>> 
>> Have a look in top_timing_summary_routed.rpt and search for 'VIOLATED' - 
>> this usually shows up which paths are hurting your design. Then, as James 
>> said, start pipeling your design.
>> 
>> Hope this helps.
>> 
>> Regards,
>> Andrew
>> 
>> On Wed, Aug 26, 2020 at 10:13 AM James Smith > <mailto:jsm...@ska.ac.za>> wrote:
>> Hello Heystek,
>> 
>> You will have to go through the timing reports and see which signal path is 
>> failing timing, and by how much.
>> 
>> Once you have an idea, you will need to sprinkle delay blocks and / or 
>> adjust latencies in your logic to get to a point where the place-and-route 
>> can find a layout that satisfies timing requirements.
>> 
>> It's a bit of a black art, always hit and miss for me.
>> 
>> Regards,
>> James
>> 
>> 
>> 
>> 
>> On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler > <mailto:heystekgrob...@gmail.com>> wrote:
>> Good day everyone
>> 
>> I am running a design but ran into this problem:
>> 
>> xflow done!
>> touch __xps/system_routed
>> xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl 
>> <http://observe_par.pl/> -error yes implementation/system.par
>> Analyzing implementation/system.par
>> 
>> ERROR: 1 constraint not met.
>> 
>> PAR could not meet all timing constraints. A bitstream will not be generated.
>> 
>> To disable the PAR timing check:
>> 
>> 1> Disable the "Treat timing closure failure as error" option from the 
>> Project Options dialog in XPS.
>> 
>> OR
>> 
>> 2> Type following at the XPS prompt:
>> XPS% xset enable_par_timing_error 0
>> 
>> system.make:140: recipe for target 'implementation/system.bit' failed
>> gmake: *** [implementation/system.bit] Error 1
>> ERROR:EDK -  
>>Error while running "gmake -f system.make bits".
>> 
>> It seems to be a timing constraint. 
>> 
>> How do I deal with this?
>> 
>> Thanks for the help! 
>> 
>> Heystek 
>> 
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Re: [casper] Help with timing constraint

[Heystek Grobler]

Hey James and Andrew

Thank you so much for the advice! 

@Andrew, this might be a stupid question, but where do I locate the 
top_timing_summary_routed.rpt file? 

Heystek 


> On 26 Aug 2020, at 10:17, Andrew van der Byl  wrote:
> 
> Hi Heystek,
> 
> Have a look in top_timing_summary_routed.rpt and search for 'VIOLATED' - this 
> usually shows up which paths are hurting your design. Then, as James said, 
> start pipeling your design.
> 
> Hope this helps.
> 
> Regards,
> Andrew
> 
> On Wed, Aug 26, 2020 at 10:13 AM James Smith  <mailto:jsm...@ska.ac.za>> wrote:
> Hello Heystek,
> 
> You will have to go through the timing reports and see which signal path is 
> failing timing, and by how much.
> 
> Once you have an idea, you will need to sprinkle delay blocks and / or adjust 
> latencies in your logic to get to a point where the place-and-route can find 
> a layout that satisfies timing requirements.
> 
> It's a bit of a black art, always hit and miss for me.
> 
> Regards,
> James
> 
> 
> 
> 
> On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
> Good day everyone
> 
> I am running a design but ran into this problem:
> 
> xflow done!
> touch __xps/system_routed
> xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl 
> <http://observe_par.pl/> -error yes implementation/system.par
> Analyzing implementation/system.par
> 
> ERROR: 1 constraint not met.
> 
> PAR could not meet all timing constraints. A bitstream will not be generated.
> 
> To disable the PAR timing check:
> 
> 1> Disable the "Treat timing closure failure as error" option from the 
> Project Options dialog in XPS.
> 
> OR
> 
> 2> Type following at the XPS prompt:
> XPS% xset enable_par_timing_error 0
> 
> system.make:140: recipe for target 'implementation/system.bit' failed
> gmake: *** [implementation/system.bit] Error 1
> ERROR:EDK -  
>Error while running "gmake -f system.make bits".
> 
> It seems to be a timing constraint. 
> 
> How do I deal with this?
> 
> Thanks for the help! 
> 
> Heystek 
> 
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[casper] Help with timing constraint

[Heystek Grobler]

Good day everyone

I am running a design but ran into this problem:

xflow done!
touch __xps/system_routed
xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl
-error yes implementation/system.par
Analyzing implementation/system.par

ERROR: 1 constraint not met.

PAR could not meet all timing constraints. A bitstream will not be
generated.

To disable the PAR timing check:

1> Disable the "Treat timing closure failure as error" option from the
Project Options dialog in XPS.

OR

2> Type following at the XPS prompt:
XPS% xset enable_par_timing_error 0

system.make:140: recipe for target 'implementation/system.bit' failed
gmake: *** [implementation/system.bit] Error 1
ERROR:EDK -
   Error while running "gmake -f system.make bits".

It seems to be a timing constraint.

How do I deal with this?

Thanks for the help!

Heystek

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Re: [casper] Installation of Matlab 2012B

[Heystek Grobler]

Hey everyone

Thank you so much for everyone's input and help.

After following everyone's advice, I got it working my making use of these
steps (for future use):

System: Ubuntu 18.04 server
Matlab 2012B

Steps:

#To setup the dummy interface

1. sudo modprobe dummy


#To see if the dummy interface is loaded

2. sudo lsmod | grep dummy


#Add the link eth0 to the dummy interface

3. sudo ip link add eth0 type dummy


#to make sure the link exists

4. ip link show eth0


#Assign MAC address to eth0

5. sudo ifconfig eth0 hw ether 0c:c4:7a:9a:ca:e6


#assign IP address to eth0

6. sudo ip address change dev eth0 10.0.0.1


#Link up to eth0

7. sudo ip link set dev eth0 up


#cjeck that the link is up

8. ifconfig


And it is working now.


Have a great day


Heystek


On Tue, Aug 18, 2020 at 5:44 PM Michael D'Cruze <
michael.dcr...@manchester.ac.uk> wrote:

> It may be of interest to someone in the future that, if you buy a Dell
> workstation with RHEL pre-installed, these solutions don’t work. Indeed
> this is what I originally tried to do. The problem appears to be that Dell
> have installed some sort of BIOS command to overrule any changes you make
> to the grub cfg file, or the interfaces list. In my case the only way to
> effect a change was to use the network config/manager command line utility.
>
>
>
> *From:* David MacMahon [mailto:dav...@berkeley.edu]
> *Sent:* 18 August 2020 16:00
> *To:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] Installation of Matlab 2012B
>
>
>
> The consistent albeit cryptic names like “enp0s5” might make life easier
> for automating Linux installations, but I don’t think they make life easier
> for sysadmins or power users. Fortunately, this naming scheme is optional
> and it’s easy to switch to the more human-friendly names by adding
> “net.ifnames=0” to the kernel command line (probably in some grub config
> file, depending on your distribution). You might also need
> “net.biosdevnames=0”.  Googling those terms plus your distro’s name will
> get you some relevant pages with more details.
>
>
>
> A rose by any other name would smell as sweet,
>
> Dave
>
>
>
> On Aug 18, 2020, at 04:00, James Smith  wrote:
>
> 
>
> Hi Heystek,
>
>
>
> Unfortunately not - I have had this in the past as well IIRC, some of the
> more modern Linux distributions will give you something like "en0s1" or the
> like. Matlab is stuck in the past, looking for eth0.
>
>
>
> It's easy enough to change the name, but bear in mind that you may have
> some funnies elsewhere that you will need to change as well (e.g. if you
> have /etc/network/interfaces - you'll need to update that too).
>
>
>
> Regards,
>
> james
>
>
>
>
>
> On Tue, Aug 18, 2020 at 10:51 AM Heystek Grobler 
> wrote:
>
> Hey Mike
>
>
>
> Thank you for your reply!
>
>
>
> On the Mathworks forums some of the folks suggest to “force” a name
> change. Apparently the license is looking for “eth0” but on my machine it
> is “em1”.  That is what is. causing the error.
>
>
>
> I was just wondering if there is perhaps a more elegant solution to this.
>
>
>
> Thanks for the help!
>
>
>
> Heystek
>
>
>
>
>
>
>
>
>
> On 18 Aug 2020, at 12:44, Michael D'Cruze 
> wrote:
>
>
>
> Hi Heystek,
>
>
>
> I’ve seen a similar thing recently installing ISE on a Linux 7 machine. It
> looks like a complaint about the naming convention of your primary NIC. You
> can force a name-change if you want using the network manager (I did it in
> RHEL, unsure about Ubuntu) but better to find a solution from Mathworks if
> you can. What does the indicated solution say?
>
>
>
> Good luck,
>
> Mike
>
>
>
>
>
> *From:* Heystek Grobler [mailto:heystekgrob...@gmail.com
> ]
> *Sent:* 18 August 2020 11:34
> *To:* Casper Lists
> *Subject:* [casper] Installation of Matlab 2012B
>
>
>
> Hello everyone
>
>
>
> I have a bit of a problem. The first time that I am experiencing it. I am
> trying to install Matlab 2012B on a Ubuntu machine (That I redid), but the
> installation gives this error:
>
>
>
> 
>
>
>
> Does anyone perhaps know how to fix this?
>
>
>
> Heystek
>
>
>
>
>
> --
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> casper@lists.berkeley.edu" group.
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Re: [casper] Installation of Matlab 2012B

[Heystek Grobler]

Hey Mike

Thank you for your reply! 

On the Mathworks forums some of the folks suggest to “force” a name change. 
Apparently the license is looking for “eth0” but on my machine it is “em1”.  
That is what is. causing the error. 

I was just wondering if there is perhaps a more elegant solution to this. 

Thanks for the help! 

Heystek 


 

> On 18 Aug 2020, at 12:44, Michael D'Cruze  
> wrote:
> 
> Hi Heystek,
>  
> I’ve seen a similar thing recently installing ISE on a Linux 7 machine. It 
> looks like a complaint about the naming convention of your primary NIC. You 
> can force a name-change if you want using the network manager (I did it in 
> RHEL, unsure about Ubuntu) but better to find a solution from Mathworks if 
> you can. What does the indicated solution say?
>  
> Good luck,
> Mike
>  
>  
> From: Heystek Grobler [mailto:heystekgrob...@gmail.com 
> <mailto:heystekgrob...@gmail.com>] 
> Sent: 18 August 2020 11:34
> To: Casper Lists
> Subject: [casper] Installation of Matlab 2012B
>  
> Hello everyone
>  
> I have a bit of a problem. The first time that I am experiencing it. I am 
> trying to install Matlab 2012B on a Ubuntu machine (That I redid), but the 
> installation gives this error:
>  
> 
>  
> Does anyone perhaps know how to fix this?
>  
> Heystek 
>  
>  
> -- 
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[casper] Installation of Matlab 2012B

[Heystek Grobler]

Hello everyone

I have a bit of a problem. The first time that I am experiencing it. I am
trying to install Matlab 2012B on a Ubuntu machine (That I redid), but the
installation gives this error:

[image: Screenshot from 2020-08-17 17-55-44.png]

Does anyone perhaps know how to fix this?

Heystek

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Re: [casper] Compiling design

[Heystek Grobler]

Hey Jack and Andrew

You were right. I literarily had one “Gateway In” block. I removed it and now 
my design compiles. 

Thank you for your help! I really appreciate it. 

Heystek 



> On 11 Aug 2020, at 16:51, Jack Hickish  wrote:
> 
> Hi Heystek,
> 
> Somewhere in your design -- presumably outside the screenshot you just sent 
> or inside one of your blocks -- you have a "Gateway In" block. This isn't 
> allowed (when you compile the design, the toolflow doesn't know what to drive 
> it with). If you find and delete this block, I think you'll be good to go.
> 
> Cheers
> Jack
> 
> On Tue, 11 Aug 2020 at 14:39, Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
> Hey James
> 
> Below is a snipped:
> 
> 
> 
>> On 11 Aug 2020, at 15:24, James Smith > <mailto:jsm...@ska.ac.za>> wrote:
>> 
>> Send a screen snip of what you've got, Heystek?
>> 
>> On Tue, Aug 11, 2020 at 1:22 PM Heystek Grobler > <mailto:heystekgrob...@gmail.com>> wrote:
>> Hey James and Mugundhan
>> 
>> Thank you for your emails. 
>> 
>> Yes, I have a Shared BRAM block in my design. The BRAM block is from the 
>> casper blockset. So I should rather use something else for the design?
>> 
>>> On 11 Aug 2020, at 15:03, James Smith >> <mailto:jsm...@ska.ac.za>> wrote:
>>> 
>>> Hello Heystek,
>>> 
>>> Somewhere in your design, you are trying to use a Xilinx block as an input. 
>>> Replace it with one of the yellow blocks from the Casper tools, and you 
>>> should be okay. (Usually this will be a software register or a BRAM block.)
>>> 
>>> Regards,
>>> James
>>> 
>>> 
>>> On Tue, Aug 11, 2020 at 12:54 PM Heystek Grobler >> <mailto:heystekgrob...@gmail.com>> wrote:
>>> Good day everyone
>>> 
>>> I am compiling a design for Roach2. I can into this error when running 
>>> casper_xps:
>>> 
>>> "xilinx input gateways cannot be used in a design. Only gpio blocks”
>>> 
>>> How can I solve this or am I doing something stupid?
>>> 
>>> Thanks for the help
>>> 
>>> Heystek 
>>> 
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>> 
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Re: [casper] Compiling design

[Heystek Grobler]

Hey James

Below is a snipped:



> On 11 Aug 2020, at 15:24, James Smith  wrote:
> 
> Send a screen snip of what you've got, Heystek?
> 
> On Tue, Aug 11, 2020 at 1:22 PM Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
> Hey James and Mugundhan
> 
> Thank you for your emails. 
> 
> Yes, I have a Shared BRAM block in my design. The BRAM block is from the 
> casper blockset. So I should rather use something else for the design?
> 
>> On 11 Aug 2020, at 15:03, James Smith > <mailto:jsm...@ska.ac.za>> wrote:
>> 
>> Hello Heystek,
>> 
>> Somewhere in your design, you are trying to use a Xilinx block as an input. 
>> Replace it with one of the yellow blocks from the Casper tools, and you 
>> should be okay. (Usually this will be a software register or a BRAM block.)
>> 
>> Regards,
>> James
>> 
>> 
>> On Tue, Aug 11, 2020 at 12:54 PM Heystek Grobler > <mailto:heystekgrob...@gmail.com>> wrote:
>> Good day everyone
>> 
>> I am compiling a design for Roach2. I can into this error when running 
>> casper_xps:
>> 
>> "xilinx input gateways cannot be used in a design. Only gpio blocks”
>> 
>> How can I solve this or am I doing something stupid?
>> 
>> Thanks for the help
>> 
>> Heystek 
>> 
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Re: [casper] Compiling design

[Heystek Grobler]

Hey James and Mugundhan

Thank you for your emails. 

Yes, I have a Shared BRAM block in my design. The BRAM block is from the casper 
blockset. So I should rather use something else for the design?

> On 11 Aug 2020, at 15:03, James Smith  wrote:
> 
> Hello Heystek,
> 
> Somewhere in your design, you are trying to use a Xilinx block as an input. 
> Replace it with one of the yellow blocks from the Casper tools, and you 
> should be okay. (Usually this will be a software register or a BRAM block.)
> 
> Regards,
> James
> 
> 
> On Tue, Aug 11, 2020 at 12:54 PM Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
> Good day everyone
> 
> I am compiling a design for Roach2. I can into this error when running 
> casper_xps:
> 
> "xilinx input gateways cannot be used in a design. Only gpio blocks”
> 
> How can I solve this or am I doing something stupid?
> 
> Thanks for the help
> 
> Heystek 
> 
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[casper] Compiling design

[Heystek Grobler]

Good day everyone

I am compiling a design for Roach2. I can into this error when running 
casper_xps:

"xilinx input gateways cannot be used in a design. Only gpio blocks”

How can I solve this or am I doing something stupid?

Thanks for the help

Heystek 

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Re: [casper] Measuring a FFT in Simulink

[Heystek Grobler]

Hey James 

I thought of the “to workspace” sink. I am not to familiar to write from 
Simulink to the workspace, but I will give it a go! Thanks for the help. 

Out of curiosity, if I have both halves of the symmetric FFT, what would be an 
application do to another FFT? I have written an Matlab script to play around 
with this idee. When I run the script, the the FFT of an FFT gives me a time 
domain signal, but the result has a larges amplitude. When I do a 3rd FFT I get 
the frequency domain again, and it is also amplified. 

It is just something that I picked up. 

Heystek  

> On 23 Apr 2020, at 11:51, James Smith  wrote:
> 
> Hello Heystek,
> 
> You can probably use a "to workspace" sink, then you'll be able to display 
> the data however you want in some matlab code once the simulation is finished 
> running.
> 
> Canonically, just applying an FFT to frequency-domain data will get you back 
> into the time domain, multiplied by some scaling factor. You need both halves 
> of the symmetric FFT though, so the output of e.g. the fft_wideband_real 
> wouldn't be meaningful to apply another FFT to it.
> 
> Regards,
> James
> 
> 
> 
> 
> On Thu, Apr 23, 2020 at 9:40 AM Heystek Grobler  <mailto:heystekgrob...@gmail.com>> wrote:
> Good day Casperites 
> 
> I have an interesting question. I am using a  FFT in simulink for the use in 
> a spectrometer design. I want to test the output of the FFT by using some 
> kind of scope. Simulink only has spectrum scope, that would be perfect, but 
> the scope does a second FFT on the signal. The other option is a vector 
> scope, but that does not give the result that I am looking for. 
> 
> Does anyone have a suggestion on how I can see the results of the FFT in 
> simulink? 
> 
> Then I have another question. What would be expected if I do a FFT on a FFT? 
> As far as I can figure out, the FFT of the FFT should just be time reversed? 
> 
> Thanks for the help! 
> 
> Heystek 
> 
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[casper] Measuring a FFT in Simulink

[Heystek Grobler]

Good day Casperites 

I have an interesting question. I am using a  FFT in simulink for the use in a 
spectrometer design. I want to test the output of the FFT by using some kind of 
scope. Simulink only has spectrum scope, that would be perfect, but the scope 
does a second FFT on the signal. The other option is a vector scope, but that 
does not give the result that I am looking for. 

Does anyone have a suggestion on how I can see the results of the FFT in 
simulink? 

Then I have another question. What would be expected if I do a FFT on a FFT? As 
far as I can figure out, the FFT of the FFT should just be time reversed? 

Thanks for the help! 

Heystek 

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Re: [casper] Issues with setting up a ROACH2

[Heystek Grobler]

Hey Michael

Did you try this procedure?

https://casper.ssl.berkeley.edu/wiki/ROACH_kernel_uboot_update

Did you manage to solve it?

Heystek

On Fri, Mar 15, 2019 at 5:45 PM Michael Peel  wrote:

> Hi all,
>
> I’m currently trying to set up a ROACH2 (for the first time), and have run
> into a number of problems. The bottom line is that I’m currently getting
> this memory error message:
>
> U-Boot 2011.06-rc2-0-g2694c9d-dirty (Dec 04 2013 - 20:58:06)
> CPU: AMCC PowerPC 440EPx Rev. A at 533.333 MHz (PLB=133 OPB=66 EBC=66)
>  No Security/Kasumi support
>  Bootstrap Option C - Boot ROM Location EBC (16 bits)
>  32 kB I-Cache 32 kB D-Cache
> Board: ROACH2
> I2C: ready
> DRAM: 512 MiB
> Memory error at , wrote , read 273218ff !
>
> This follows from the casperfpga software being able to connect to the
> ROACH2, but unable to load the .fpg file onto it. That led to me attempting
> to update the romfs using ‘run tftproot’, but it could not get an IP
> address from the computer (DHCP/dnsmasq configuration issues on RHEL7 that
> I still need to figure out), so it did not run the update. However, after
> that I got a kernel panic on the onboard software, so the roach no longer
> got to the login stage.
>
> I then created a USB boot drive using:
>
> https://github.com/ska-sa/roach2_nfs_uboot/blob/master/roach2-debian-fs-snapshot-24-10-2012.tar.gz
> and tried to boot the roach from that, however it stalled during the boot
> process, and on reset I got the above error message.
>
> Any suggestions?
>
> Thanks,
> Mike
>
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Re: [casper] ROACH2 compile error

[Heystek Grobler]

Hey Jack and Adam

https://github.com/casper-astro/mlib_devel/issues/7



That is the exact error I can into


Heystek

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Re: [casper] ROACH2 compile error

[Heystek Grobler]

Hey Adam and Jack

I mannaged to solve the problem. The GPIO block for was set for the wrong
platform. It was set on ROACH1 and not ROACH2.

Thanks for all the help!

Heystek

On Sat, Mar 9, 2019 at 12:27 AM Jack Hickish  wrote:

> Hi Heystek,
>
> Adam's right. I think this is potentially a bug in the tool flow's
> auto-generated ROACH2 UCF file. Which is weird. Either that or your GPIO
> block is misconfigured, though I'm not sure off the top of my head what
> this would be. Can you send me your model (preferably a GitHub link) and an
> mlib_devel git hash for the version of the library you're using?
>
> Cheers
> Jack
>
> On Fri, 8 Mar 2019 at 01:15, Heystek Grobler 
> wrote:
>
>> Hey Franco and Jack
>>
>> I have cheked that I have done the post install "fixes"
>>
>> I have traced the error to these:
>>
>> ERROR:NgdBuild:488 - Attribute value "LVCMOS33" is not an accepted value
>> for
>>attribute "IOSTANDARD" on "r2wb640mhz_roach_gpio_a_enable_not_ext<0>".
>> ERROR:NgdBuild:488 - Attribute value "LVCMOS33" is not an accepted value
>> for
>>attribute "IOSTANDARD" on "r2wb640mhz_roach_gpio_b_enable_not_ext<0>".
>>
>> Do you perhaps know how I can fix this?
>>
>> Heystek
>>
>>
>> On Thu, Mar 7, 2019 at 2:12 AM Jack Hickish 
>> wrote:
>>
>>> Hi Heystek,
>>>
>>> In addition to Franco's point about post-installation tweaks, you might
>>> find more information if you look up above the "Number of errors: 2", where
>>> [hopefully] there will be more specific error messages.
>>>
>>> Cheers
>>> Jack
>>>
>>> On Wed, 6 Mar 2019 at 09:47, Franco  wrote:
>>>
>>>> I'm not sure but did you make the modifications required
>>>> post-installation:
>>>> https://github.com/casper-astro/tutorials_devel/wiki#modifications-to-be-run-after-installs
>>>> ?
>>>>
>>>> I remember having a similar error for not having the make -> gmake link.
>>>>
>>>> Franco
>>>>
>>>> On Tue, Mar 5, 2019 at 10:24 AM Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Good day CASPERites
>>>>>
>>>>> I am trying to compile a deign for a ROACH2 but I get the
>>>>> following error:
>>>>>
>>>>> NGDBUILD Design Results Summary:
>>>>>   Number of errors: 2
>>>>>   Number of warnings: 10272
>>>>>
>>>>> Total REAL time to NGDBUILD completion: 2 min  48 sec
>>>>> Total CPU time to NGDBUILD completion:  2 min  41 sec
>>>>>
>>>>> One or more errors were found during NGDBUILD.  No NGD file will be
>>>>> written.
>>>>>
>>>>> Writing NGDBUILD log file "system.bld"...
>>>>> ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow
>>>>> execution...
>>>>> gmake: *** [__xps/system_routed] Error 1
>>>>> ERROR:EDK -
>>>>>Error while running "gmake -f system.make bits".
>>>>> Error using gen_xps_files (line 688)
>>>>> XPS failed.
>>>>>
>>>>> Does anyone perhaps know how to fix it?
>>>>>
>>>>> Thanks for the help
>>>>>
>>>>> Heystek
>>>>>
>>>>>
>>>>>
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Re: [casper] ROACH2 compile error

[Heystek Grobler]

Hey Franco and Jack

I have cheked that I have done the post install "fixes"

I have traced the error to these:

ERROR:NgdBuild:488 - Attribute value "LVCMOS33" is not an accepted value for
   attribute "IOSTANDARD" on "r2wb640mhz_roach_gpio_a_enable_not_ext<0>".
ERROR:NgdBuild:488 - Attribute value "LVCMOS33" is not an accepted value for
   attribute "IOSTANDARD" on "r2wb640mhz_roach_gpio_b_enable_not_ext<0>".

Do you perhaps know how I can fix this?

Heystek


On Thu, Mar 7, 2019 at 2:12 AM Jack Hickish  wrote:

> Hi Heystek,
>
> In addition to Franco's point about post-installation tweaks, you might
> find more information if you look up above the "Number of errors: 2", where
> [hopefully] there will be more specific error messages.
>
> Cheers
> Jack
>
> On Wed, 6 Mar 2019 at 09:47, Franco  wrote:
>
>> I'm not sure but did you make the modifications required
>> post-installation:
>> https://github.com/casper-astro/tutorials_devel/wiki#modifications-to-be-run-after-installs
>> ?
>>
>> I remember having a similar error for not having the make -> gmake link.
>>
>> Franco
>>
>> On Tue, Mar 5, 2019 at 10:24 AM Heystek Grobler 
>> wrote:
>>
>>> Good day CASPERites
>>>
>>> I am trying to compile a deign for a ROACH2 but I get the
>>> following error:
>>>
>>> NGDBUILD Design Results Summary:
>>>   Number of errors: 2
>>>   Number of warnings: 10272
>>>
>>> Total REAL time to NGDBUILD completion: 2 min  48 sec
>>> Total CPU time to NGDBUILD completion:  2 min  41 sec
>>>
>>> One or more errors were found during NGDBUILD.  No NGD file will be
>>> written.
>>>
>>> Writing NGDBUILD log file "system.bld"...
>>> ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow
>>> execution...
>>> gmake: *** [__xps/system_routed] Error 1
>>> ERROR:EDK -
>>>Error while running "gmake -f system.make bits".
>>> Error using gen_xps_files (line 688)
>>> XPS failed.
>>>
>>> Does anyone perhaps know how to fix it?
>>>
>>> Thanks for the help
>>>
>>> Heystek
>>>
>>>
>>>
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[casper] ROACH2 compile error

[Heystek Grobler]

Good day CASPERites

I am trying to compile a deign for a ROACH2 but I get the following error:

NGDBUILD Design Results Summary:
  Number of errors: 2
  Number of warnings: 10272

Total REAL time to NGDBUILD completion: 2 min  48 sec
Total CPU time to NGDBUILD completion:  2 min  41 sec

One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "system.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow
execution...
gmake: *** [__xps/system_routed] Error 1
ERROR:EDK -
   Error while running "gmake -f system.make bits".
Error using gen_xps_files (line 688)
XPS failed.

Does anyone perhaps know how to fix it?

Thanks for the help

Heystek

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Re: [casper] How to acquire matlab2013 license

[Heystek Grobler]

Hi Francisco

Thats good news!

Have a great day

Heystek

On Fri, 17 Nov 2017 at 19:54, Francisco Casado <fcas...@ug.uchile.cl> wrote:

> Thank you! I managed to get things working :)
>
>
>
>
>
> 2017-11-14 15:35 GMT-03:00 Heystek Grobler <heystekgrob...@gmail.com>:
>
>> Hi Francisco
>>
>> I had exactly the same issue about a year ago. Luckily the Matlab
>> licences are backwards compatible. You say that your university has a 2015
>> Matlab licence? Then you can use that licence to download and use a 2012
>> version from the Matlab site.
>>
>> I hope that it helps
>>
>> Heystek
>>
>>
>>
>> On Tue, Nov 14, 2017 at 8:25 PM, Francisco Casado <fcas...@ug.uchile.cl>
>> wrote:
>>
>>> Hi,
>>>
>>> I'm starting to work with ROACH2, but I don't have a matlab 2012/2013
>>> license, so I can't work with the casper library. Currently I have Xilinx
>>> ISE license and my university has a matlab 2015 license, but as far as I
>>> know, 2013 is the latest compatible version with ISE, which is also the
>>> latest compatible with the Virtex 6 in the ROACH2.
>>>
>>> How should I proceed to get one? The MathWorks page only provides info
>>> about 2017 products. Are there any other providers for older products?
>>>
>>> I would appreciate any advice on this matter.
>>>
>>> Thanks in advance,
>>>
>>> Francisco Casado
>>>
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>>
>>
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Re: [casper] How to acquire matlab2013 license

[Heystek Grobler]

Hi Francisco

I had exactly the same issue about a year ago. Luckily the Matlab licences
are backwards compatible. You say that your university has a 2015 Matlab
licence? Then you can use that licence to download and use a 2012 version
from the Matlab site.

I hope that it helps

Heystek



On Tue, Nov 14, 2017 at 8:25 PM, Francisco Casado 
wrote:

> Hi,
>
> I'm starting to work with ROACH2, but I don't have a matlab 2012/2013
> license, so I can't work with the casper library. Currently I have Xilinx
> ISE license and my university has a matlab 2015 license, but as far as I
> know, 2013 is the latest compatible version with ISE, which is also the
> latest compatible with the Virtex 6 in the ROACH2.
>
> How should I proceed to get one? The MathWorks page only provides info
> about 2017 products. Are there any other providers for older products?
>
> I would appreciate any advice on this matter.
>
> Thanks in advance,
>
> Francisco Casado
>
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Re: [casper] update the uboot file for ROACH2

[Heystek Grobler]

Good day!

I had a simular problem at the beginning of the year with a ROACH1 board.
What are the symptoms of your board? What happens when you hit the power
button?

Kind regards

Heystek



On Tue, 12 Sep 2017 at 6:50 PM pei...@xao.ac.cn  wrote:

> Hi All,
>
> We have a ROACH2 board couldn't boot up, does anyone has experience about
> how to update the uboot file for ROACH2?
> We found some old memo but we are not sure which macros(mac) file is
> correct.
>
>
> Best wishes,
> Pei Xin
> Xinjiang Astronomical Observatory, CAS
>
> --
> pei...@xao.ac.cn
>
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Re: [casper] Bof files

[Heystek Grobler]

Hi Michael!

I have found my problem. My OS did not have the “make” library installed.
Everything is compiling now.

Thanks for all the help :-)

Heystek

On Fri, Sep 1, 2017 at 11:09 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi Michael
>
> I have also tried compiling it through ISE itself, and then I get the
> following errors:
> Started : "XPS Process: Synthesize XPS Source".
>
> Xilinx Platform Studio
> Xilinx EDK 14.7 Build EDK_P.20131013
> Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
>
> XPS% Evaluating file
> /home/dserver/Simulink/wb_spectrometer_17/wb_spectrometer_17/system.synth.
> tcl
> WARNING:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE:
>wb_spectrometer_17_tgbe0_txs_ss_bram - Superseded core for architecture
>'virtex5lx' -
>/home/dserver/Simulink/wb_spectrometer_17/XPS_ROACH_base/system.mhs
> line 1300
>
> WARNING:EDK - IPNAME: opb_opb_lite, INSTANCE: opb2opb_bridge_opb1 -
> Superseded
>core for architecture 'virtex5lx' -
>/home/dserver/Simulink/wb_spectrometer_17/XPS_ROACH_base/system.mhs
> line 1475
>
> WARNING:EDK - IPNAME: opb_opb_lite, INSTANCE: opb2opb_bridge_opb2 -
> Superseded
>core for architecture 'virtex5lx' -
>/home/dserver/Simulink/wb_spectrometer_17/XPS_ROACH_base/system.mhs
> line 1496
>
> WARNING:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE:
>wb_spectrometer_17_tgbe0_txs_ss_bram - Superseded core for architecture
>'virtex5lx' -
>/home/dserver/Simulink/wb_spectrometer_17/XPS_ROACH_base/system.mhs
> line 1300
>
> WARNING:EDK - IPNAME: opb_opb_lite, INSTANCE: opb2opb_bridge_opb1 -
> Superseded
>core for architecture 'virtex5lx' -
>/home/dserver/Simulink/wb_spectrometer_17/XPS_ROACH_base/system.mhs
> line 1475
>
> WARNING:EDK - IPNAME: opb_opb_lite, INSTANCE: opb2opb_bridge_opb2 -
> Superseded
>core for architecture 'virtex5lx' -
>/home/dserver/Simulink/wb_spectrometer_17/XPS_ROACH_base/system.mhs
> line 1496
>
>
> Overriding IP level properties ...
>
> Computing clock values...
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with port :
>infrastructure_inst:epb_clk. Clock DRCs will not be performed on this
> core
>and cores connected to it.
> INFO:EDK - Cannot determine the input clock associated with por

Re: [casper] Bof files

[Heystek Grobler]

eter_17_sync_next_ppsopb0->opb2opb_bridge_opb1->opb1
  (0x01084000-0x01087fff)
wb_spectrometer_17_tgbe0opb0->opb2opb_bridge_opb1->opb1
  (0x01088000-0x010880ff)
wb_spectrometer_17_tgbe0_txctropb0->opb2opb_bridge_opb1->opb1
  (0x01088100-0x010881ff)
wb_spectrometer_17_tgbe0_txofctropb0->opb2opb_bridge_opb1->opb1
  (0x010a-0x010b)
wb_spectrometer_17_tgbe0_txs_ss_bramopb0->opb2opb_bridge_opb1->opb1
  (0x010c-0x010c00ff)
wb_spectrometer_17_tgbe0_txs_ss_ctrlopb0->opb2opb_bridge_opb1->opb1
  (0x010c0100-0x010c01ff)
wb_spectrometer_17_tgbe0_txs_ss_statusopb0->opb2opb_bridge_opb1->opb1
  (0x010c0200-0x010c02ff)
wb_spectrometer_17_tgbe0_txvldctropb0->opb2opb_bridge_opb1->opb1
  (0x010c0300-0x010c03ff)
wb_spectrometer_17_tgbe0_debug_resetopb0->opb2opb_bridge_opb1->opb1
  (0x010c0400-0x010c04ff)
wb_spectrometer_17_tgbe0_dest_ipopb0->opb2opb_bridge_opb1->opb1
  (0x010c0500-0x010c05ff)
wb_spectrometer_17_tgbe0_dest_portopb0->opb2opb_bridge_opb1->opb1
  (0x0110-0x011000ff)
wb_spectrometer_17_tgbe0_linkupopb0->opb2opb_bridge_opb2->opb2
  (0x01100100-0x011001ff)
wb_spectrometer_17_tgbe0_txopb0->opb2opb_bridge_opb2->opb2
  (0x01100200-0x011002ff)
wb_spectrometer_17_tgbe0_tx_fullopb0->opb2opb_bridge_opb2->opb2
  (0x01100300-0x011003ff)
wb_spectrometer_17_tgbe0_tx_ofopb0->opb2opb_bridge_opb2->opb2
  (0x01100400-0x011004ff)
wb_spectrometer_17_time_lsbopb0->opb2opb_bridge_opb2->opb2
  (0x01100500-0x011005ff)
wb_spectrometer_17_time_msbopb0->opb2opb_bridge_opb2->opb2
  (0x01100600-0x011006ff)
wb_spectrometer_17_upper_adc_thresholdopb0->opb2opb_bridge_opb2->opb2
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding PARAMETER
   C_NUM_MASTERS value to 1 -

/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/da
   ta/opb_v20_v2_1_0.mpd line 74
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding PARAMETER
   C_NUM_SLAVES value to 31 -

/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/da
   ta/opb_v20_v2_1_0.mpd line 75
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb1 - tool is overriding PARAMETER
   C_NUM_MASTERS value to 1 -

/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/da
   ta/opb_v20_v2_1_0.mpd line 74
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb1 - tool is overriding PARAMETER
   C_NUM_SLAVES value to 32 -

/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/da
   ta/opb_v20_v2_1_0.mpd line 75
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb2 - tool is overriding PARAMETER
   C_NUM_MASTERS value to 1 -

/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/da
   ta/opb_v20_v2_1_0.mpd line 74
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb2 - tool is overriding PARAMETER
   C_NUM_SLAVES value to 7 -

/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/da
   ta/opb_v20_v2_1_0.mpd line 75

Checking platform address map ...
Xilinx Port::Process Exec Failed:2
ERROR:EDK -
   Error while running "gmake -f system.make netlist".
ERROR: synthesizing XPS module failed!

Process "XPS Process: Synthesize XPS Source" failed

So it seams like that gmake -f is the problem?



On Fri, Sep 1, 2017 at 9:42 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi Michael
>
> Then I get the following:
>
> dserver@rserver:~/Simulink/wb_spectrometer_17/XPS_ROACH_base$ ./mkbof -o
> system.bof –s core_info.tab -t 3 system.bit
>
> -bash: ./mkbof: No such file or directory
>
> dserver@rserver:~/Simulink/wb_spectrometer_17/XPS_ROACH_base$
>
>
> I have used the locate function (locate mkbof) and get this:
>
> dserver@rserver:~/Simulink/wb_spectrometer_17/XPS_ROACH_base$ locate mkbof
>
> /home/dserver/Installs/DSP_System/mlib_devel/xps_base/
> XPS_ROACH2_base/mkbof
>
> /home/dserver/Installs/DSP_System/mlib_devel/xps_base/
> XPS_ROACH2_base/mkbof.exe
>
> /home/dserver/Installs/DSP_System/mlib_devel/xps_base/
> XPS_ROACH2_base/mkbof_64
>
> /home/dserver/Installs/DSP_System/mlib_devel/xps_base/XPS_ROACH_base/mkbof
>
> /home/dserver/Installs/DSP_System/mlib_devel/xps_base/
> XPS_ROACH_base/mkbof.exe
>
> /home/dserver/Installs/DSP_System/mlib_devel/xps_base/
> XPS_ROACH_base/mkbof_64
>
> /home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_
> ROACH2_base/mkbof
>
> /home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_
> ROACH2_base/mkbof.exe
>
> /home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_
> ROACH2_base/mkbof_64
>
> /home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_ROACH_base/mkbof
>
> /home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_
> ROACH_base/mkbof.exe
>
> /home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_
> RO

Re: [casper] Bof files

[Heystek Grobler]

Hi Michael

Then I get the following:

dserver@rserver:~/Simulink/wb_spectrometer_17/XPS_ROACH_base$ ./mkbof -o
system.bof –s core_info.tab -t 3 system.bit

-bash: ./mkbof: No such file or directory

dserver@rserver:~/Simulink/wb_spectrometer_17/XPS_ROACH_base$


I have used the locate function (locate mkbof) and get this:

dserver@rserver:~/Simulink/wb_spectrometer_17/XPS_ROACH_base$ locate mkbof

/home/dserver/Installs/DSP_System/mlib_devel/xps_base/XPS_ROACH2_base/mkbof

/home/dserver/Installs/DSP_System/mlib_devel/xps_base/XPS_ROACH2_base/mkbof.exe

/home/dserver/Installs/DSP_System/mlib_devel/xps_base/XPS_ROACH2_base/mkbof_64

/home/dserver/Installs/DSP_System/mlib_devel/xps_base/XPS_ROACH_base/mkbof

/home/dserver/Installs/DSP_System/mlib_devel/xps_base/XPS_ROACH_base/mkbof.exe

/home/dserver/Installs/DSP_System/mlib_devel/xps_base/XPS_ROACH_base/mkbof_64

/home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_ROACH2_base/mkbof

/home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_ROACH2_base/mkbof.exe

/home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_ROACH2_base/mkbof_64

/home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_ROACH_base/mkbof

/home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_ROACH_base/mkbof.exe

/home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_ROACH_base/mkbof_64

/home/dserver/Simulink/test/XPS_ROACH_base/mkbof

/home/dserver/Simulink/test/XPS_ROACH_base/mkbof.exe

/home/dserver/Simulink/test/XPS_ROACH_base/mkbof_64

/home/dserver/Simulink/wb_spectrometer_17/XPS_ROACH_base/mkbof

/home/dserver/Simulink/wb_spectrometer_17/XPS_ROACH_base/mkbof.exe

/home/dserver/Simulink/wb_spectrometer_17/XPS_ROACH_base/mkbof_64

which mkbof directory is the one that I should use. The one within
/home/dserver/Installs/mlib_devel-AVN_legacy/xps_base/XPS_ROACH2_base/mkbof or
the one where the casper_xps has generated the folder
/home/dserver/Simulink/wb_spectrometer_17/XPS_ROACH_base/mkbof

Thanks for the help!!

Heystek




On Fri, Sep 1, 2017 at 9:37 AM, David MacMahon <dav...@berkeley.edu> wrote:

> Maybe "./mkbof" instead of just "mkbof"?
>
> Dave
>
>
> On Aug 31, 2017, at 23:50, Heystek Grobler <heystekgrob...@gmail.com>
> wrote:
>
> Hi Michael
>
> If I run mkbof -o system.bof –s core_info.tab -t 3 system.bit it gives
> the following error/message
>
> -bash: mkbof: command not found
>
> I run it like this :
>
> dserver@rserver:~/Simulink/wb_spectrometer_17/XPS_ROACH_base$ mkbof -o
> system.bof –s core_info.tab -t 3 system.bit
>
> I am diong something wrong?
>
> Thanks for the help
>
> Heystek :-)
>
>
> On Thu, Aug 31, 2017 at 9:39 PM, Michael D'Cruze <michael.dcruze@postgrad.
> manchester.ac.uk> wrote:
>
>> Hi Heystek,
>>
>>
>>
>> If a bit file is created – and I think it is (someone correct me if I’m
>> wrong?) – you can use the following code to generate a bof file from it:
>>
>>
>>
>> mkbof -o system.bof –s core_info.tab -t 3 system.bit
>>
>>
>>
>> where core_info.tab is in XPS_ROACH2_base/.
>>
>>
>>
>> If that doesn’t work you can use the ISE suite itself to perform the
>> creation. Have a look at the memo I wrote on the Casper memos page (the one
>> with SmartXplorer in the title) which tells you how to do this.
>>
>>
>>
>> Cheers
>>
>> Michael
>>
>>
>>
>> *From:* Heystek Grobler [mailto:heystekgrob...@gmail.com]
>> *Sent:* 31 August 2017 20:22
>> *To:* Casper Lists
>> *Subject:* [casper] Bof files
>>
>>
>>
>> Hi Everyone :-)
>>
>>
>>
>> My apologies for bugging everyone again.
>>
>>
>>
>> I want to know I would I be able to compile/create a .bof file if I
>> un-tick the last box on the casper_xps screen?
>>
>>
>>
>> I have a unique problem where casper_xps does not run if the last box is
>> ticked.
>>
>>
>>
>> Thanks for the help
>>
>>
>>
>> Heystek :-)
>>
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>
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Re: [casper] Bof files

[Heystek Grobler]

Hi Michael

If I run mkbof -o system.bof –s core_info.tab -t 3 system.bit it gives the
following error/message

-bash: mkbof: command not found


I run it like this :


dserver@rserver:~/Simulink/wb_spectrometer_17/XPS_ROACH_base$ mkbof -o
system.bof –s core_info.tab -t 3 system.bit


I am diong something wrong?


Thanks for the help


Heystek :-)



On Thu, Aug 31, 2017 at 9:39 PM, Michael D'Cruze <
michael.dcr...@postgrad.manchester.ac.uk> wrote:

> Hi Heystek,
>
>
>
> If a bit file is created – and I think it is (someone correct me if I’m
> wrong?) – you can use the following code to generate a bof file from it:
>
>
>
> mkbof -o system.bof –s core_info.tab -t 3 system.bit
>
>
>
> where core_info.tab is in XPS_ROACH2_base/.
>
>
>
> If that doesn’t work you can use the ISE suite itself to perform the
> creation. Have a look at the memo I wrote on the Casper memos page (the one
> with SmartXplorer in the title) which tells you how to do this.
>
>
>
> Cheers
>
> Michael
>
>
>
> *From:* Heystek Grobler [mailto:heystekgrob...@gmail.com]
> *Sent:* 31 August 2017 20:22
> *To:* Casper Lists
> *Subject:* [casper] Bof files
>
>
>
> Hi Everyone :-)
>
>
>
> My apologies for bugging everyone again.
>
>
>
> I want to know I would I be able to compile/create a .bof file if I
> un-tick the last box on the casper_xps screen?
>
>
>
> I have a unique problem where casper_xps does not run if the last box is
> ticked.
>
>
>
> Thanks for the help
>
>
>
> Heystek :-)
>
> --
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[casper] Bof files

[Heystek Grobler]

Hi Everyone :-)

My apologies for bugging everyone again.

I want to know I would I be able to compile/create a .bof file if I un-tick
the last box on the casper_xps screen?

I have a unique problem where casper_xps does not run if the last box is
ticked.

Thanks for the help

Heystek :-)

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Re: [casper] gen_xps fails

[Heystek Grobler]

++
+++   WARNING !!!  +


WARNING:EDK - Processor epb_opb_bridge_inst has no memory mapped at its
reset
   vector.



INFO:EDK - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding PARAMETER
   C_NUM_MASTERS value to 1 -

 /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/da
   ta/opb_v20_v2_1_0.mpd line 74
INFO:EDK - IPNAME: opb_v20, INSTANCE:opb0 - tool is overriding PARAMETER
   C_NUM_SLAVES value to 1 -

 /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/da
   ta/opb_v20_v2_1_0.mpd line 75

Checking platform address map ...

XPS% Evaluating file run_xps.tcl
Xilinx Port::Process Exec Failed:2
ERROR:EDK -
   Error while running "gmake -f system.make bits".
Error using edit (line 66)
File 'implementation/system.twr' not found.
>>

Could it be the pcores?

Thanks for the help

Heystek

On Mon, Aug 28, 2017 at 10:23 AM, Amit Bansod <aban...@mpifr-bonn.mpg.de>
wrote:

> Hi,
>
> Can you try to update design (ctrl + D) to see if you get more information
> on the error?
> Cheers,
> Amit
>
>
> On 28 August 2017 09:10:56 CEST, Heystek Grobler <heystekgrob...@gmail.com>
> wrote:
>>
>> Hi Jack
>>
>> I have tried that but it still does not work. I have tried it with all
>> casper tutorials. The file “gen_xps_files.m” gives the problem. It is this
>> three veriables
>>
>> xps_objs
>> custom_xps_objs
>> core_types
>>
>> [image: Inline image 1]
>>
>> It breaks at line 255
>>
>> I cant figure out what is causing it.
>>
>> Heystek
>>
>> On Fri, Aug 25, 2017 at 6:45 PM, Jack Hickish <jackhick...@gmail.com>
>> wrote:
>>
>>> Weird. I'm guessing that is a software register? if you select the block
>>> that's throwing the error, then in matlab type "update_casper_block(gcb)"
>>> (which will delete that block and replace it with a fresh copy from the
>>> library) does that help at all.
>>>
>>> Cheers
>>> Jack
>>>
>>> On Fri, 25 Aug 2017 at 04:21 Heystek Grobler <heystekgrob...@gmail.com>
>>> wrote:
>>>
>>>> Good day everyone!
>>>>
>>>> I have one more weird problem. If I run casper_xps and start the
>>>> compilation, everything works until the file creation part. I keep getting
>>>> this error:
>>>>
>>>>  casper_xps
>>>> Detected Linux OS#
>>>> ##  System Update  ##
>>>> #
>>>> Warning: The model 'tutorial1' does not have continuous states, hence
>>>> Simulink is
>>>> using the solver 'VariableStepDiscrete' instead of solver 'ode45'. You
>>>> can disable
>>>> this diagnostic by explicitly specifying a discrete solver in the
>>>> solver tab of the
>>>> Configuration Parameters dialog, or by setting the 'Automatic solver
>>>> parameter
>>>> selection' diagnostic to 'none' in the Diagnostics tab of the
>>>> Configuration
>>>> Parameters dialog
>>>> > In gen_xps_files at 202
>>>>   In casper_xps>run_Callback at 155
>>>>   In casper_xps at 88
>>>>   In @(hObject,eventdata)casper_xps('run_Callback',hObject,eventd
>>>> ata,guidata(hObject))
>>>> Warning: Using a default value of 0.2 for maximum step size.  The
>>>> simulation step
>>>> size will be equal to or less than this value.  You can disable this
>>>> diagnostic by
>>>> setting 'Automatic solver parameter selection' diagnostic to 'none' in
>>>> the
>>>> Diagnostics page of the configuration parameters dialog
>>>> > In gen_xps_files at 202
>>>>   In casper_xps>run_Callback at 155
>>>>   In casper_xps at 88
>>>>   In @(hObject,eventdata)casper_xps('run_Callback',hObject,eventd
>>>> ata,guidata(hObject))
>>>> #
>>>> ## Block objects creation  ##
>>>> #
>>>> Problem with XPS: tag block: tutorial1/counter_value
>>>>
>>>> Error using gen_xps_files (line 255)
>>>> Error found during Object creation.
>>>>
>>>> Do anyone perhaps know what is going on?
>>>>
>>>> Thanks for the help
>>>>
>>>> --
>>>> You received this message because you are subscribed to the Google
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>>>> an email to casper+unsubscr...@lists.berkeley.edu.
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>>>>
>>>
>>

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[casper] gen_xps fails

[Heystek Grobler]

Good day everyone!

I have one more weird problem. If I run casper_xps and start the
compilation, everything works until the file creation part. I keep getting
this error:

 casper_xps
Detected Linux OS#
##  System Update  ##
#
Warning: The model 'tutorial1' does not have continuous states, hence
Simulink is
using the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can
disable
this diagnostic by explicitly specifying a discrete solver in the solver
tab of the
Configuration Parameters dialog, or by setting the 'Automatic solver
parameter
selection' diagnostic to 'none' in the Diagnostics tab of the Configuration
Parameters dialog
> In gen_xps_files at 202
  In casper_xps>run_Callback at 155
  In casper_xps at 88
  In @(hObject,eventdata)casper_xps('run_Callback',hObject,
eventdata,guidata(hObject))
Warning: Using a default value of 0.2 for maximum step size.  The
simulation step
size will be equal to or less than this value.  You can disable this
diagnostic by
setting 'Automatic solver parameter selection' diagnostic to 'none' in the
Diagnostics page of the configuration parameters dialog
> In gen_xps_files at 202
  In casper_xps>run_Callback at 155
  In casper_xps at 88
  In @(hObject,eventdata)casper_xps('run_Callback',hObject,
eventdata,guidata(hObject))
#
## Block objects creation  ##
#
Problem with XPS: tag block: tutorial1/counter_value

Error using gen_xps_files (line 255)
Error found during Object creation.

Do anyone perhaps know what is going on?

Thanks for the help

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[casper] Re: Matlab - Xilinx Help

[Heystek Grobler]

Good day Everyone.

I have found a fix to enable Matlab and Xilinx to work correctly on Debian.
The problem is that Matlab makes use of an older awk library and Xilinx
makes use of a newer one.

To fix the problem do the following steps:

Nr1: under the Matlab install path do the following


opt/Matlab/bin mv matlab.orig matlab

opt/Matlab/bin mv matlab.new



Nr 2: Create the following script and execute the script:


#!/bin/sh

unset LD_LIBRARY_PATH; /usr/bin/awk.real “$”

awk (END)


Nr3: Add this following code to the startsg script


if [ -n “$LD_LIBARY_PATH”];

 then

 LD_LIBRARY_PATH=${XILINX_PATH}/ISE/lib/lin64;

 echo “Using LD_LIBRARY_PATH=${LD_LIBRARY_PATH}”

 export LD_LIBRARY_PATH;

fi


Then Matlab and Xilinx will work on Debian.


Have a great day


Heystek

On Fri, Aug 11, 2017 at 10:58 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Good day everyone
>
> The last year I have been working on a Ubuntu system with Xilinx and
> Matlab. Currently I am trying to setup a system on a Debian (Jessie) system
> but I get the following error message when staring up matlab:
>
> Cannot access directory lib/lin64. The libraries under the
> path are needed to simulate and netlist designs using blocks
> from Xilinx System Generator for DSP blockset.
>
> Does anyone perhaps know how to solve this?
>
> Thanks for the help
>
> Heystek Grobler
>

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Re: [casper] Matlab - Xilinx Help

[Heystek Grobler]

Hi James

You were correct. The problem is with the environment variables. For some
reason the bash script "startsg" does not setup the path and as soon as
Matlab fires up it gives the error "Xilinx not installed properly or path
variables not set correctly" and then it gives the error on the terminal
window of "directory bin/lin" not found.

Do you have any idea on what is perhaps going on? I am a newby to
environment variables.

Thanks for the help

Heystek







On Fri, Aug 11, 2017 at 11:33 AM, James Smith <jsm...@ska.ac.za> wrote:

> You're going to have to check those environment variables, and see whether
> they're actually pointing to their targets.
>
>
> On Fri, Aug 11, 2017 at 11:29 AM, Heystek Grobler <
> heystekgrob...@gmail.com> wrote:
>
>> Hi James
>>
>> I Installed Xilinx under:
>>
>>  /opt/Xilinx/14.7/ISE_DS
>>
>> I am not sure to which bin/lin64 matlab is referring because you can find
>> them under
>>
>> /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
>>
>> and
>>
>>
>> /opt/Xilinx/14.7/ISE_DS/common/bin/lin64
>>
>> Thanks for the help
>>
>> Heystek
>>
>> On Fri, Aug 11, 2017 at 11:18 AM, James Smith <jsm...@ska.ac.za> wrote:
>>
>>> Hello Heystek,
>>>
>>> Where is your Xilinx library installed? See if you can cd to the
>>> directory that it refers to?
>>>
>>> Regards,
>>> James
>>>
>>>
>>> On Fri, Aug 11, 2017 at 11:17 AM, Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>>
>>>> Hi Ryan
>>>>
>>>> Thanks for your help!
>>>>
>>>> I have added that slash but still get the same error.
>>>>
>>>> I also had to add the following code to the settibgs64.sh file to get
>>>> matlab started:
>>>>
>>>> if [ -n "$LD_LIBRARY_PATH" ]; then
>>>>   LD_LIBRARY_PATH=:${LD_LIBRARY_PATH}:${XILINX_EDK}/lib/lin64;
>>>>   export LD_LIBRARY_PATH;
>>>>
>>>> any other idees?
>>>>
>>>> Thanks for your help :-)
>>>>
>>>> Heystek
>>>>
>>>>
>>>>
>>>> On Fri, Aug 11, 2017 at 11:02 AM, Ryan Monroe <ryan.m.mon...@gmail.com>
>>>> wrote:
>>>>
>>>>> I just dealt with this problem yesterday!  Somewhere in your startup.m
>>>>> file, you should have a line that looks like this:
>>>>> xlAddSysgen([getenv('XILINX_PATH'), '/ISE'])
>>>>>
>>>>> Toss in an extra slash at the end of the path:
>>>>> xlAddSysgen([getenv('XILINX_PATH'), '/ISE/'])
>>>>>
>>>>> Now, I still haven't sorted the REST of the debian/xilinx issues
>>>>> that's tomorrows problem :-)
>>>>>
>>>>>
>>>>>
>>>>> On 08/11/2017 01:58 AM, Heystek Grobler wrote:
>>>>>
>>>>> Good day everyone
>>>>>
>>>>> The last year I have been working on a Ubuntu system with Xilinx and
>>>>> Matlab. Currently I am trying to setup a system on a Debian (Jessie) 
>>>>> system
>>>>> but I get the following error message when staring up matlab:
>>>>>
>>>>> Cannot access directory lib/lin64. The libraries under the
>>>>> path are needed to simulate and netlist designs using blocks
>>>>> from Xilinx System Generator for DSP blockset.
>>>>>
>>>>> Does anyone perhaps know how to solve this?
>>>>>
>>>>> Thanks for the help
>>>>>
>>>>> Heystek Grobler
>>>>> --
>>>>> You received this message because you are subscribed to the Google
>>>>> Groups "casper@lists.berkeley.edu" <casper@lists.berkeley.edu> group.
>>>>> To unsubscribe from this group and stop receiving emails from it, send
>>>>> an email to casper+unsubscr...@lists.berkeley.edu.
>>>>> To post to this group, send email to casper@lists.berkeley.edu.
>>>>>
>>>>>
>>>>>
>>>> --
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>>>
>>>
>>
>

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Re: [casper] Matlab - Xilinx Help

[Heystek Grobler]

Hi James

I Installed Xilinx under:

 /opt/Xilinx/14.7/ISE_DS

I am not sure to which bin/lin64 matlab is referring because you can find
them under

/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64

and


/opt/Xilinx/14.7/ISE_DS/common/bin/lin64

Thanks for the help

Heystek

On Fri, Aug 11, 2017 at 11:18 AM, James Smith <jsm...@ska.ac.za> wrote:

> Hello Heystek,
>
> Where is your Xilinx library installed? See if you can cd to the directory
> that it refers to?
>
> Regards,
> James
>
>
> On Fri, Aug 11, 2017 at 11:17 AM, Heystek Grobler <
> heystekgrob...@gmail.com> wrote:
>
>> Hi Ryan
>>
>> Thanks for your help!
>>
>> I have added that slash but still get the same error.
>>
>> I also had to add the following code to the settibgs64.sh file to get
>> matlab started:
>>
>> if [ -n "$LD_LIBRARY_PATH" ]; then
>>   LD_LIBRARY_PATH=:${LD_LIBRARY_PATH}:${XILINX_EDK}/lib/lin64;
>>   export LD_LIBRARY_PATH;
>>
>> any other idees?
>>
>> Thanks for your help :-)
>>
>> Heystek
>>
>>
>>
>> On Fri, Aug 11, 2017 at 11:02 AM, Ryan Monroe <ryan.m.mon...@gmail.com>
>> wrote:
>>
>>> I just dealt with this problem yesterday!  Somewhere in your startup.m
>>> file, you should have a line that looks like this:
>>> xlAddSysgen([getenv('XILINX_PATH'), '/ISE'])
>>>
>>> Toss in an extra slash at the end of the path:
>>> xlAddSysgen([getenv('XILINX_PATH'), '/ISE/'])
>>>
>>> Now, I still haven't sorted the REST of the debian/xilinx issues
>>> that's tomorrows problem :-)
>>>
>>>
>>>
>>> On 08/11/2017 01:58 AM, Heystek Grobler wrote:
>>>
>>> Good day everyone
>>>
>>> The last year I have been working on a Ubuntu system with Xilinx and
>>> Matlab. Currently I am trying to setup a system on a Debian (Jessie) system
>>> but I get the following error message when staring up matlab:
>>>
>>> Cannot access directory lib/lin64. The libraries under the
>>> path are needed to simulate and netlist designs using blocks
>>> from Xilinx System Generator for DSP blockset.
>>>
>>> Does anyone perhaps know how to solve this?
>>>
>>> Thanks for the help
>>>
>>> Heystek Grobler
>>> --
>>> You received this message because you are subscribed to the Google
>>> Groups "casper@lists.berkeley.edu" <casper@lists.berkeley.edu> group.
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>>> an email to casper+unsubscr...@lists.berkeley.edu.
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>>>
>>>
>>>
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>
>

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Re: [casper] Matlab - Xilinx Help

[Heystek Grobler]

Hi Ryan

Thanks for your help!

I have added that slash but still get the same error.

I also had to add the following code to the settibgs64.sh file to get
matlab started:

if [ -n "$LD_LIBRARY_PATH" ]; then
  LD_LIBRARY_PATH=:${LD_LIBRARY_PATH}:${XILINX_EDK}/lib/lin64;
  export LD_LIBRARY_PATH;

any other idees?

Thanks for your help :-)

Heystek



On Fri, Aug 11, 2017 at 11:02 AM, Ryan Monroe <ryan.m.mon...@gmail.com>
wrote:

> I just dealt with this problem yesterday!  Somewhere in your startup.m
> file, you should have a line that looks like this:
> xlAddSysgen([getenv('XILINX_PATH'), '/ISE'])
>
> Toss in an extra slash at the end of the path:
> xlAddSysgen([getenv('XILINX_PATH'), '/ISE/'])
>
> Now, I still haven't sorted the REST of the debian/xilinx issues
> that's tomorrows problem :-)
>
>
>
> On 08/11/2017 01:58 AM, Heystek Grobler wrote:
>
> Good day everyone
>
> The last year I have been working on a Ubuntu system with Xilinx and
> Matlab. Currently I am trying to setup a system on a Debian (Jessie) system
> but I get the following error message when staring up matlab:
>
> Cannot access directory lib/lin64. The libraries under the
> path are needed to simulate and netlist designs using blocks
> from Xilinx System Generator for DSP blockset.
>
> Does anyone perhaps know how to solve this?
>
> Thanks for the help
>
> Heystek Grobler
> --
> You received this message because you are subscribed to the Google Groups
> "casper@lists.berkeley.edu" <casper@lists.berkeley.edu> group.
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> email to casper+unsubscr...@lists.berkeley.edu.
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>
>
>

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[casper] Matlab - Xilinx Help

[Heystek Grobler]

Good day everyone

The last year I have been working on a Ubuntu system with Xilinx and
Matlab. Currently I am trying to setup a system on a Debian (Jessie) system
but I get the following error message when staring up matlab:

Cannot access directory lib/lin64. The libraries under the
path are needed to simulate and netlist designs using blocks
from Xilinx System Generator for DSP blockset.

Does anyone perhaps know how to solve this?

Thanks for the help

Heystek Grobler

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[casper] Clock signal question

[Heystek Grobler]

Hi everyone

Does anyone know what is the best clock signal for a ROACH1 and ROACH2
board and will a sign wave do and at what level?

Thanks for all the help

Heystek

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Re: [casper] katadc

[Heystek Grobler]

Hi James

Physically I have connected the signal generator to the katadc's "i" input
connector with a square wave at 50MHz with amplitude of 2Vpp.

The simulink model is connected as follows:

[image: Inline image 2]
If I program the ROACH and pull a spectrum of It I get nothing (only a
straight line through zero) or sometimes I get the most random noise that
is all over the place.

Heystek









On Wed, May 17, 2017 at 9:48 AM, James Smith <jsm...@ska.ac.za> wrote:

> Hello Heystek,
>
> If you're not getting a spectrum, what are you getting? How have you
> connected your katadc? (Both physically and with the yellow block)?
>
> Regards,
> James
>
>
> On Wed, May 17, 2017 at 9:46 AM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Good day everyone
>>
>> I am trying to implement tutorial 3 on a ROACH1 with a katadc. I have
>> previously done it on a ROACH2 with the iadc.
>>
>> For some reason I am struggling to get the katadc to work. I am using
>> the katadc yellow block but I cant generate a spectrum. I hooked up an
>> signal generator to the katadc and gave it a square wave at 50MHz.
>>
>> Am I doing something stupid? Or is there another yellow block that I
>> should rather use.
>>
>> Have a great day
>>
>> Heystek Grobler
>>
>> --
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>>
>
>

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[casper] katadc

[Heystek Grobler]

Good day everyone

I am trying to implement tutorial 3 on a ROACH1 with a katadc. I have
previously done it on a ROACH2 with the iadc.

For some reason I am struggling to get the katadc to work. I am using the
katadc yellow block but I cant generate a spectrum. I hooked up an signal
generator to the katadc and gave it a square wave at 50MHz.

Am I doing something stupid? Or is there another yellow block that I should
rather use.

Have a great day

Heystek Grobler

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Re: [casper] Problem uploading .bof file to Roach1

[Heystek Grobler]

Hi James and Marc

If I ssh into the roach and copy the file over to /boffiles/ then I can
program it, so the problem is semi solved for now. If I check ow much
memory I have used, it is at 46%

On Mon, May 15, 2017 at 1:49 PM, James Smith <jsm...@ska.ac.za> wrote:

> Hello Heystek,
>
> If you're not sure on Marc's suggestion -- ssh in and use "df -h" and it
> should tell you how much space you have left on the ROACH's filesystems.
>
> Regards,
> James
>
>
> On Mon, May 15, 2017 at 1:48 PM, Marc Welz <m...@ska.ac.za> wrote:
>
>> Long shot - could you have run out of space on the roach ?
>>
>> On Mon, May 15, 2017 at 7:39 AM, Heystek Grobler
>> <heystekgrob...@gmail.com> wrote:
>> > Good day everyone
>> >
>> > I have encountered a weird problem. Everything was working fine until
>> today.
>> > I cant upload a .bof file to my roach1. I keep getting this error:
>> >
>> > #log error 2947729786047 poco ulpoad\_process\_exitet\_with\_code\_69
>> >
>> > I have tried uploading the file through kapcp and telnet but poco errors
>> > keeps popping up.
>> >
>> > Does anyone have an idee whats going on?
>> >
>> > Thanks for the help
>> >
>> > Heystek
>> >
>> > --
>> > You received this message because you are subscribed to the Google
>> Groups
>> > "casper@lists.berkeley.edu" group.
>> > To unsubscribe from this group and stop receiving emails from it, send
>> an
>> > email to casper+unsubscr...@lists.berkeley.edu.
>> > To post to this group, send email to casper@lists.berkeley.edu.
>>
>> --
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>
>

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[casper] Problem uploading .bof file to Roach1

[Heystek Grobler]

Good day everyone

I have encountered a weird problem. Everything was working fine until
today. I cant upload a .bof file to my roach1. I keep getting this error:

#log error 2947729786047 poco ulpoad\_process\_exitet\_with\_code\_69

I have tried uploading the file through kapcp and telnet but poco errors
keeps popping up.

Does anyone have an idee whats going on?

Thanks for the help

Heystek

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Re: [casper] katadc help in simulink

[Heystek Grobler]

Hi James

Thanks for the help!! I had to add software registers to en0 and en1 as
well but know it compiles.

Thanks for the help!!

I really apreciate it

Heystek

On Mon, May 8, 2017 at 2:23 PM, James Smith <jsm...@ska.ac.za> wrote:

> Hello Heystek,
>
> The KatADC is described here:
> https://casper.berkeley.edu/wiki/KatADC
>
> It's got two channels which you need to enable if you want to use them,
> and 31.5 dB variable attenuators which you need to set.
>
> So if you want them to be on all the time, just hard-wire some 1s into en0
> and en1. I'd suggest putting software registers into atten0 and atten1 then
> writing to them from a Python script. You can adjust the attenuation from 0
> dB to 31.5 dB in 0.5 dB increments using a 5-bit number.
>
> Regards,
> James
>
>
>
> On Mon, May 8, 2017 at 2:17 PM, Heystek Grobler <heystekgrob...@gmail.com>
> wrote:
>
>> Good day everyone
>>
>> I have a ROACH1 board with a katadc. I have located the katadc under the
>> CAPER XPS Blockset (I am trying to do tut3). I have swapped the iadc for
>> the katadc.
>>
>> The problem is, the katadc has the following inputs:
>> en0
>> atten0
>> en1
>> atten1
>>
>> I need to connect something to those inputs to be able to compile a bof
>> file. Does anyone perhaps know what inputs I should connect/use?
>>
>> Have a great day
>>
>> Thanks for the help
>>
>> Heystek Grobler
>>
>>
>> --
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>>
>
>

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[casper] katadc help in simulink

[Heystek Grobler]

Good day everyone

I have a ROACH1 board with a katadc. I have located the katadc under the
CAPER XPS Blockset (I am trying to do tut3). I have swapped the iadc for
the katadc.

The problem is, the katadc has the following inputs:
en0
atten0
en1
atten1

I need to connect something to those inputs to be able to compile a bof
file. Does anyone perhaps know what inputs I should connect/use?

Have a great day

Thanks for the help

Heystek Grobler

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[casper] Re: Help to program roach1

[Heystek Grobler]

Good day everyone

I have mannaged to solve the problem. I have installed katcp 0.5.5 and and
using the commands in this order:

fpga.upload_bof()

then

fpga.progdev()

Then the Roach1 works.

Thanks for everyones help and advice!

Have a great day

Heystek


On Sat, Apr 22, 2017 at 1:26 PM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Good day
>
> I have an interesting problem. I'm used to working on a ROACH2 and now I
> must do a project on a ROACH1 board.
>
> When Running the casperfpga package I received this error:
>
> In [1]: import casperfpga
>
> In [2]: fpga=casperfpga.katcp_fpga.KatcpFpga('192.168.33.3')
> In [3]: 
> fpga.upload_to_ram_and_program('heystek_tut3_2017_Apr_19_1133.bof')---
> RuntimeError  Traceback (most recent call last)
>  in ()
> > 1 fpga.upload_to_ram_and_program('heystek_tut3_2017_Apr_19_1133.bof')
>
> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in 
> upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
> 442 if request_result != '':
> 443 raise RuntimeError('progremote request(%s) on host %s 
> failed' %
> --> 444(request_result, self.host))
> 445
> 446 # start the upload thread and join
>
> RuntimeError: progremote request(Request to client 192.168.33.3 failed.) on 
> host 192.168.33.3 failed
>
> I then tried running the corr package and I got this error:
>
> In [7]: fpga=corr.katcp_wrapper.FpgaClient('192.168.33.3',7147)
> ---
> TypeError Traceback (most recent call last)
>  in ()
> > 1 fpga=corr.katcp_wrapper.FpgaClient('192.168.33.3',7147)
>
> /usr/local/lib/python2.7/dist-packages/corr/katcp_wrapper.pyc in 
> __init__(self, host, port, tb_limit, timeout, logger)
>  86 self.host = host
>  87 self._timeout = timeout
> ---> 88 self.start(daemon = True)
>  89
>  90 # async stuff
>
> TypeError: start() got an unexpected keyword argument 'daemon'
>
> With my ROACH2 I had to update the kernel and file system with this 
> instructions to solve the problem:
> https://www.mail-archive.com/casper@lists.berkeley.edu/msg06452.html
>
> but this does not work on the ROACH1 so I reverted back to this kernel and 
> file system
> https://casper.berkeley.edu/wiki/Setting_Up_BORPH_on_ROACH
>
> What am I doing wrong?
>
> Thanks for the help
>
> Heystek
>
>

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[casper] Help to program roach1

[Heystek Grobler]

Good day

I have an interesting problem. I'm used to working on a ROACH2 and now I
must do a project on a ROACH1 board.

When Running the casperfpga package I received this error:

In [1]: import casperfpga

In [2]: fpga=casperfpga.katcp_fpga.KatcpFpga('192.168.33.3')
In [3]: 
fpga.upload_to_ram_and_program('heystek_tut3_2017_Apr_19_1133.bof')---
RuntimeError  Traceback (most recent call last)
 in ()
> 1 fpga.upload_to_ram_and_program('heystek_tut3_2017_Apr_19_1133.bof')

/usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
upload_to_ram_and_program(self, filename, port, timeout,
wait_complete)
442 if request_result != '':
443 raise RuntimeError('progremote request(%s) on host
%s failed' %
--> 444(request_result, self.host))
445
446 # start the upload thread and join

RuntimeError: progremote request(Request to client 192.168.33.3
failed.) on host 192.168.33.3 failed

I then tried running the corr package and I got this error:

In [7]: fpga=corr.katcp_wrapper.FpgaClient('192.168.33.3',7147)
---
TypeError Traceback (most recent call last)
 in ()
> 1 fpga=corr.katcp_wrapper.FpgaClient('192.168.33.3',7147)

/usr/local/lib/python2.7/dist-packages/corr/katcp_wrapper.pyc in
__init__(self, host, port, tb_limit, timeout, logger)
 86 self.host = host
 87 self._timeout = timeout
---> 88 self.start(daemon = True)
 89
 90 # async stuff

TypeError: start() got an unexpected keyword argument 'daemon'

With my ROACH2 I had to update the kernel and file system with this
instructions to solve the problem:
https://www.mail-archive.com/casper@lists.berkeley.edu/msg06452.html

but this does not work on the ROACH1 so I reverted back to this kernel
and file system
https://casper.berkeley.edu/wiki/Setting_Up_BORPH_on_ROACH

What am I doing wrong?

Thanks for the help

Heystek

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Re: [casper] ROACH1 serial to USB connection

[Heystek Grobler]

Hi Jason

Its really no problem.

I used the steps that you have send me with a ST-link V2 J-TAG (It is
almost like the USB wiggler). I can open up a serail connection with
Hyperterminal and open up an connection with the OCD Commander. Once i run
the Macro I get the following error:

Write large: processor running (40:0C)

and

An error occured during the execution of your Marco file. Exit Marco
execution now?

and then nothing happens.

Thanks for your help!!

Heystek

On Fri, Mar 31, 2017 at 9:27 PM, Jason Ray <j...@nrao.edu> wrote:

> Heystek,
>
> Sorry for the delay in replying.
>
> I'm not sure about the converter script.  Every time I've debricked a
> roach, I used our USB wiggler, and followed these steps:
> http://www2.asiaa.sinica.edu.tw/~homin/wiki/pmwiki-2.1.27/
> uploads/HiSpeedDigital/fileHow_to_update_uboot_file_
> if_ROACH_cannot_bootup.pdf
>
> And, this procedure as well...
> https://casper.berkeley.edu/wiki/ROACH_kernel_uboot_update
>
> Hope this helps,
> Jason
>
>
>
> On 3/29/2017 8:45 AM, Heystek Grobler wrote:
>
> Hi Jason
>
> I got my hands on a JTAG. I went through the CASPER debricking tutorial
> page but I dont understand how to use the converter script? Do you perhaps
> know how to use it?
>
> Thanks for all of your help
>
> Heystek
>
> On Mon, Mar 27, 2017 at 11:54 AM, Heystek Grobler <
> heystekgrob...@gmail.com> wrote:
>
>> Hi Jason
>>
>> Yes, all flow control is off. both the (Xon/Xoff or DC1/DC3) is off.
>>
>> On Mon, Mar 27, 2017 at 11:32 AM, Jason Manley <jman...@ska.ac.za> wrote:
>>
>>> You've checked that hardware flow control is turned off on your serial
>>> port?
>>>
>>> Jason
>>>
>>>
>>> On 27 Mar 2017, at 11:29, Heystek Grobler <heystekgrob...@gmail.com>
>>> wrote:
>>>
>>> > Hi Jason
>>> >
>>> > The ROACH1 is a brand new board that we just unboxed. I tried
>>> connecing to it using two diffirent serial to usb cables and both gave the
>>> same result, a connection to the board, but the terminal only displays a
>>> black screen. No Uboot sequence or any kind of output.
>>> >
>>> > I will double check by shorting pins 2 & 3 and see if I get anyyhing
>>> on the terminal.
>>> >
>>> > If I am right if I say I think that the roach might be bricked?
>>> >
>>> > Thanks for all the help
>>> >
>>> > Heystek
>>> >
>>> > On Wed, Mar 22, 2017 at 9:23 PM, Jason Ray <j...@nrao.edu> wrote:
>>> > Heystek,
>>> >
>>> > Is this a known good roach1 board?  Could it have been bricked by
>>> chance?  If so it will behave like you describe and you may need to do this:
>>> >
>>> > https://casper.berkeley.edu/wiki/ROACH_Debricking
>>> >
>>> > Another thing you can try if you haven't already is to swap pins 2 &
>>> 3.  Even if you have a null modem cable, something else could be going on
>>> (with the adapter perhaps.?) and it never hurts to just swap 2 & 3 and give
>>> it another try.
>>> >
>>> > Also, a simple thing you can do to verify your serial adapter is
>>> working is to do a loopback, short pins 2 & 3 together, then type something
>>> in the terminal and see if it displays on the screen.
>>> >
>>> > Good luck,
>>> > Jason
>>> >
>>> >
>>> >
>>> >
>>> > On 3/22/2017 3:08 PM, Heystek Grobler wrote:
>>> >> Hi
>>> >>
>>> >> When I use dev/tty* I can see the adapter. This is the adapter Im
>>> using
>>> >>
>>> >> https://www.unitek-products.com/en/product_detail.php?id=12
>>> >>
>>> >>
>>> >> On Wed, 22 Mar 2017 at 9:05 PM Jack Hickish <jackhick...@gmail.com>
>>> wrote:
>>> >> H. And the adapter definitely works?
>>> >>
>>> >> Sorry, I think you're going to need someone smarter than me.
>>> >>
>>> >> On Wed, 22 Mar 2017 at 11:06 Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>> >> Hi Jack
>>> >>
>>> >> Jip it is the null-modem type with the 9 pins. If I open up an
>>> terminal connection through putty or minicom I can open up an connection
>>> with the 115200 8N1 settings, but I cant see Uboot. I can only see 'n blank
>>> terminal window.
>>> >>
>>> >

Re: [casper] ROACH1 serial to USB connection

[Heystek Grobler]

Hi Jason

I got my hands on a JTAG. I went through the CASPER debricking tutorial
page but I dont understand how to use the converter script? Do you perhaps
know how to use it?

Thanks for all of your help

Heystek

On Mon, Mar 27, 2017 at 11:54 AM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Hi Jason
>
> Yes, all flow control is off. both the (Xon/Xoff or DC1/DC3) is off.
>
> On Mon, Mar 27, 2017 at 11:32 AM, Jason Manley <jman...@ska.ac.za> wrote:
>
>> You've checked that hardware flow control is turned off on your serial
>> port?
>>
>> Jason
>>
>>
>> On 27 Mar 2017, at 11:29, Heystek Grobler <heystekgrob...@gmail.com>
>> wrote:
>>
>> > Hi Jason
>> >
>> > The ROACH1 is a brand new board that we just unboxed. I tried connecing
>> to it using two diffirent serial to usb cables and both gave the same
>> result, a connection to the board, but the terminal only displays a black
>> screen. No Uboot sequence or any kind of output.
>> >
>> > I will double check by shorting pins 2 & 3 and see if I get anyyhing on
>> the terminal.
>> >
>> > If I am right if I say I think that the roach might be bricked?
>> >
>> > Thanks for all the help
>> >
>> > Heystek
>> >
>> > On Wed, Mar 22, 2017 at 9:23 PM, Jason Ray <j...@nrao.edu> wrote:
>> > Heystek,
>> >
>> > Is this a known good roach1 board?  Could it have been bricked by
>> chance?  If so it will behave like you describe and you may need to do this:
>> >
>> > https://casper.berkeley.edu/wiki/ROACH_Debricking
>> >
>> > Another thing you can try if you haven't already is to swap pins 2 &
>> 3.  Even if you have a null modem cable, something else could be going on
>> (with the adapter perhaps.?) and it never hurts to just swap 2 & 3 and give
>> it another try.
>> >
>> > Also, a simple thing you can do to verify your serial adapter is
>> working is to do a loopback, short pins 2 & 3 together, then type something
>> in the terminal and see if it displays on the screen.
>> >
>> > Good luck,
>> > Jason
>> >
>> >
>> >
>> >
>> > On 3/22/2017 3:08 PM, Heystek Grobler wrote:
>> >> Hi
>> >>
>> >> When I use dev/tty* I can see the adapter. This is the adapter Im using
>> >>
>> >> https://www.unitek-products.com/en/product_detail.php?id=12
>> >>
>> >>
>> >> On Wed, 22 Mar 2017 at 9:05 PM Jack Hickish <jackhick...@gmail.com>
>> wrote:
>> >> H. And the adapter definitely works?
>> >>
>> >> Sorry, I think you're going to need someone smarter than me.
>> >>
>> >> On Wed, 22 Mar 2017 at 11:06 Heystek Grobler <heystekgrob...@gmail.com>
>> wrote:
>> >> Hi Jack
>> >>
>> >> Jip it is the null-modem type with the 9 pins. If I open up an
>> terminal connection through putty or minicom I can open up an connection
>> with the 115200 8N1 settings, but I cant see Uboot. I can only see 'n blank
>> terminal window.
>> >>
>> >>
>> >> On Wed, 22 Mar 2017 at 7:24 PM Jack Hickish <jackhick...@gmail.com>
>> wrote:
>> >> Hi Heystek,
>> >>
>> >> Just to be clear, you're connecting to the 9 pin serial connector on
>> the ROACH (not the USB port)?
>> >> If you're using a serial cable between the ROACH and your USB adapter,
>> is it the correct null-modem type?
>> >> Do you have the correct comms settings? -- roach1 is 115200 8N1
>> >>
>> >> Some info which might help is at https://casper.berkeley.edu/wi
>> ki/ROACH_NFS_guide#Preliminary_setup_1:_The_serial_connection
>> >>
>> >> Cheers
>> >> Jack
>> >>
>> >> On Wed, 22 Mar 2017 at 05:39 Heystek Grobler <heystekgrob...@gmail.com>
>> wrote:
>> >> Good day everyone
>> >>
>> >> I am trying to connect to a ROACH1 board with a serial to usb cable. I
>> have tried the connection through putty and minicom. I can open up a serial
>> connection but I can not see the U-Boot loader kicking in and watch the
>> start up sequence. I also have ROACH2 and I can see U-Boot and the start up
>> sequence fine in it with a USB cable.
>> >>
>> >> Do you perhaps know what the problem could be that I am not getting is
>> right on the ROACH1?
>> >>
>> >> Have a great day
>

Re: [casper] ROACH1 serial to USB connection

[Heystek Grobler]

Hi Jason

The ROACH1 is a brand new board that we just unboxed. I tried connecing to
it using two diffirent serial to usb cables and both gave the same result,
a connection to the board, but the terminal only displays a black screen.
No Uboot sequence or any kind of output.

I will double check by shorting pins 2 & 3 and see if I get anyyhing on the
terminal.

If I am right if I say I think that the roach might be bricked?

Thanks for all the help

Heystek

On Wed, Mar 22, 2017 at 9:23 PM, Jason Ray <j...@nrao.edu> wrote:

> Heystek,
>
> Is this a known good roach1 board?  Could it have been bricked by chance?
> If so it will behave like you describe and you may need to do this:
>
> https://casper.berkeley.edu/wiki/ROACH_Debricking
>
> Another thing you can try if you haven't already is to swap pins 2 & 3.
> Even if you have a null modem cable, something else could be going on (with
> the adapter perhaps.?) and it never hurts to just swap 2 & 3 and give it
> another try.
>
> Also, a simple thing you can do to verify your serial adapter is working
> is to do a loopback, short pins 2 & 3 together, then type something in the
> terminal and see if it displays on the screen.
>
> Good luck,
> Jason
>
>
>
>
> On 3/22/2017 3:08 PM, Heystek Grobler wrote:
>
> Hi
>
> When I use dev/tty* I can see the adapter. This is the adapter Im using
>
> https://www.unitek-products.com/en/product_detail.php?id=12
>
>
> On Wed, 22 Mar 2017 at 9:05 PM Jack Hickish <jackhick...@gmail.com> wrote:
>
>> H. And the adapter definitely works?
>>
>> Sorry, I think you're going to need someone smarter than me.
>>
>> On Wed, 22 Mar 2017 at 11:06 Heystek Grobler <heystekgrob...@gmail.com>
>> wrote:
>>
>> Hi Jack
>>
>> Jip it is the null-modem type with the 9 pins. If I open up an terminal
>> connection through putty or minicom I can open up an connection with the
>> 115200 8N1 settings, but I cant see Uboot. I can only see 'n blank terminal
>> window.
>>
>>
>> On Wed, 22 Mar 2017 at 7:24 PM Jack Hickish <jackhick...@gmail.com>
>> wrote:
>>
>> Hi Heystek,
>>
>> Just to be clear, you're connecting to the 9 pin serial connector on the
>> ROACH (not the USB port)?
>> If you're using a serial cable between the ROACH and your USB adapter, is
>> it the correct null-modem type?
>> Do you have the correct comms settings? -- roach1 is 115200 8N1
>>
>> Some info which might help is at https://casper.berkeley.
>> edu/wiki/ROACH_NFS_guide#Preliminary_setup_1:_The_serial_connection
>>
>> Cheers
>> Jack
>>
>> On Wed, 22 Mar 2017 at 05:39 Heystek Grobler <heystekgrob...@gmail.com>
>> wrote:
>>
>> Good day everyone
>>
>> I am trying to connect to a ROACH1 board with a serial to usb cable. I
>> have tried the connection through putty and minicom. I can open up a serial
>> connection but I can not see the U-Boot loader kicking in and watch the
>> start up sequence. I also have ROACH2 and I can see U-Boot and the start up
>> sequence fine in it with a USB cable.
>>
>> Do you perhaps know what the problem could be that I am not getting is
>> right on the ROACH1?
>>
>> Have a great day
>>
>> Heystek Grobler
>>
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>> email to casper+unsubscr...@lists.berkeley.edu.
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>>
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Re: [casper] 回复: Programming a ROACH2

[Heystek Grobler]

Hi James

With ''live data'' I mean my own data from an FM antenna. Wesley suggested
that I use a snap block. So basically al I need to do is add a snap block
at the end of the simulation from tut3 that says "evan" and "odd" and plot
the data that has been captured inside them.

Thank you

Heystek

On Tue, Oct 18, 2016 at 10:31 AM, James Smith <jsm...@ska.ac.za> wrote:

> Hello Heystek,
>
> I'm not sure what you mean by 'live' data. Wesley's mail correctly refers
> you to tut 3 which will let you plot your spectrum, but that's somewhat
> staggered. Having it display on a continuous basis will take a fair amount
> more work and will probably require having a 10 GbE connection to a
> computer.
>
> For power vs frequency - each channel represents a nominal centre
> frequency, so it's just a matter of scaling your X-axis in terms of
> fractions of your ADC bandwidth.
>
> Regards,
> James
>
>
> On Mon, Oct 17, 2016 at 9:52 PM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi Everyone
>>
>> I got it wot king using the following commands:
>>
>> ipython --pylab
>> import casperfpga, corr,time,numpy,struct,sys,logging,pylab,matplotlib
>> fpga = casperfpga.katcp_fpga.KatcpFpga('192.168.33.7')
>> fpga.upload_to_ram_and_program('heystek_tut3_2016_Sep_22_1726.fpg')
>> fpga.write_int('acc_len',2*(2**28)/2048)
>> fpga.write_int('gain',0x)
>> fpga.write_int('cnt_rst',1)
>> fpga.write_int('cnt_rst',0)
>> acc_n = fpga.read_uint('acc_cnt')
>> a_0=struct.unpack('>1024l',fpga.read('even',1024*4,0))
>> a_1=struct.unpack('>1024l',fpga.read('odd',1024*4,0))
>>
>> interleave_a=[]
>>
>> for i in range(1024):
>> interleave_a.append(a_0[i])
>> interleave_a.append(a_1[i])
>>
>> fpga.write_int('cnt_rst',1)
>> fpga.write_int('cnt_rst',0)
>>
>> pylab.figure(num=1,figsize=(10,10))
>> pylab.plot(interleave_a)
>> pylab.title('Integration number %i.'%acc_n)
>> pylab.ylabel('Power (arbitrary units)')
>> pylab.grid()
>> pylab.xlabel('Channel')
>> pylab.xlim(0,2048)
>> pylab.show()
>>
>> I don't get the exact same output as the image on the casper site, but I
>> think it is due to the integration size, but I get output.
>>
>> This my seem like stupid questions but I have two questions.
>>
>> The first is. How can I plot frequency vs power and not channel vs power?
>>
>> The second question is. I want to hook up an FM antenna to the ADC and
>> see if I get "live" data. How to I do that? Do I need to create a .bof file
>> somehow? and if so, how do I do it.
>>
>> Thanks for all for help
>>
>> Heystek
>>
>> On Tue, Oct 11, 2016 at 5:20 PM, lij...@xao.ac.cn <lij...@xao.ac.cn>
>> wrote:
>>
>>> mybe your katcp is too new(0.6?),try to install 0.5.5
>>> if you use pip,just run : sudo pip install katcp==0.5.5
>>>
>>> 发自我的华为手机
>>>
>>>
>>>  原始邮件 
>>> 主题：Re: [casper] Programming a ROACH2
>>> 发件人：David MacMahon
>>> 收件人：Jason Manley
>>> 抄送：Casper Lists ,Ryan Monroe
>>>
>>>
>>> I think the intent of exit_fail() is to try to close the connection,
>>> ignore any exceptions raised while trying to close the connection, and then
>>> re-raise the original exception that happened before exit_fail was called,
>>> but I think the implementation is flawed. Here’s the definition of
>>> exit_fail() as it appears on GitHub:
>>>
>>> def exit_fail():
>>> print 'FAILURE DETECTED. Log entries:\n',lh.printMessages()
>>> try:
>>> fpga.stop()
>>> except: pass
>>> raise
>>> exit()
>>>
>>> I think this try/except block (with "pass" in the except part) followed
>>> by "raise" is completely superfluous. I think it means try to do something
>>> and if an exception is raised while trying, ignore it but then re-raise it,
>>> which seems exactly the same as not having the try/except block there at
>>> all! Not to mention that the exit() call will never be reached. I’m also
>>> not a fan of functions that can only be called while an exception is being
>>> handled (otherwise the no-arg form of "raise" will bomb out I think).
>>>
>>> It would probably be preferable to pass the original exception to
>>> exit_fail() as an argument so that the original exception can be re-raised.
>>> I can make that change when I get back to Berkeley next week (unless
>>&g

Re: [casper] 回复: Programming a ROACH2

[Heystek Grobler]

Hi Everyone

I got it wot king using the following commands:

ipython --pylab
import casperfpga, corr,time,numpy,struct,sys,logging,pylab,matplotlib
fpga = casperfpga.katcp_fpga.KatcpFpga('192.168.33.7')
fpga.upload_to_ram_and_program('heystek_tut3_2016_Sep_22_1726.fpg')
fpga.write_int('acc_len',2*(2**28)/2048)
fpga.write_int('gain',0x)
fpga.write_int('cnt_rst',1)
fpga.write_int('cnt_rst',0)
acc_n = fpga.read_uint('acc_cnt')
a_0=struct.unpack('>1024l',fpga.read('even',1024*4,0))
a_1=struct.unpack('>1024l',fpga.read('odd',1024*4,0))

interleave_a=[]

for i in range(1024):
interleave_a.append(a_0[i])
interleave_a.append(a_1[i])

fpga.write_int('cnt_rst',1)
fpga.write_int('cnt_rst',0)

pylab.figure(num=1,figsize=(10,10))
pylab.plot(interleave_a)
pylab.title('Integration number %i.'%acc_n)
pylab.ylabel('Power (arbitrary units)')
pylab.grid()
pylab.xlabel('Channel')
pylab.xlim(0,2048)
pylab.show()

I don't get the exact same output as the image on the casper site, but I
think it is due to the integration size, but I get output.

This my seem like stupid questions but I have two questions.

The first is. How can I plot frequency vs power and not channel vs power?

The second question is. I want to hook up an FM antenna to the ADC and see
if I get "live" data. How to I do that? Do I need to create a .bof file
somehow? and if so, how do I do it.

Thanks for all for help

Heystek

On Tue, Oct 11, 2016 at 5:20 PM, lij...@xao.ac.cn <lij...@xao.ac.cn> wrote:

> mybe your katcp is too new(0.6?),try to install 0.5.5
> if you use pip,just run : sudo pip install katcp==0.5.5
>
> 发自我的华为手机
>
>
>  原始邮件 
> 主题：Re: [casper] Programming a ROACH2
> 发件人：David MacMahon
> 收件人：Jason Manley
> 抄送：Casper Lists ,Ryan Monroe
>
>
> I think the intent of exit_fail() is to try to close the connection,
> ignore any exceptions raised while trying to close the connection, and then
> re-raise the original exception that happened before exit_fail was called,
> but I think the implementation is flawed. Here’s the definition of
> exit_fail() as it appears on GitHub:
>
> def exit_fail():
> print 'FAILURE DETECTED. Log entries:\n',lh.printMessages()
> try:
> fpga.stop()
> except: pass
> raise
> exit()
>
> I think this try/except block (with "pass" in the except part) followed by
> "raise" is completely superfluous. I think it means try to do something and
> if an exception is raised while trying, ignore it but then re-raise it,
> which seems exactly the same as not having the try/except block there at
> all! Not to mention that the exit() call will never be reached. I’m also
> not a fan of functions that can only be called while an exception is being
> handled (otherwise the no-arg form of "raise" will bomb out I think).
>
> It would probably be preferable to pass the original exception to
> exit_fail() as an argument so that the original exception can be re-raised.
> I can make that change when I get back to Berkeley next week (unless
> someone beats me to it).
>
> Sorry for veering so far off topic,
> Dave
>
>
> > On Oct 11, 2016, at 10:16, Jason Manley wrote:
> >
> > Some of the earlier scripts had bad error handling. If anything fails
> before the host object was successfully created, then you get this error
> because it tries to close the connection before exiting.
> >
> > Jason
> >
> > On 11 Oct 2016, at 16:09, David MacMahon wrote:
> >
> >>
> >>> On Oct 11, 2016, at 06:46, Heystek Grobler wrote:
> >>>
> >>> Connecting to server 192.168.33.7 on port 7147... FAILURE DETECTED
> >>
> >> Editorial comments on error handling in tut3.py aside, I think the fact
> that "FAILURE DETECTED" follows "Connecting to server…" on the same line
> (i.e. no newline character inbetween) means that something went wrong when
> constructing the FpgaClient object which connects to TCP port 7147 of the
> ROACH2 with IP address 192.168.33.7. This is expecting the ROACH2 to have a
> tcpborphserver process listening on that port.
> >>
> >> What happens when you run:
> >>
> >> telnet 198.168.33.7 7147
> >>
> >> HTH,
> >> Dave
> >>
> >
>
>
>

Re: [casper] Programming a ROACH2

[Heystek Grobler]

Hi

I am now trying to do this manually line by line through ipython.

Do anyone perhaps know what is the equivalent for the roach2 of the
following function?
fpga.progdev()

a_0=struct.unpack('>1024l',fpga.read('even',1024*4,0))
a_1=struct.unpack('>1024l',fpga.read('odd',1024*4,0))



On Tue, Oct 11, 2016 at 1:43 PM, James Smith <jsm...@ska.ac.za> wrote:

> Hello Heystek,
>
> Having looked at the tut3 which is on the website, it is using the older
> corr library, not casperfpga. It also looks as though it's intended for
> ROACH and not ROACH2, I'm not sure whether that's an issue. I've never used
> a ROACH2.
>
> I was under the impression that it should have been updated for the recent
> CASPER workshop. Can someone comment on this?
>
> It might be an interesting exercise to try and use the model files to
> compile for ROACH2 then to write your own script, using this one as a
> guide. You'd learn a lot about how things work in the process. Not a quick
> fix to your problem, I'll admit, but it'll be an education.
>
> Regards,
> James
>
>
> On Tue, Oct 11, 2016 at 1:33 PM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi James
>>
>> Through ipython I can connect to the Roach and upload the .fga file. I
>> can also ping the roach.The problem comes in using the script with the .bof
>> file. I am very new to python but have training in C, C#, Java and Assembly.
>>
>> I run the script as follows:
>> python tut3.py 192.168.33.7
>>
>>
>> On Tue, Oct 11, 2016 at 1:06 PM, James Smith <jsm...@ska.ac.za> wrote:
>>
>>> Hello Heystek,
>>>
>>> How cognisant are you with Python? Try opening an ipython session and
>>> connecting to your ROACH manually, I think you have been able to do that in
>>> the past.
>>>
>>> This error message means that your network can't reach the ROACH for
>>> some reason.
>>>
>>> Regards,
>>> James
>>>
>>>
>>> On Tue, Oct 11, 2016 at 12:46 PM, Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>>
>>>> Hi Everyone
>>>>
>>>> After trying all of your suggestions and install a few more packages is
>>>> works. I get the following error now when I run the tut3.py script for 
>>>> tut3.
>>>>
>>>> heystek@heystek-HP-G62-Notebook-PC:~/simulink/heystek_tutorial_3/heystek_tut3$
>>>> ./tut3.py 192.168.33.7 tut3.bofConnecting to server 192.168.33.7 on port
>>>> 7147...  FAILURE DETECTED. Log entries:
>>>> None
>>>> Traceback (most recent call last):
>>>>   File "./tut3.py", line 141, in 
>>>> exit_fail()
>>>>   File "./tut3.py", line 21, in exit_fail
>>>> fpga.stop()
>>>> NameError: global name 'fpga' is not defined
>>>>
>>>>
>>>> Any ideas on how to solve this?
>>>>
>>>> Thank you
>>>>
>>>> Heystek
>>>>
>>>> On Fri, Oct 7, 2016 at 9:05 PM, Ryan Monroe <ryan.m.mon...@gmail.com>
>>>> wrote:
>>>>
>>>>> I would suggest using "pip uninstall spead" instead -- I don't recall
>>>>> ever using it myself, but it appears to be the pip-sanctioned way of
>>>>> removing something.
>>>>>
>>>>> On 10/07/2016 02:24 AM, James Smith wrote:
>>>>>
>>>>> Hello Heystek,
>>>>>
>>>>> Pip is seeing that you've already got a version of Spead installed,
>>>>> which might not have worked. You can delete the directory to 'uninstall' 
>>>>> it
>>>>> (Request for comment: is this a safe approach? It's what I've always done
>>>>> with no problems.)
>>>>>
>>>>> Before you try that though, perhaps just try importing spead in
>>>>> ipython as Ryan did. What are the error messages?
>>>>>
>>>>> Regards,
>>>>> James
>>>>>
>>>>>
>>>>> On Fri, Oct 7, 2016 at 11:23 AM, Heystek Grobler <
>>>>> heystekgrob...@gmail.com> wrote:
>>>>>
>>>>>> Hi James and Ryan
>>>>>>
>>>>>> I tried sudo pip install spead and I get the following
>>>>>>
>>>>>> Requirment already satisfied (use --upgrade): spead in
>>>>>> usr/local/lib/python2.7/dist-packages
>>>>>> cleaning up
>>&g

Re: [casper] Programming a ROACH2

[Heystek Grobler]

Hi Everyone

After trying all of your suggestions and install a few more packages is
works. I get the following error now when I run the tut3.py script for tut3.

heystek@heystek-HP-G62-Notebook-PC:~/simulink/heystek_tutorial_3/heystek_tut3$
./tut3.py 192.168.33.7 tut3.bofConnecting to server 192.168.33.7 on port
7147...  FAILURE DETECTED. Log entries:
None
Traceback (most recent call last):
  File "./tut3.py", line 141, in 
exit_fail()
  File "./tut3.py", line 21, in exit_fail
fpga.stop()
NameError: global name 'fpga' is not defined


Any ideas on how to solve this?

Thank you

Heystek

On Fri, Oct 7, 2016 at 9:05 PM, Ryan Monroe <ryan.m.mon...@gmail.com> wrote:

> I would suggest using "pip uninstall spead" instead -- I don't recall ever
> using it myself, but it appears to be the pip-sanctioned way of removing
> something.
>
> On 10/07/2016 02:24 AM, James Smith wrote:
>
> Hello Heystek,
>
> Pip is seeing that you've already got a version of Spead installed, which
> might not have worked. You can delete the directory to 'uninstall' it
> (Request for comment: is this a safe approach? It's what I've always done
> with no problems.)
>
> Before you try that though, perhaps just try importing spead in ipython as
> Ryan did. What are the error messages?
>
> Regards,
> James
>
>
> On Fri, Oct 7, 2016 at 11:23 AM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi James and Ryan
>>
>> I tried sudo pip install spead and I get the following
>>
>> Requirment already satisfied (use --upgrade): spead in
>> usr/local/lib/python2.7/dist-packages
>> cleaning up
>>
>> Any ideas?
>>
>> I am a bit lost to be honest.
>>
>> On Fri, Oct 7, 2016 at 11:09 AM, James Smith <jsm...@ska.ac.za> wrote:
>>
>>> Hello Heystek,
>>>
>>> I vaguely recall installing spead from pip as well, as Ryan has done
>>> here. Give that a whirl.
>>>
>>> Regards,
>>> James
>>>
>>>
>>> On Fri, Oct 7, 2016 at 11:06 AM, Ryan Monroe <ryan.m.mon...@gmail.com>
>>> wrote:
>>>
>>>> rmonroe@rmonroe-ThinkPad-P50:~$ sudo pip install spead
>>>> [sudo] password for rmonroe:
>>>> The directory '/home/rmonroe/.cache/pip/http' or its parent directory
>>>> is not owned by the current user and the cache has been disabled. Please
>>>> check the permissions and owner of that directory. If executing pip with
>>>> sudo, you may want sudo's -H flag.
>>>> The directory '/home/rmonroe/.cache/pip' or its parent directory is not
>>>> owned by the current user and caching wheels has been disabled. check the
>>>> permissions and owner of that directory. If executing pip with sudo, you
>>>> may want sudo's -H flag.
>>>> Collecting spead
>>>>   Downloading spead-0.5.1.tar.gz (61kB)
>>>> 100% || 71kB 1.5MB/s
>>>> Installing collected packages: spead
>>>>   Running setup.py install for spead ... done
>>>> Successfully installed spead-0.5.1
>>>> rmonroe@rmonroe-ThinkPad-P50:~$ ipython
>>>> Python 2.7.12 (default, Jul  1 2016, 15:12:24)
>>>> Type "copyright", "credits" or "license" for more information.
>>>>
>>>> IPython 2.4.1 -- An enhanced Interactive Python.
>>>> ? -> Introduction and overview of IPython's features.
>>>> %quickref -> Quick reference.
>>>> help  -> Python's own help system.
>>>> object?   -> Details about 'object', use 'object??' for extra details.
>>>>
>>>> In [1]: import spead
>>>>
>>>> In [2]:
>>>>
>>>>
>>>> On 10/07/2016 02:04 AM, Heystek Grobler wrote:
>>>>
>>>> Hi James
>>>>
>>>> I installed the PySpead package but I get the following error when I
>>>> run the tut3.py script:
>>>>
>>>> ImportError: No mode named spead
>>>>
>>>> Do you perhaps have any ideas on how to solve it?
>>>>
>>>> Thank you!!
>>>>
>>>> Heystek
>>>>
>>>> On Fri, Oct 7, 2016 at 11:01 AM, James Smith <jsm...@ska.ac.za> wrote:
>>>>
>>>>> Hello Heystek,
>>>>>
>>>>> If you're still in the Python environment, then PySpead is the one you
>>>>> want.
>>>>>
>>>>> Regards,
>>>>> James
>>>>>

Re: [casper] Programming a ROACH2

[Heystek Grobler]

Hi James

I installed the PySpead package but I get the following error when I run
the tut3.py script:

ImportError: No mode named spead

Do you perhaps have any ideas on how to solve it?

Thank you!!

Heystek

On Fri, Oct 7, 2016 at 11:01 AM, James Smith <jsm...@ska.ac.za> wrote:

> Hello Heystek,
>
> If you're still in the Python environment, then PySpead is the one you
> want.
>
> Regards,
> James
>
>
> On Fri, Oct 7, 2016 at 10:59 AM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Good Day
>>
>> After a while of troubleshooting I determined the connection with TCP/IP
>> into the board was correct. I updated the file system and kernel of the
>> ROACH2 and now I can program it.
>>
>> I only need to install a package called spead in order to use the .bof
>> file with tutorial 3 of CASPER.
>>
>> Where can a download the spead package from? I can only find PySpead and
>> Spead2.
>>
>> Thanks for everyones help
>>
>> Heystek!
>>
>> On Fri, Sep 30, 2016 at 5:28 PM, Adam Isaacson <aisaac...@ska.ac.za>
>> wrote:
>>
>>> Hi Heystek,
>>>
>>> If you want to telnet, which is another way of configuring your board,
>>> then you need to state the port. Are you doing the following from the
>>> terminal:
>>>
>>> 1)Telnet to port 7147: "telnet  7147".
>>>
>>> 2)?progremote fpgfile.fpg
>>>
>>> You say you can ping your board, so you should be able to connect via
>>> casperfpga, as you mentioned above. Did you do what James suggested i.e.
>>> try running fpga.is_connected()? if it reports "True" then you are
>>> connected and if false then you will need to debug further. Are you sure
>>> that the IP you are pinging is your roach2 - may sound like a silly
>>> question, but I don't know your setup.
>>>
>>> Kind Regards,
>>>
>>> Adam
>>>
>>>
>>> On Fri, Sep 30, 2016 at 3:38 PM, Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>>
>>>> Hi James
>>>>
>>>> I will try it. Through the terminal I can ping the board, but I cant
>>>> open a Telnet connection.
>>>>
>>>> When I open a ttyUSB connection to the Roach en monitor it, and try to
>>>> upload the fga file, the Roach gives the same error "progremote"
>>>>
>>>> Thats why I'm confused
>>>>
>>>> Thanks for your help!
>>>>
>>>> I really appreciate it
>>>>
>>>> Heystek
>>>>
>>>>
>>>> On Friday, 30 September 2016, James Smith <jsm...@ska.ac.za> wrote:
>>>>
>>>>> Hello Heystek,
>>>>>
>>>>> Before you program the ROACH2, I'd suggest trying fpga.is_connected()
>>>>> and fpga.est_clk_frequency() to check whether you can actually
>>>>> communicate with the ROACH2. It might be a network cable that's been
>>>>> unplugged by accident - that's where I've seen those errors before. The
>>>>> fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address')
>>>>> doesn't actually throw an error if it can't connect to the ROACH2. This
>>>>> information would at least help you narrow down the possibilities as to
>>>>> what's wrong (i.e. whether it's the kernel on the ROACH2).
>>>>>
>>>>> Disclaimer: I work only on ROACH, but I'm fairly certain the procedure
>>>>> would be the same.
>>>>>
>>>>> Regards,
>>>>> James
>>>>>
>>>>>
>>>>> On Fri, Sep 30, 2016 at 1:36 PM, Heystek Grobler <
>>>>> heystekgrob...@gmail.com> wrote:
>>>>>
>>>>>> Good day everyone
>>>>>>
>>>>>> I am having difficulties programming the ROACH 2 board. I am
>>>>>> following the instructions of CASPER tutorial one.
>>>>>>
>>>>>> I Have compiled the fpg file and is using the following steps from
>>>>>> the tutorial.
>>>>>>
>>>>>> 1. I entered ipython into the terminal
>>>>>> 2. import casperfpga
>>>>>> 3. fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address')
>>>>>> with the ip address of my roach
>>>>>> 4. fpga.upload_to_ram_and_program('your_fpgfile.fpg') with the
>>>>>> location of the .fpg

Re: [casper] Programming a ROACH2

[Heystek Grobler]

Good Day

After a while of troubleshooting I determined the connection with TCP/IP
into the board was correct. I updated the file system and kernel of the
ROACH2 and now I can program it.

I only need to install a package called spead in order to use the .bof file
with tutorial 3 of CASPER.

Where can a download the spead package from? I can only find PySpead and
Spead2.

Thanks for everyones help

Heystek!

On Fri, Sep 30, 2016 at 5:28 PM, Adam Isaacson <aisaac...@ska.ac.za> wrote:

> Hi Heystek,
>
> If you want to telnet, which is another way of configuring your board,
> then you need to state the port. Are you doing the following from the
> terminal:
>
> 1)Telnet to port 7147: "telnet  7147".
>
> 2)?progremote fpgfile.fpg
>
> You say you can ping your board, so you should be able to connect via
> casperfpga, as you mentioned above. Did you do what James suggested i.e.
> try running fpga.is_connected()? if it reports "True" then you are
> connected and if false then you will need to debug further. Are you sure
> that the IP you are pinging is your roach2 - may sound like a silly
> question, but I don't know your setup.
>
> Kind Regards,
>
> Adam
>
>
> On Fri, Sep 30, 2016 at 3:38 PM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi James
>>
>> I will try it. Through the terminal I can ping the board, but I cant open
>> a Telnet connection.
>>
>> When I open a ttyUSB connection to the Roach en monitor it, and try to
>> upload the fga file, the Roach gives the same error "progremote"
>>
>> Thats why I'm confused
>>
>> Thanks for your help!
>>
>> I really appreciate it
>>
>> Heystek
>>
>>
>> On Friday, 30 September 2016, James Smith <jsm...@ska.ac.za> wrote:
>>
>>> Hello Heystek,
>>>
>>> Before you program the ROACH2, I'd suggest trying fpga.is_connected()
>>> and fpga.est_clk_frequency() to check whether you can actually
>>> communicate with the ROACH2. It might be a network cable that's been
>>> unplugged by accident - that's where I've seen those errors before. The
>>> fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') doesn't
>>> actually throw an error if it can't connect to the ROACH2. This information
>>> would at least help you narrow down the possibilities as to what's wrong
>>> (i.e. whether it's the kernel on the ROACH2).
>>>
>>> Disclaimer: I work only on ROACH, but I'm fairly certain the procedure
>>> would be the same.
>>>
>>> Regards,
>>> James
>>>
>>>
>>> On Fri, Sep 30, 2016 at 1:36 PM, Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>>
>>>> Good day everyone
>>>>
>>>> I am having difficulties programming the ROACH 2 board. I am following
>>>> the instructions of CASPER tutorial one.
>>>>
>>>> I Have compiled the fpg file and is using the following steps from the
>>>> tutorial.
>>>>
>>>> 1. I entered ipython into the terminal
>>>> 2. import casperfpga
>>>> 3. fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address')
>>>> with the ip address of my roach
>>>> 4. fpga.upload_to_ram_and_program('your_fpgfile.fpg') with the
>>>> location of the .fpga file
>>>>
>>>> but at point 4 I get the following error:
>>>>
>>>> RuntimeError  Traceback (most recent call
>>>> last)
>>>>  in ()
>>>> > 1 fpga.upload_to_ram_and_program('/home/heystek/simulink/ai_t1
>>>> /bit_files/ai_t1_2016_Sep_14_2052.fpg')
>>>>
>>>> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
>>>> upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
>>>> 442 if request_result != '':
>>>> 443 raise RuntimeError('progremote request(%s) on host
>>>> %s failed' %
>>>> --> 444(request_result, self.host))
>>>> 445
>>>> 446 # start the upload thread and join
>>>>
>>>> RuntimeError: progremote request(Request to client 192.168.33.4
>>>> failed.) on host 192.168.33.4 failed
>>>>
>>>> Am I doing something wrong?
>>>>
>>>> I looked at the mail archives and it sugested that I update the kernel
>>>> of the roach. Is this perhaps the problem? Or am I doing something wrong?
>>>>
>>>> Have a wonderful day.
>>>>
>>>> Heystek
>>>>
>>>
>>>
>
>
> --
>
> Adam Isaacson
>
> DBE: FPGA Engineer
>
> SKA-SA
>
> 3rd Floor
>
> The Park
>
> Park Road
>
> Pinelands
>
> 7405
>
>
> Tel: +27215067300 (W)
>
> Fax: +27215067375 (W)
>
> Cell: +27825639602
>

Re: [casper] Programming a ROACH2

[Heystek Grobler]

Hi James

I will try it. Through the terminal I can ping the board, but I cant open a
Telnet connection.

When I open a ttyUSB connection to the Roach en monitor it, and try to
upload the fga file, the Roach gives the same error "progremote"

Thats why I'm confused

Thanks for your help!

I really appreciate it

Heystek

On Friday, 30 September 2016, James Smith <jsm...@ska.ac.za> wrote:

> Hello Heystek,
>
> Before you program the ROACH2, I'd suggest trying fpga.is_connected() and
> fpga.est_clk_frequency() to check whether you can actually communicate
> with the ROACH2. It might be a network cable that's been unplugged by
> accident - that's where I've seen those errors before. The
> fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') doesn't
> actually throw an error if it can't connect to the ROACH2. This information
> would at least help you narrow down the possibilities as to what's wrong
> (i.e. whether it's the kernel on the ROACH2).
>
> Disclaimer: I work only on ROACH, but I'm fairly certain the procedure
> would be the same.
>
> Regards,
> James
>
>
> On Fri, Sep 30, 2016 at 1:36 PM, Heystek Grobler <heystekgrob...@gmail.com
> <javascript:_e(%7B%7D,'cvml','heystekgrob...@gmail.com');>> wrote:
>
>> Good day everyone
>>
>> I am having difficulties programming the ROACH 2 board. I am following
>> the instructions of CASPER tutorial one.
>>
>> I Have compiled the fpg file and is using the following steps from the
>> tutorial.
>>
>> 1. I entered ipython into the terminal
>> 2. import casperfpga
>> 3. fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') with
>> the ip address of my roach
>> 4. fpga.upload_to_ram_and_program('your_fpgfile.fpg') with the location
>> of the .fpga file
>>
>> but at point 4 I get the following error:
>>
>> RuntimeError  Traceback (most recent call
>> last)
>>  in ()
>> > 1 fpga.upload_to_ram_and_program('/home/heystek/simulink/ai_t1
>> /bit_files/ai_t1_2016_Sep_14_2052.fpg')
>>
>> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
>> upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
>> 442 if request_result != '':
>> 443 raise RuntimeError('progremote request(%s) on host %s
>> failed' %
>> --> 444(request_result, self.host))
>> 445
>> 446 # start the upload thread and join
>>
>> RuntimeError: progremote request(Request to client 192.168.33.4 failed.)
>> on host 192.168.33.4 failed
>>
>> Am I doing something wrong?
>>
>> I looked at the mail archives and it sugested that I update the kernel of
>> the roach. Is this perhaps the problem? Or am I doing something wrong?
>>
>> Have a wonderful day.
>>
>> Heystek
>>
>
>

[casper] Programming a ROACH2

[Heystek Grobler]

Good day everyone

I am having difficulties programming the ROACH 2 board. I am following the
instructions of CASPER tutorial one.

I Have compiled the fpg file and is using the following steps from the
tutorial.

1. I entered ipython into the terminal
2. import casperfpga
3. fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') with the
ip address of my roach
4. fpga.upload_to_ram_and_program('your_fpgfile.fpg') with the location of
the .fpga file

but at point 4 I get the following error:

RuntimeError  Traceback (most recent call last)
 in ()
> 1 fpga.upload_to_ram_and_program('/home/heystek/
simulink/ai_t1/bit_files/ai_t1_2016_Sep_14_2052.fpg')

/usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
442 if request_result != '':
443 raise RuntimeError('progremote request(%s) on host %s
failed' %
--> 444(request_result, self.host))
445
446 # start the upload thread and join

RuntimeError: progremote request(Request to client 192.168.33.4 failed.) on
host 192.168.33.4 failed

Am I doing something wrong?

I looked at the mail archives and it sugested that I update the kernel of
the roach. Is this perhaps the problem? Or am I doing something wrong?

Have a wonderful day.

Heystek

Re: [casper] Help with Casper Tutorial 3

[Heystek Grobler]

Good day

My University got me a license for MATLAB 2012b with the DSP System Toolbox
and the 3rd Tutorial from CASPER compiles now.

Thank you for everything!

Heystek

On Wed, Sep 21, 2016 at 9:53 AM, Jack Hickish <jackhick...@gmail.com> wrote:

> Hi Heystek,
>
> There's always a chance it will work, but my guess is you'll run into all
> kinds of strange problems. If you can, I'd *strongly* recommend trying to
> get hold of a supported MATLAB version.
>
> Jack
>
> On Wed, 21 Sep 2016 at 00:43 Heystek Grobler <heystekgrob...@gmail.com>
> wrote:
>
>> Hi Jack
>>
>> Do you perhaps know if MATLAB 2016b will work with ISE 14.7? I can get
>> hold of a license for MATLAB 2016b with according the this link below, ISE
>> 14.7 only works with MATLAB 2013b and not above.
>>
>> http://www.xilinx.com/support/answers/17966.html
>>
>> Have a nice day
>>
>> Heystek
>>
>>
>>
>>
>> On Tue, Sep 20, 2016 at 10:40 PM, Jack Hickish <jackhick...@gmail.com>
>> wrote:
>>
>>> Hi Heystek,
>>>
>>> You can also just delete the simulation blocks inside the ADC for the
>>> time being. You don't need them to compile the design, only to be able to
>>> simulate the ADC analog inputs properly.
>>>
>>> Cheers
>>> Jack
>>>
>>> On Tue, 20 Sep 2016 at 13:32 Heystek Grobler <heystekgrob...@gmail.com>
>>> wrote:
>>>
>>>> Hi Michael
>>>>
>>>> Thanks for your help. I will try to obtain a license for the DSP System
>>>> Toolbox.
>>>>
>>>> Have a wonderful evening
>>>>
>>>> Heystek
>>>>
>>>> On Tue, Sep 20, 2016 at 10:28 PM, Michael D'Cruze <
>>>> michael.dcr...@postgrad.manchester.ac.uk> wrote:
>>>>
>>>>> Hi Heystek,
>>>>>
>>>>>
>>>>>
>>>>> You need the DSP System Toolbox unfortunately, in order to compile the
>>>>> ADC blocks. This is typically a paid-for toolbox, though my local IT
>>>>> Services were helpful and had a few spare server licences.
>>>>>
>>>>>
>>>>>
>>>>> BW
>>>>> Michael
>>>>>
>>>>>
>>>>>
>>>>> *From:* Heystek Grobler [mailto:heystekgrob...@gmail.com]
>>>>> *Sent:* 20 September 2016 21:24
>>>>> *To:* Michael D'Cruze
>>>>> *Cc:* Casper Lists
>>>>> *Subject:* Re: [casper] Help with Casper Tutorial 3
>>>>>
>>>>>
>>>>>
>>>>> Hi Michael
>>>>>
>>>>> This is the toolboxes that I have:
>>>>>
>>>>> MATLAB Version: 8.0.0.783 (R2012b)
>>>>> MATLAB License Number: 724504
>>>>> Operating System: Linux 3.19.0-68-generic #76~14.04.1-Ubuntu SMP Fri
>>>>> Aug 12 11:46:25 UTC 2016 x86_64
>>>>> Java Version: Java 1.6.0_17-b04 with Sun Microsystems Inc. Java
>>>>> HotSpot(TM) 64-Bit Server VM mixed mode
>>>>> 
>>>>> ---
>>>>> MATLABVersion
>>>>> 8.0(R2012b)
>>>>> Simulink  Version
>>>>> 8.0(R2012b)
>>>>> Bioinformatics ToolboxVersion
>>>>> 4.2(R2012b)
>>>>> Curve Fitting Toolbox Version
>>>>> 3.3(R2012b)
>>>>> Database Toolbox  Version
>>>>> 4.0(R2012b)
>>>>> Datafeed Toolbox  Version
>>>>> 4.4(R2012b)
>>>>> Econometrics Toolbox  Version
>>>>> 2.2(R2012b)
>>>>> Financial Instruments Toolbox Version
>>>>> 1.0(R2012b)
>>>>> Financial Toolbox Version
>>>>> 5.0(R2012b)
>>>>> Fuzzy Logic Toolbox   Version
>>>>> 2.2.16 (R2012b)
>>>>> Global Optimization Toolbox   Version
>>>>> 3.2.2  (R2012b)
>>>>> Image Acquisition Toolbox

Re: [casper] Help with Casper Tutorial 3

[Heystek Grobler]

Hi Jack

Do you perhaps know if MATLAB 2016b will work with ISE 14.7? I can get hold
of a license for MATLAB 2016b with according the this link below, ISE 14.7
only works with MATLAB 2013b and not above.

http://www.xilinx.com/support/answers/17966.html

Have a nice day

Heystek




On Tue, Sep 20, 2016 at 10:40 PM, Jack Hickish <jackhick...@gmail.com>
wrote:

> Hi Heystek,
>
> You can also just delete the simulation blocks inside the ADC for the time
> being. You don't need them to compile the design, only to be able to
> simulate the ADC analog inputs properly.
>
> Cheers
> Jack
>
> On Tue, 20 Sep 2016 at 13:32 Heystek Grobler <heystekgrob...@gmail.com>
> wrote:
>
>> Hi Michael
>>
>> Thanks for your help. I will try to obtain a license for the DSP System
>> Toolbox.
>>
>> Have a wonderful evening
>>
>> Heystek
>>
>> On Tue, Sep 20, 2016 at 10:28 PM, Michael D'Cruze <
>> michael.dcr...@postgrad.manchester.ac.uk> wrote:
>>
>>> Hi Heystek,
>>>
>>>
>>>
>>> You need the DSP System Toolbox unfortunately, in order to compile the
>>> ADC blocks. This is typically a paid-for toolbox, though my local IT
>>> Services were helpful and had a few spare server licences.
>>>
>>>
>>>
>>> BW
>>> Michael
>>>
>>>
>>>
>>> *From:* Heystek Grobler [mailto:heystekgrob...@gmail.com]
>>> *Sent:* 20 September 2016 21:24
>>> *To:* Michael D'Cruze
>>> *Cc:* Casper Lists
>>> *Subject:* Re: [casper] Help with Casper Tutorial 3
>>>
>>>
>>>
>>> Hi Michael
>>>
>>> This is the toolboxes that I have:
>>>
>>> MATLAB Version: 8.0.0.783 (R2012b)
>>> MATLAB License Number: 724504
>>> Operating System: Linux 3.19.0-68-generic #76~14.04.1-Ubuntu SMP Fri Aug
>>> 12 11:46:25 UTC 2016 x86_64
>>> Java Version: Java 1.6.0_17-b04 with Sun Microsystems Inc. Java
>>> HotSpot(TM) 64-Bit Server VM mixed mode
>>> 
>>> ---
>>> MATLABVersion
>>> 8.0(R2012b)
>>> Simulink  Version
>>> 8.0(R2012b)
>>> Bioinformatics ToolboxVersion
>>> 4.2(R2012b)
>>> Curve Fitting Toolbox Version
>>> 3.3(R2012b)
>>> Database Toolbox  Version
>>> 4.0(R2012b)
>>> Datafeed Toolbox  Version
>>> 4.4(R2012b)
>>> Econometrics Toolbox  Version
>>> 2.2(R2012b)
>>> Financial Instruments Toolbox Version
>>> 1.0(R2012b)
>>> Financial Toolbox Version
>>> 5.0(R2012b)
>>> Fuzzy Logic Toolbox   Version
>>> 2.2.16 (R2012b)
>>> Global Optimization Toolbox   Version
>>> 3.2.2  (R2012b)
>>> Image Acquisition Toolbox Version
>>> 4.4(R2012b)
>>> Image Processing Toolbox  Version
>>> 8.1(R2012b)
>>> Instrument Control ToolboxVersion
>>> 3.2(R2012b)
>>> MATLAB Compiler   Version
>>> 4.18   (R2012b)
>>> Mapping Toolbox   Version
>>> 3.6(R2012b)
>>> Neural Network ToolboxVersion
>>> 8.0(R2012b)
>>> Optimization Toolbox  Version
>>> 6.2.1  (R2012b)
>>> Parallel Computing ToolboxVersion
>>> 6.1(R2012b)
>>> Partial Differential Equation Toolbox Version 1.1
>>> (R2012b)
>>> Signal Processing Toolbox Version
>>> 6.18   (R2012b)
>>> SimMechanics  Version
>>> 4.1(R2012b)
>>> Simscape  Version
>>> 3.8(R2012b)
>>> Simulink 3D Animation Version
>>> 6.2(R2012b)
>>> Stateflow V

Re: [casper] Help with Casper Tutorial 3

[Heystek Grobler]

Hi Michael

Thanks for your help. I will try to obtain a license for the DSP System
Toolbox.

Have a wonderful evening

Heystek

On Tue, Sep 20, 2016 at 10:28 PM, Michael D'Cruze <
michael.dcr...@postgrad.manchester.ac.uk> wrote:

> Hi Heystek,
>
>
>
> You need the DSP System Toolbox unfortunately, in order to compile the ADC
> blocks. This is typically a paid-for toolbox, though my local IT Services
> were helpful and had a few spare server licences.
>
>
>
> BW
> Michael
>
>
>
> *From:* Heystek Grobler [mailto:heystekgrob...@gmail.com]
> *Sent:* 20 September 2016 21:24
> *To:* Michael D'Cruze
> *Cc:* Casper Lists
> *Subject:* Re: [casper] Help with Casper Tutorial 3
>
>
>
> Hi Michael
>
> This is the toolboxes that I have:
>
> MATLAB Version: 8.0.0.783 (R2012b)
> MATLAB License Number: 724504
> Operating System: Linux 3.19.0-68-generic #76~14.04.1-Ubuntu SMP Fri Aug
> 12 11:46:25 UTC 2016 x86_64
> Java Version: Java 1.6.0_17-b04 with Sun Microsystems Inc. Java
> HotSpot(TM) 64-Bit Server VM mixed mode
> 
> ---
> MATLABVersion 8.0
> (R2012b)
> Simulink  Version 8.0
> (R2012b)
> Bioinformatics ToolboxVersion 4.2
> (R2012b)
> Curve Fitting Toolbox Version 3.3
> (R2012b)
> Database Toolbox  Version 4.0
> (R2012b)
> Datafeed Toolbox  Version 4.4
> (R2012b)
> Econometrics Toolbox  Version 2.2
> (R2012b)
> Financial Instruments Toolbox Version 1.0
> (R2012b)
> Financial Toolbox Version 5.0
> (R2012b)
> Fuzzy Logic Toolbox   Version 2.2.16
> (R2012b)
> Global Optimization Toolbox   Version 3.2.2
> (R2012b)
> Image Acquisition Toolbox Version 4.4
> (R2012b)
> Image Processing Toolbox  Version 8.1
> (R2012b)
> Instrument Control ToolboxVersion 3.2
> (R2012b)
> MATLAB Compiler   Version 4.18
> (R2012b)
> Mapping Toolbox   Version 3.6
> (R2012b)
> Neural Network ToolboxVersion 8.0
> (R2012b)
> Optimization Toolbox  Version 6.2.1
> (R2012b)
> Parallel Computing ToolboxVersion 6.1
> (R2012b)
> Partial Differential Equation Toolbox Version 1.1
> (R2012b)
> Signal Processing Toolbox Version 6.18
> (R2012b)
> SimMechanics  Version 4.1
> (R2012b)
> Simscape  Version 3.8
> (R2012b)
> Simulink 3D Animation Version 6.2
> (R2012b)
> Stateflow Version 8.0
> (R2012b)
> Statistics ToolboxVersion 8.1
> (R2012b)
> Symbolic Math Toolbox Version 5.9
> (R2012b)
> System Identification Toolbox Version 8.1
> (R2012b)
> Wavelet Toolbox   Version 4.10
> (R2012b)
> Xilinx System Generator   Version 14.7
> production build
>
> It seems that the DSP Toolbox is not included. I have the signal
> processing toolbox. Do you have suggestions of what I can do?
>
> Have a wonderful evening
>
> Heystek
>
>
>
>
>
> On Tue, Sep 20, 2016 at 8:58 PM, Michael D'Cruze <michael.dcruze@postgrad.
> manchester.ac.uk> wrote:
>
> Heystek,
>
>
>
> Do you have the DSP System Toolbox installed in Matlab?
>
>
>
> Michael
>
>
>

Re: [casper] Help with Casper Tutorial 3

[Heystek Grobler]

Hi Michael

This is the toolboxes that I have:

MATLAB Version: 8.0.0.783 (R2012b)
MATLAB License Number: 724504
Operating System: Linux 3.19.0-68-generic #76~14.04.1-Ubuntu SMP Fri Aug 12
11:46:25 UTC 2016 x86_64
Java Version: Java 1.6.0_17-b04 with Sun Microsystems Inc. Java HotSpot(TM)
64-Bit Server VM mixed mode
---
MATLABVersion 8.0
(R2012b)
Simulink  Version 8.0
(R2012b)
Bioinformatics ToolboxVersion 4.2
(R2012b)
Curve Fitting Toolbox Version 3.3
(R2012b)
Database Toolbox  Version 4.0
(R2012b)
Datafeed Toolbox  Version 4.4
(R2012b)
Econometrics Toolbox  Version 2.2
(R2012b)
Financial Instruments Toolbox Version 1.0
(R2012b)
Financial Toolbox Version 5.0
(R2012b)
Fuzzy Logic Toolbox   Version 2.2.16
(R2012b)
Global Optimization Toolbox   Version 3.2.2
(R2012b)
Image Acquisition Toolbox Version 4.4
(R2012b)
Image Processing Toolbox  Version 8.1
(R2012b)
Instrument Control ToolboxVersion 3.2
(R2012b)
MATLAB Compiler   Version 4.18
(R2012b)
Mapping Toolbox   Version 3.6
(R2012b)
Neural Network ToolboxVersion 8.0
(R2012b)
Optimization Toolbox  Version 6.2.1
(R2012b)
Parallel Computing ToolboxVersion 6.1
(R2012b)
Partial Differential Equation Toolbox Version 1.1
(R2012b)
Signal Processing Toolbox Version 6.18
(R2012b)
SimMechanics  Version 4.1
(R2012b)
Simscape  Version 3.8
(R2012b)
Simulink 3D Animation Version 6.2
(R2012b)
Stateflow Version 8.0
(R2012b)
Statistics ToolboxVersion 8.1
(R2012b)
Symbolic Math Toolbox Version 5.9
(R2012b)
System Identification Toolbox Version 8.1
(R2012b)
Wavelet Toolbox   Version 4.10
(R2012b)
Xilinx System Generator   Version 14.7
production build

It seems that the DSP Toolbox is not included. I have the signal processing
toolbox. Do you have suggestions of what I can do?

Have a wonderful evening

Heystek


On Tue, Sep 20, 2016 at 8:58 PM, Michael D'Cruze <
michael.dcr...@postgrad.manchester.ac.uk> wrote:

> Heystek,
>
>
>
> Do you have the DSP System Toolbox installed in Matlab?
>
>
>
> Michael
>

[casper] Help with Casper Tutorial 3

[Heystek Grobler]

Good evening

I am trying to do the casper tutorial nr 3 on Ubuntu 14.04 LTS with ISE
14.7.

When I say update model in Simulink or run System generator I get the
following error:

Failed to load library 'dspsigops' referenced by 'tut3/adc/Downsamplei0'

Caused by:
Unable to load block diagram 'dspsigops'

I have tried the CASPER-ASTRO repository as well as the SKA repository.

The error is from the Sample Down Block inside the ADC.

Does anyone know how I can fix this? Tutorial 1 and 2 compiles perfectly.

Have a great evening

Heystek

Re: [casper] Help with Xilinx and Simulink

[Heystek Grobler]

Good Day

I have sorted the out the problems that I was having with my setup. It
basically came down to that my Matlab install file was files missing, I
installed Matlab incorrectly and did not have the correct Xilinx Licence.

Everything is working now.

Thank you for all the suggestions and the help. I really appreciate it!

Keep well

Heystek

On Thu, Aug 25, 2016 at 1:50 PM, Primiani, Rurik <rprimi...@cfa.harvard.edu>
wrote:

> Hi Heystek,
>
> In addition to what Jack suggests it looks like you may have copied
> "tutorial1.slx" to a new model called "tutorial1a.slx" and then immediately
> tried to run the casper_xps. From my experience when this is done some of
> the gateway in/out blocks do not have a chance to change their hierarchical
> names to match the name of the top-level model file. In other words they
> are prepended with "tutorial1_" instead of "tutorial1a_" which causes the
> CASPER toolflow to throw an error.
>
> To fix this try running "Update diagram" from within Simulink (no
> casper_xps) via the "Simulation" menu drop down of your open "tutorial1a"
> model file. Then try the casper_xps flow again.
>
> Hope this helps,
> Rurik
>
>
>
> On Wed, Aug 24, 2016 at 6:18 PM, Jack Hickish <jackhick...@gmail.com>
> wrote:
>
>> Hi Heystek,
>>
>> From a clean install, you shouldn't really have this many problems, and I
>> suspect all your chmod/chown-ing to/from root is just making everything
>> worse.You certainly don't need to run startsg as root (and you shouldn't,
>> who knows what code CASPER collaborators have hidden in there!) and if you
>> do you'll likely create a bunch of temporary files and directories that you
>> now can't write to without root permissions, which will cause pain down the
>> road.
>>
>> It's *possible* that your current problem will go away if you try and
>> force your model and library versions up to date. You can do this by
>> opening your model, and running "update_casper_blocks(bdroot)" at the
>> MATLAB prompt. However, given your permissions problems so far, if it
>> were me I would clean out everything and start again.
>>
>> - Delete your mlib_devel and tutorials_devel directories.
>> - Delete (or change ownership to your normal user account) your MATLAB
>> and Xilinx configuration directories in ~/.matlab/ and ~/.Xilinx/
>> Doing *nothing* with sudo/root:
>> - clone from https://github.com/casper-astro/mlib_devel.git
>> - Modify startsg to point to your MATLAB/Xilinx installs
>> - Make sure you have completed the "tweaks to compile" from
>> https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilin
>> x_14.x_and_Matlab_2012b
>>
>> Run startsg and try and build something.
>>
>> If you're trying to build one of the tutorials, make sure you're either
>> using the correct library version -- see the instructions at
>> https://casper.berkeley.edu/wiki/Tutorials (which I hope has been kept
>> up to date) -- or, after opening a tutorial, run
>> "update_casper_blocks(bdroot)" at the MATLAB prompt, which will make sure
>> the blocks in your library are up to date with your mlib_devel version.
>>
>> Cheers
>> Jack
>>
>> On Wed, 24 Aug 2016 at 13:21 Heystek Grobler <heystekgrob...@gmail.com>
>> wrote:
>>
>>> Good evening
>>>
>>> I am still struggling to get Matlab and Xilinx up and running. I have
>>> noticed that the system generator of Xilinx locks the simulink file during
>>> compilation. It changes the permissions to access only and the  it can not
>>> read and write from it. I have change the permission back to read and write
>>> but as soon as it compiles it locks the file again.
>>>
>>> To try and solve this I have changed the owner of MATLAB and XILINX to
>>> "me" and not root. Now I get the following errors that I attached as
>>> pictures.
>>>
>>> I hope that you can help
>>>
>>> Heystek
>>>
>>>
>>>
>>> On Wed, Aug 17, 2016 at 8:45 AM, Adam Isaacson <aisaac...@ska.ac.za>
>>> wrote:
>>>
>>>> Hi Heystek,
>>>>
>>>> It appears that line 362 of gen_xps_files.m is commented out, so not
>>>> sure what the error pertains to, but still worth checking the pcore compile
>>>> tweaks.
>>>>
>>>> Kind Regards,
>>>>
>>>> Adam
>>>>
>>>> On Tue, Aug 16, 2016 at 11:48 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>>> wrot

Re: [casper] Help with Xilinx and Simulink

[Heystek Grobler]

Hi

I will check that I did everything of the compile tweeks in the casper
webpage. If it does not work I will provide screenshots of the errors.

Thanks for all the help

Heystek

On Wed, Aug 17, 2016 at 8:45 AM, Adam Isaacson <aisaac...@ska.ac.za> wrote:

> Hi Heystek,
>
> It appears that line 362 of gen_xps_files.m is commented out, so not sure
> what the error pertains to, but still worth checking the pcore compile
> tweaks.
>
> Kind Regards,
>
> Adam
>
> On Tue, Aug 16, 2016 at 11:48 PM, Adam Isaacson <aisaac...@ska.ac.za>
> wrote:
>
>> Hi Heystek,
>>
>> I am a bit confused where you are now. Are you still getting the
>> following error in red below or has this been resolved, but now you are
>> encountering another error (Error using gen_xps_files(362)) after you
>> applied the chmod command? Please send screen captures of the actual
>> errors, thanks.
>>
>> Details:
>> standard exception: XNetlistEngine:
>> Exception message could not be parsed:
>> com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first
>> pass text file at
>> /home/heystek/Desktop/tut1/sysgen/sysgen/masterScript423796839757439882
>> 5.pl
>> line 559'
>>
>> I had a brief look at line 362 of gen_xps_files.m and it is connected
>> with the pcores, so once again I have to ask whether you repeated the
>> compile tweaks after you installed ISE 14.7 (
>> https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_14
>> .x_and_Matlab_2012b)? Also, the tut1 Simulink model that I have been
>> working with is a slx file and not an mdl file? What tut 1 file are you
>> using?
>>
>> I am making the assumption that you are based near the Cape Town area? If
>> I am correct and if you are still experiencing difficulties why not bring
>> your machine and pop over? I think this may be the easiest solution :).
>> Just email me directly if you favour this option.
>>
>> Kind Regards,
>>
>> Adam
>>
>> On Tue, Aug 16, 2016 at 9:02 PM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi James
>>>
>>> I tried the command and it accepted it. The matlab terminal gives the
>>> following error:
>>>
>>> Error using gen_xps_files(362)
>>>
>>> Does it make a diffirence if the simulink models are .mdl or .slx?
>>>
>>> Thank for your help
>>>
>>> Heystek
>>>
>>> On Tue, Aug 16, 2016 at 5:40 PM, James Smith <jsm...@ska.ac.za> wrote:
>>>
>>>> Hello Heystek,
>>>>
>>>> Just to get you an answer quickly, try the following command:
>>>>
>>>> chmod 777 -R /home/heystek/Desktop/tut1
>>>>
>>>> If that command makes an error message then add sudo.
>>>> It's funny that you should have permissions issues there, if this
>>>> doesn't fix things then there might be stranger issues at play.
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Tue, Aug 16, 2016 at 5:36 PM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Hi James and Adam
>>>>>
>>>>> I got it working. The chmod +x startsg command did the trick. I
>>>>> started with the first casper tutorial, but when the system generator
>>>>> compiles it the tutorial breaks. It gives two errors.
>>>>>
>>>>> 1. Design Error  DefaultBlockDiagram  System Generator   Caught
>>>>> standard exception
>>>>> 2. Block ErrorAddSub   System Generator
>>>>>
>>>>> The following error log was also generated:
>>>>>
>>>>> - Version Log
>>>>> --
>>>>> Version Path
>>>>> System Generator/opt/Xilinx/14.7/ISE_DS/ISE/s
>>>>> ysgen
>>>>> Matlab 8.0.0.783 (R2012b)   /usr/local/MATLAB/R2012b
>>>>> ISE /opt/Xilinx/14.7/ISE_DS/ISE
>>>>> 
>>>>> 
>>>>> Summary of Errors:
>>>>> Error 0001: caught standard exception
>>>>>  Block: Unspecified
>>>>> 
>>>>> 
>>>>>
>&

Re: [casper] Help with Xilinx and Simulink

[Heystek Grobler]

Hi James

I tried the command and it accepted it. The matlab terminal gives the
following error:

Error using gen_xps_files(362)

Does it make a diffirence if the simulink models are .mdl or .slx?

Thank for your help

Heystek

On Tue, Aug 16, 2016 at 5:40 PM, James Smith <jsm...@ska.ac.za> wrote:

> Hello Heystek,
>
> Just to get you an answer quickly, try the following command:
>
> chmod 777 -R /home/heystek/Desktop/tut1
>
> If that command makes an error message then add sudo.
> It's funny that you should have permissions issues there, if this doesn't
> fix things then there might be stranger issues at play.
>
> Regards,
> James
>
>
> On Tue, Aug 16, 2016 at 5:36 PM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi James and Adam
>>
>> I got it working. The chmod +x startsg command did the trick. I started
>> with the first casper tutorial, but when the system generator compiles it
>> the tutorial breaks. It gives two errors.
>>
>> 1. Design Error  DefaultBlockDiagram  System Generator   Caught standard
>> exception
>> 2. Block ErrorAddSub   System Generator
>>
>> The following error log was also generated:
>>
>> - Version Log
>> --
>> Version Path
>> System Generator/opt/Xilinx/14.7/ISE_DS/ISE/s
>> ysgen
>> Matlab 8.0.0.783 (R2012b)   /usr/local/MATLAB/R2012b
>> ISE /opt/Xilinx/14.7/ISE_DS/ISE
>> 
>> 
>> Summary of Errors:
>> Error 0001: caught standard exception
>>  Block: Unspecified
>> 
>> 
>>
>> Error 0001:
>>
>> Reported by:
>>   Unspecified
>>
>> Details:
>> standard exception: XNetlistEngine:
>> Exception message could not be parsed:
>> com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first
>> pass text file at
>> /home/heystek/Desktop/tut1/sysgen/sysgen/masterScript423796839757439882
>> 5.pl
>> line 559'
>>
>> 
>> 
>>
>> Do you perhaps have an idea how I can fix it?
>>
>> Thanks for all the help.
>>
>> Have a wonderful day.
>>
>> Heystek
>>
>>
>> On Tue, Aug 16, 2016 at 8:07 AM, James Smith <jsm...@ska.ac.za> wrote:
>>
>>> Hello Heystek,
>>>
>>> This should be a relatively trivial problem to solve:
>>>
>>> cd ~ # This is a shortcut for your home directory
>>> git clone >> SKA-SA one>
>>> cd mlib-devel
>>> ./startsg
>>>
>>> If that doesn't work, then do this:
>>> chmod +x startsg
>>>
>>> Then you should be fine.
>>>
>>> Regards,
>>> James
>>>
>>>
>>> On Mon, Aug 15, 2016 at 7:46 PM, Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>>
>>>> Hi Adam and James
>>>>
>>>> I am working on my personal computer. I will ask a IT guy to help me
>>>> with the privileges and also clone the mlib-devel into the home
>>>> directory and try to run it again.
>>>>
>>>> Thanks for all your help.
>>>>
>>>> Heystek
>>>>
>>>> On Mon, Aug 15, 2016 at 12:58 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>>> wrote:
>>>>
>>>>> Hi Heystek,
>>>>>
>>>>> This issue is not with your script, but your linux permissions. I
>>>>> suggest you follow what James suggests. The fact that you can't run sudo
>>>>> though means that you may need your IT guy to give you sudo rights, but if
>>>>> you are working off the university server that may be an issue - as James
>>>>> says, you shouldn't need this if you install into your home directory.
>>>>>
>>>>> Kind Regards,
>>>>>
>>>>> Adam
>>>>>
>>>>> On Mon, Aug 15, 2016 at 11:27 AM, James Smith <jsm...@ska.ac.za>
>>>>> wrote:
>>>>>
>>>>>> Hello Heystek,
>>>>>>
>>>>>> It would be a bit easier to debug if you posted the terminal session,
>>>>>> along with the commands you ran.
>>>&

Re: [casper] Help with Xilinx and Simulink

[Heystek Grobler]

Hi James and Adam

I got it working. The chmod +x startsg command did the trick. I started
with the first casper tutorial, but when the system generator compiles it
the tutorial breaks. It gives two errors.

1. Design Error  DefaultBlockDiagram  System Generator   Caught standard
exception
2. Block ErrorAddSub   System Generator

The following error log was also generated:

- Version Log
--
Version Path
System Generator/opt/Xilinx/14.7/ISE_DS/ISE/sysgen
Matlab 8.0.0.783 (R2012b)   /usr/local/MATLAB/R2012b
ISE /opt/Xilinx/14.7/ISE_DS/ISE

Summary of Errors:
Error 0001: caught standard exception
 Block: Unspecified


Error 0001:

Reported by:
  Unspecified

Details:
standard exception: XNetlistEngine:
Exception message could not be parsed:
com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first
pass text file at
/home/heystek/Desktop/tut1/sysgen/sysgen/masterScript4237968397574398825.pl
line 559'



Do you perhaps have an idea how I can fix it?

Thanks for all the help.

Have a wonderful day.

Heystek


On Tue, Aug 16, 2016 at 8:07 AM, James Smith <jsm...@ska.ac.za> wrote:

> Hello Heystek,
>
> This should be a relatively trivial problem to solve:
>
> cd ~ # This is a shortcut for your home directory
> git clone  SKA-SA one>
> cd mlib-devel
> ./startsg
>
> If that doesn't work, then do this:
> chmod +x startsg
>
> Then you should be fine.
>
> Regards,
> James
>
>
> On Mon, Aug 15, 2016 at 7:46 PM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi Adam and James
>>
>> I am working on my personal computer. I will ask a IT guy to help me with
>> the privileges and also clone the mlib-devel into the home directory and
>> try to run it again.
>>
>> Thanks for all your help.
>>
>> Heystek
>>
>> On Mon, Aug 15, 2016 at 12:58 PM, Adam Isaacson <aisaac...@ska.ac.za>
>> wrote:
>>
>>> Hi Heystek,
>>>
>>> This issue is not with your script, but your linux permissions. I
>>> suggest you follow what James suggests. The fact that you can't run sudo
>>> though means that you may need your IT guy to give you sudo rights, but if
>>> you are working off the university server that may be an issue - as James
>>> says, you shouldn't need this if you install into your home directory.
>>>
>>> Kind Regards,
>>>
>>> Adam
>>>
>>> On Mon, Aug 15, 2016 at 11:27 AM, James Smith <jsm...@ska.ac.za> wrote:
>>>
>>>> Hello Heystek,
>>>>
>>>> It would be a bit easier to debug if you posted the terminal session,
>>>> along with the commands you ran.
>>>>
>>>> Also, please run "ls -l" in the directory and post that as well. It
>>>> might just be that you need to give the file executable permissions.
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Mon, Aug 15, 2016 at 11:24 AM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Hi Adam
>>>>>
>>>>> I modified the startsg file. When I run it I get the error in the
>>>>> terminal "Permission denied". When I run the startsg file as sudo I get 
>>>>> the
>>>>> error "command not found".
>>>>>
>>>>> I have attached my modified startsg file.
>>>>>
>>>>> Do you perhaps have any ideas of how to solve it?
>>>>>
>>>>> Sorry for the inconvenience
>>>>>
>>>>> Heystek
>>>>>
>>>>> On Mon, Aug 15, 2016 at 11:10 AM, Adam Isaacson <aisaac...@ska.ac.za>
>>>>> wrote:
>>>>>
>>>>>> Hi Heystek,
>>>>>>
>>>>>> Nope, just run the ./startsg and matlab will run the startup.m file
>>>>>> for you when it opens. You should already have both the startsg and
>>>>>> startup.m files, but I gave you mine as I know it works.
>>>>>>
>>>>>> Kind Regards,
>>>>>>
>>>>>> Adam
>>>>>>
>>>>>> On Mon, Aug

Re: [casper] Help with Xilinx and Simulink

[Heystek Grobler]

Hi Adam and James

I am working on my personal computer. I will ask a IT guy to help me with
the privileges and also clone the mlib-devel into the home directory and
try to run it again.

Thanks for all your help.

Heystek

On Mon, Aug 15, 2016 at 12:58 PM, Adam Isaacson <aisaac...@ska.ac.za> wrote:

> Hi Heystek,
>
> This issue is not with your script, but your linux permissions. I suggest
> you follow what James suggests. The fact that you can't run sudo though
> means that you may need your IT guy to give you sudo rights, but if you are
> working off the university server that may be an issue - as James says, you
> shouldn't need this if you install into your home directory.
>
> Kind Regards,
>
> Adam
>
> On Mon, Aug 15, 2016 at 11:27 AM, James Smith <jsm...@ska.ac.za> wrote:
>
>> Hello Heystek,
>>
>> It would be a bit easier to debug if you posted the terminal session,
>> along with the commands you ran.
>>
>> Also, please run "ls -l" in the directory and post that as well. It might
>> just be that you need to give the file executable permissions.
>>
>> Regards,
>> James
>>
>>
>> On Mon, Aug 15, 2016 at 11:24 AM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Hi Adam
>>>
>>> I modified the startsg file. When I run it I get the error in the
>>> terminal "Permission denied". When I run the startsg file as sudo I get the
>>> error "command not found".
>>>
>>> I have attached my modified startsg file.
>>>
>>> Do you perhaps have any ideas of how to solve it?
>>>
>>> Sorry for the inconvenience
>>>
>>> Heystek
>>>
>>> On Mon, Aug 15, 2016 at 11:10 AM, Adam Isaacson <aisaac...@ska.ac.za>
>>> wrote:
>>>
>>>> Hi Heystek,
>>>>
>>>> Nope, just run the ./startsg and matlab will run the startup.m file for
>>>> you when it opens. You should already have both the startsg and startup.m
>>>> files, but I gave you mine as I know it works.
>>>>
>>>> Kind Regards,
>>>>
>>>> Adam
>>>>
>>>> On Mon, Aug 15, 2016 at 10:58 AM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Hi Adam
>>>>>
>>>>> I will try these files! Do I run the startup.m file in matlab as well?
>>>>>
>>>>> Have a nice day
>>>>>
>>>>> Heystek
>>>>>
>>>>> On Mon, Aug 15, 2016 at 9:04 AM, Adam Isaacson <aisaac...@ska.ac.za>
>>>>> wrote:
>>>>>
>>>>>> Hi Heystek,
>>>>>>
>>>>>> No worries. I was in your position just a few months ago :). I have
>>>>>> attached my matlab startup scripts (startsg and startup.m). These must be
>>>>>> placed in the "mlib_devel" directory. You will probably have to change 
>>>>>> the
>>>>>> paths to where your installs are.
>>>>>>
>>>>>> All you need to do is the following:
>>>>>>
>>>>>> 1) Startup matlab R2012b, by running the startsg script. Using the
>>>>>> Ubuntu terminal, in the "mlib_devel" directory type: "./startsg". This
>>>>>> should startup matlab. There should be a message saying that "system
>>>>>> generator currently found installed in matlab default path..."
>>>>>> 2) Type in "simulink" in the command window.
>>>>>> 3) The Simulink Library Browser will open. Browse to where your model
>>>>>> is located and select the *.slx file.
>>>>>> 4) The model should open. Press "Ctrl + D" to check for any errors.
>>>>>> There should be no errors.
>>>>>> 5) Type in "casper_xps" in the command window. The casper XPS window
>>>>>> should pop up. Make sure all boxes are ticked under "ISE Design Flow
>>>>>> Choice:" and then click on "Run XPS". This will run the system generator 
>>>>>> as
>>>>>> part of the process, the Xilinx ISE and generate the relevant bit, fpg
>>>>>> files.
>>>>>>
>>>>>> I have also attached scripts if you just want to run the programs
>>>>>> individually - you will need to edit the path to where your installs are.
>>>

Re: [casper] Help with Xilinx and Simulink

[Heystek Grobler]

Hi Adam

I modified the startsg file. When I run it I get the error in the terminal
"Permission denied". When I run the startsg file as sudo I get the error
"command not found".

I have attached my modified startsg file.

Do you perhaps have any ideas of how to solve it?

Sorry for the inconvenience

Heystek

On Mon, Aug 15, 2016 at 11:10 AM, Adam Isaacson <aisaac...@ska.ac.za> wrote:

> Hi Heystek,
>
> Nope, just run the ./startsg and matlab will run the startup.m file for
> you when it opens. You should already have both the startsg and startup.m
> files, but I gave you mine as I know it works.
>
> Kind Regards,
>
> Adam
>
> On Mon, Aug 15, 2016 at 10:58 AM, Heystek Grobler <
> heystekgrob...@gmail.com> wrote:
>
>> Hi Adam
>>
>> I will try these files! Do I run the startup.m file in matlab as well?
>>
>> Have a nice day
>>
>> Heystek
>>
>> On Mon, Aug 15, 2016 at 9:04 AM, Adam Isaacson <aisaac...@ska.ac.za>
>> wrote:
>>
>>> Hi Heystek,
>>>
>>> No worries. I was in your position just a few months ago :). I have
>>> attached my matlab startup scripts (startsg and startup.m). These must be
>>> placed in the "mlib_devel" directory. You will probably have to change the
>>> paths to where your installs are.
>>>
>>> All you need to do is the following:
>>>
>>> 1) Startup matlab R2012b, by running the startsg script. Using the
>>> Ubuntu terminal, in the "mlib_devel" directory type: "./startsg". This
>>> should startup matlab. There should be a message saying that "system
>>> generator currently found installed in matlab default path..."
>>> 2) Type in "simulink" in the command window.
>>> 3) The Simulink Library Browser will open. Browse to where your model is
>>> located and select the *.slx file.
>>> 4) The model should open. Press "Ctrl + D" to check for any errors.
>>> There should be no errors.
>>> 5) Type in "casper_xps" in the command window. The casper XPS window
>>> should pop up. Make sure all boxes are ticked under "ISE Design Flow
>>> Choice:" and then click on "Run XPS". This will run the system generator as
>>> part of the process, the Xilinx ISE and generate the relevant bit, fpg
>>> files.
>>>
>>> I have also attached scripts if you just want to run the programs
>>> individually - you will need to edit the path to where your installs are.
>>>
>>> Good luck. This should get you going. If the scripts bomb out then it is
>>> likely that your paths are not correct - check that first.
>>>
>>> Kind Regards,
>>>
>>> Adam
>>>
>>> On Sun, Aug 14, 2016 at 8:26 PM, Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>>
>>>> Hi Adam
>>>>
>>>> I got ISE to run. It open up die GUI. How do I start the sysgen with
>>>> MATLAB?
>>>>
>>>> Sorry about the queations.
>>>>
>>>> Thank you for your help
>>>>
>>>> Heystek
>>>>
>>>> On Sun, Aug 14, 2016 at 12:06 PM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Good day Adam
>>>>>
>>>>> I have been working through the documents you send me. I cant open the
>>>>> ISE IDE. As soon as I run the script I get the following error:
>>>>>
>>>>> command not found
>>>>>
>>>>> I am new to Linux and Xilinx.
>>>>>
>>>>> Have a good day
>>>>>
>>>>> Heystek
>>>>>
>>>>> On Mon, Aug 8, 2016 at 3:31 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>>>> wrote:
>>>>>
>>>>>> Hi Heystek,
>>>>>>
>>>>>> You mentioned that you were using the ROACH2 board. This contains a
>>>>>> Virtex 6 device. Vivado only works with Virtex 7 onwards. I would suggest
>>>>>> if you are going to target the ROACH 2 that you use Xilinx ISE 14.7.
>>>>>>
>>>>>> You will need to work with ISE 14.7 and not Vivado.  We have just
>>>>>> begun to use Vivado for our Virtex 7 board e.g  SKARAB. As far as I am
>>>>>> aware, all the the ROACH2 development in SKA-SA has been done using 
>>>>>> Xilinx
>>>>>> ISE 14., as it supports Virtex 6 

Re: [casper] Help with Xilinx and Simulink

[Heystek Grobler]

Hi Adam

I will try these files! Do I run the startup.m file in matlab as well?

Have a nice day

Heystek

On Mon, Aug 15, 2016 at 9:04 AM, Adam Isaacson <aisaac...@ska.ac.za> wrote:

> Hi Heystek,
>
> No worries. I was in your position just a few months ago :). I have
> attached my matlab startup scripts (startsg and startup.m). These must be
> placed in the "mlib_devel" directory. You will probably have to change the
> paths to where your installs are.
>
> All you need to do is the following:
>
> 1) Startup matlab R2012b, by running the startsg script. Using the Ubuntu
> terminal, in the "mlib_devel" directory type: "./startsg". This should
> startup matlab. There should be a message saying that "system generator
> currently found installed in matlab default path..."
> 2) Type in "simulink" in the command window.
> 3) The Simulink Library Browser will open. Browse to where your model is
> located and select the *.slx file.
> 4) The model should open. Press "Ctrl + D" to check for any errors. There
> should be no errors.
> 5) Type in "casper_xps" in the command window. The casper XPS window
> should pop up. Make sure all boxes are ticked under "ISE Design Flow
> Choice:" and then click on "Run XPS". This will run the system generator as
> part of the process, the Xilinx ISE and generate the relevant bit, fpg
> files.
>
> I have also attached scripts if you just want to run the programs
> individually - you will need to edit the path to where your installs are.
>
> Good luck. This should get you going. If the scripts bomb out then it is
> likely that your paths are not correct - check that first.
>
> Kind Regards,
>
> Adam
>
> On Sun, Aug 14, 2016 at 8:26 PM, Heystek Grobler <heystekgrob...@gmail.com
> > wrote:
>
>> Hi Adam
>>
>> I got ISE to run. It open up die GUI. How do I start the sysgen with
>> MATLAB?
>>
>> Sorry about the queations.
>>
>> Thank you for your help
>>
>> Heystek
>>
>> On Sun, Aug 14, 2016 at 12:06 PM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Good day Adam
>>>
>>> I have been working through the documents you send me. I cant open the
>>> ISE IDE. As soon as I run the script I get the following error:
>>>
>>> command not found
>>>
>>> I am new to Linux and Xilinx.
>>>
>>> Have a good day
>>>
>>> Heystek
>>>
>>> On Mon, Aug 8, 2016 at 3:31 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>> wrote:
>>>
>>>> Hi Heystek,
>>>>
>>>> You mentioned that you were using the ROACH2 board. This contains a
>>>> Virtex 6 device. Vivado only works with Virtex 7 onwards. I would suggest
>>>> if you are going to target the ROACH 2 that you use Xilinx ISE 14.7.
>>>>
>>>> You will need to work with ISE 14.7 and not Vivado.  We have just begun
>>>> to use Vivado for our Virtex 7 board e.g  SKARAB. As far as I am aware, all
>>>> the the ROACH2 development in SKA-SA has been done using Xilinx ISE 14., as
>>>> it supports Virtex 6 devices.
>>>>
>>>> Kind Regards,
>>>>
>>>> Adam
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> On Mon, Aug 8, 2016 at 3:13 PM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Good day Adam
>>>>>
>>>>> I am using Ubuntu 14.04 LTS with MATLAB 2012B. Im using the Vivado
>>>>> suite that came with a Zed-Board (Vivado 2013.4).
>>>>>
>>>>> The error I am receiving from MATLAB at startup is:
>>>>> Undefined function 'lAddSysgen' for input arguments of type 'char'.
>>>>> > In matlabrc at 205
>>>>>
>>>>> The errors I get from the system generator is:
>>>>> 1. Design Error - Default block diagram
>>>>> 2. Block Error - AddSub
>>>>>
>>>>> These errors occurs with the first tutorial from CASPER.
>>>>>
>>>>> I looked at the "tweaks to compile" but everything seems ok.
>>>>>
>>>>> I will use the guides you have attached in the previous email.
>>>>>
>>>>> I appreciate your help!!
>>>>>
>>>>> Heystek
>>>>>
>>>>> On Mon, Aug 8, 2016 at 2:30 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>>>> 

Re: [casper] Help with Xilinx and Simulink

[Heystek Grobler]

Hi Adam

I got ISE to run. It open up die GUI. How do I start the sysgen with MATLAB?

Sorry about the queations.

Thank you for your help

Heystek

On Sun, Aug 14, 2016 at 12:06 PM, Heystek Grobler <heystekgrob...@gmail.com>
wrote:

> Good day Adam
>
> I have been working through the documents you send me. I cant open the ISE
> IDE. As soon as I run the script I get the following error:
>
> command not found
>
> I am new to Linux and Xilinx.
>
> Have a good day
>
> Heystek
>
> On Mon, Aug 8, 2016 at 3:31 PM, Adam Isaacson <aisaac...@ska.ac.za> wrote:
>
>> Hi Heystek,
>>
>> You mentioned that you were using the ROACH2 board. This contains a
>> Virtex 6 device. Vivado only works with Virtex 7 onwards. I would suggest
>> if you are going to target the ROACH 2 that you use Xilinx ISE 14.7.
>>
>> You will need to work with ISE 14.7 and not Vivado.  We have just begun
>> to use Vivado for our Virtex 7 board e.g  SKARAB. As far as I am aware, all
>> the the ROACH2 development in SKA-SA has been done using Xilinx ISE 14., as
>> it supports Virtex 6 devices.
>>
>> Kind Regards,
>>
>> Adam
>>
>>
>>
>>
>>
>> On Mon, Aug 8, 2016 at 3:13 PM, Heystek Grobler <heystekgrob...@gmail.com
>> > wrote:
>>
>>> Good day Adam
>>>
>>> I am using Ubuntu 14.04 LTS with MATLAB 2012B. Im using the Vivado suite
>>> that came with a Zed-Board (Vivado 2013.4).
>>>
>>> The error I am receiving from MATLAB at startup is:
>>> Undefined function 'lAddSysgen' for input arguments of type 'char'.
>>> > In matlabrc at 205
>>>
>>> The errors I get from the system generator is:
>>> 1. Design Error - Default block diagram
>>> 2. Block Error - AddSub
>>>
>>> These errors occurs with the first tutorial from CASPER.
>>>
>>> I looked at the "tweaks to compile" but everything seems ok.
>>>
>>> I will use the guides you have attached in the previous email.
>>>
>>> I appreciate your help!!
>>>
>>> Heystek
>>>
>>> On Mon, Aug 8, 2016 at 2:30 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>> wrote:
>>>
>>>> Apologies, that should of been Ubuntu 14.04 LTS and Matlab R2015b...
>>>>
>>>> On Mon, Aug 8, 2016 at 2:28 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>>> wrote:
>>>>
>>>>> Hi Heystek,
>>>>>
>>>>> What OS are you using? I am using Ubuntu 4.04 LTS. What repo are you
>>>>> using? I am using https://github.com/ska-sa/mlib_devel. What version
>>>>> of Matlab and Xilinx are you using? I am using Matlab R2012b and R2105b. I
>>>>> am using Xilinx ISE 14.7. I wrote these How To docs which may or may not
>>>>> come in handy.
>>>>>
>>>>> 1) Matlab 2012b and 2015b Installation:
>>>>> https://drive.google.com/open?id=18BBkoWlSGeuK8BV1UlSnRJIYzl
>>>>> OEWUhqTlF_zAePTj0
>>>>>
>>>>> 2) Xilinx ISE 14.7 Installation:
>>>>> https://drive.google.com/open?id=1o7Wl7wzB7VE1Cckk60B35WerJv
>>>>> l5crXa7Q5xbcoYgE0
>>>>>
>>>>> This should be read in conjunction with the CASPER wiki page -
>>>>> https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_1
>>>>> 4.x_and_Matlab_2012b - did you follow "tweaks to be able to compile"?
>>>>>
>>>>> Kind Regards,
>>>>>
>>>>> Adam
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> On Mon, Aug 8, 2016 at 1:53 PM, Heystek Grobler <
>>>>> heystekgrob...@gmail.com> wrote:
>>>>>
>>>>>> Good Day
>>>>>>
>>>>>> My name is Heystek Grobler. I am an electrical en electronic
>>>>>> engineering science student and for my final year project (skripsie) I'm
>>>>>> developing a wideband spectrometer on a ROACH-2 board.
>>>>>>
>>>>>> Currently I have a problem with Xilinx System Generator and MATLAB.
>>>>>> The Simulink Model runs as a simulation but as soon as I run it in Xilinx
>>>>>> System Generator to compile it for the board it crashes and gives a 
>>>>>> "design
>>>>>> error" as and "block error".
>>>>>>
>>>>>> I was hoping that if possible, that you could provide me with
>>>>>> assistance to get Xilinx and Simulink up and running. So far I followed 
>>>>>> the
>>>>>> CASPER tutorials but got stuck with this problem/
>>>>>>
>>>>>> I hope to hear from you soon.
>>>>>>
>>>>>> Have a wonderful day
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>>
>>>>> Adam Isaacson
>>>>>
>>>>> DBE: FPGA Engineer
>>>>>
>>>>> SKA-SA
>>>>>
>>>>> 3rd Floor
>>>>>
>>>>> The Park
>>>>>
>>>>> Park Road
>>>>>
>>>>> Pinelands
>>>>>
>>>>> 7405
>>>>>
>>>>>
>>>>> Tel: +27215067300 (W)
>>>>>
>>>>> Fax: +27215067375 (W)
>>>>>
>>>>> Cell: +27825639602
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>>
>>>> Adam Isaacson
>>>>
>>>> DBE: FPGA Engineer
>>>>
>>>> SKA-SA
>>>>
>>>> 3rd Floor
>>>>
>>>> The Park
>>>>
>>>> Park Road
>>>>
>>>> Pinelands
>>>>
>>>> 7405
>>>>
>>>>
>>>> Tel: +27215067300 (W)
>>>>
>>>> Fax: +27215067375 (W)
>>>>
>>>> Cell: +27825639602
>>>>
>>>
>>>
>>
>>
>> --
>>
>> Adam Isaacson
>>
>> DBE: FPGA Engineer
>>
>> SKA-SA
>>
>> 3rd Floor
>>
>> The Park
>>
>> Park Road
>>
>> Pinelands
>>
>> 7405
>>
>>
>> Tel: +27215067300 (W)
>>
>> Fax: +27215067375 (W)
>>
>> Cell: +27825639602
>>
>
>

Re: [casper] Help with Xilinx and Simulink

[Heystek Grobler]

Good day Adam

I have been working through the documents you send me. I cant open the ISE
IDE. As soon as I run the script I get the following error:

command not found

I am new to Linux and Xilinx.

Have a good day

Heystek

On Mon, Aug 8, 2016 at 3:31 PM, Adam Isaacson <aisaac...@ska.ac.za> wrote:

> Hi Heystek,
>
> You mentioned that you were using the ROACH2 board. This contains a Virtex
> 6 device. Vivado only works with Virtex 7 onwards. I would suggest if you
> are going to target the ROACH 2 that you use Xilinx ISE 14.7.
>
> You will need to work with ISE 14.7 and not Vivado.  We have just begun to
> use Vivado for our Virtex 7 board e.g  SKARAB. As far as I am aware, all
> the the ROACH2 development in SKA-SA has been done using Xilinx ISE 14., as
> it supports Virtex 6 devices.
>
> Kind Regards,
>
> Adam
>
>
>
>
>
> On Mon, Aug 8, 2016 at 3:13 PM, Heystek Grobler <heystekgrob...@gmail.com>
> wrote:
>
>> Good day Adam
>>
>> I am using Ubuntu 14.04 LTS with MATLAB 2012B. Im using the Vivado suite
>> that came with a Zed-Board (Vivado 2013.4).
>>
>> The error I am receiving from MATLAB at startup is:
>> Undefined function 'lAddSysgen' for input arguments of type 'char'.
>> > In matlabrc at 205
>>
>> The errors I get from the system generator is:
>> 1. Design Error - Default block diagram
>> 2. Block Error - AddSub
>>
>> These errors occurs with the first tutorial from CASPER.
>>
>> I looked at the "tweaks to compile" but everything seems ok.
>>
>> I will use the guides you have attached in the previous email.
>>
>> I appreciate your help!!
>>
>> Heystek
>>
>> On Mon, Aug 8, 2016 at 2:30 PM, Adam Isaacson <aisaac...@ska.ac.za>
>> wrote:
>>
>>> Apologies, that should of been Ubuntu 14.04 LTS and Matlab R2015b...
>>>
>>> On Mon, Aug 8, 2016 at 2:28 PM, Adam Isaacson <aisaac...@ska.ac.za>
>>> wrote:
>>>
>>>> Hi Heystek,
>>>>
>>>> What OS are you using? I am using Ubuntu 4.04 LTS. What repo are you
>>>> using? I am using https://github.com/ska-sa/mlib_devel. What version
>>>> of Matlab and Xilinx are you using? I am using Matlab R2012b and R2105b. I
>>>> am using Xilinx ISE 14.7. I wrote these How To docs which may or may not
>>>> come in handy.
>>>>
>>>> 1) Matlab 2012b and 2015b Installation:
>>>> https://drive.google.com/open?id=18BBkoWlSGeuK8BV1UlSnRJIYzl
>>>> OEWUhqTlF_zAePTj0
>>>>
>>>> 2) Xilinx ISE 14.7 Installation:
>>>> https://drive.google.com/open?id=1o7Wl7wzB7VE1Cckk60B35WerJv
>>>> l5crXa7Q5xbcoYgE0
>>>>
>>>> This should be read in conjunction with the CASPER wiki page -
>>>> https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_1
>>>> 4.x_and_Matlab_2012b - did you follow "tweaks to be able to compile"?
>>>>
>>>> Kind Regards,
>>>>
>>>> Adam
>>>>
>>>>
>>>>
>>>>
>>>> On Mon, Aug 8, 2016 at 1:53 PM, Heystek Grobler <
>>>> heystekgrob...@gmail.com> wrote:
>>>>
>>>>> Good Day
>>>>>
>>>>> My name is Heystek Grobler. I am an electrical en electronic
>>>>> engineering science student and for my final year project (skripsie) I'm
>>>>> developing a wideband spectrometer on a ROACH-2 board.
>>>>>
>>>>> Currently I have a problem with Xilinx System Generator and MATLAB.
>>>>> The Simulink Model runs as a simulation but as soon as I run it in Xilinx
>>>>> System Generator to compile it for the board it crashes and gives a 
>>>>> "design
>>>>> error" as and "block error".
>>>>>
>>>>> I was hoping that if possible, that you could provide me with
>>>>> assistance to get Xilinx and Simulink up and running. So far I followed 
>>>>> the
>>>>> CASPER tutorials but got stuck with this problem/
>>>>>
>>>>> I hope to hear from you soon.
>>>>>
>>>>> Have a wonderful day
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>>
>>>> Adam Isaacson
>>>>
>>>> DBE: FPGA Engineer
>>>>
>>>> SKA-SA
>>>>
>>>> 3rd Floor
>>>>
>>>> The Park
>>>>
>>>> Park Road
>>>>
>>>> Pinelands
>>>>
>>>> 7405
>>>>
>>>>
>>>> Tel: +27215067300 (W)
>>>>
>>>> Fax: +27215067375 (W)
>>>>
>>>> Cell: +27825639602
>>>>
>>>
>>>
>>>
>>> --
>>>
>>> Adam Isaacson
>>>
>>> DBE: FPGA Engineer
>>>
>>> SKA-SA
>>>
>>> 3rd Floor
>>>
>>> The Park
>>>
>>> Park Road
>>>
>>> Pinelands
>>>
>>> 7405
>>>
>>>
>>> Tel: +27215067300 (W)
>>>
>>> Fax: +27215067375 (W)
>>>
>>> Cell: +27825639602
>>>
>>
>>
>
>
> --
>
> Adam Isaacson
>
> DBE: FPGA Engineer
>
> SKA-SA
>
> 3rd Floor
>
> The Park
>
> Park Road
>
> Pinelands
>
> 7405
>
>
> Tel: +27215067300 (W)
>
> Fax: +27215067375 (W)
>
> Cell: +27825639602
>

Re: [casper] Help with Xilinx and Simulink

[Heystek Grobler]

Good day Adam

I am using Ubuntu 14.04 LTS with MATLAB 2012B. Im using the Vivado suite
that came with a Zed-Board (Vivado 2013.4).

The error I am receiving from MATLAB at startup is:
Undefined function 'lAddSysgen' for input arguments of type 'char'.
> In matlabrc at 205

The errors I get from the system generator is:
1. Design Error - Default block diagram
2. Block Error - AddSub

These errors occurs with the first tutorial from CASPER.

I looked at the "tweaks to compile" but everything seems ok.

I will use the guides you have attached in the previous email.

I appreciate your help!!

Heystek

On Mon, Aug 8, 2016 at 2:30 PM, Adam Isaacson <aisaac...@ska.ac.za> wrote:

> Apologies, that should of been Ubuntu 14.04 LTS and Matlab R2015b...
>
> On Mon, Aug 8, 2016 at 2:28 PM, Adam Isaacson <aisaac...@ska.ac.za> wrote:
>
>> Hi Heystek,
>>
>> What OS are you using? I am using Ubuntu 4.04 LTS. What repo are you
>> using? I am using https://github.com/ska-sa/mlib_devel. What version of
>> Matlab and Xilinx are you using? I am using Matlab R2012b and R2105b. I am
>> using Xilinx ISE 14.7. I wrote these How To docs which may or may not come
>> in handy.
>>
>> 1) Matlab 2012b and 2015b Installation:
>> https://drive.google.com/open?id=18BBkoWlSGeuK8BV1UlSnRJIYzl
>> OEWUhqTlF_zAePTj0
>>
>> 2) Xilinx ISE 14.7 Installation:
>> https://drive.google.com/open?id=1o7Wl7wzB7VE1Cckk60B35WerJv
>> l5crXa7Q5xbcoYgE0
>>
>> This should be read in conjunction with the CASPER wiki page -
>> https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_1
>> 4.x_and_Matlab_2012b - did you follow "tweaks to be able to compile"?
>>
>> Kind Regards,
>>
>> Adam
>>
>>
>>
>>
>> On Mon, Aug 8, 2016 at 1:53 PM, Heystek Grobler <heystekgrob...@gmail.com
>> > wrote:
>>
>>> Good Day
>>>
>>> My name is Heystek Grobler. I am an electrical en electronic engineering
>>> science student and for my final year project (skripsie) I'm developing a
>>> wideband spectrometer on a ROACH-2 board.
>>>
>>> Currently I have a problem with Xilinx System Generator and MATLAB. The
>>> Simulink Model runs as a simulation but as soon as I run it in Xilinx
>>> System Generator to compile it for the board it crashes and gives a "design
>>> error" as and "block error".
>>>
>>> I was hoping that if possible, that you could provide me with assistance
>>> to get Xilinx and Simulink up and running. So far I followed the CASPER
>>> tutorials but got stuck with this problem/
>>>
>>> I hope to hear from you soon.
>>>
>>> Have a wonderful day
>>>
>>
>>
>>
>> --
>>
>> Adam Isaacson
>>
>> DBE: FPGA Engineer
>>
>> SKA-SA
>>
>> 3rd Floor
>>
>> The Park
>>
>> Park Road
>>
>> Pinelands
>>
>> 7405
>>
>>
>> Tel: +27215067300 (W)
>>
>> Fax: +27215067375 (W)
>>
>> Cell: +27825639602
>>
>
>
>
> --
>
> Adam Isaacson
>
> DBE: FPGA Engineer
>
> SKA-SA
>
> 3rd Floor
>
> The Park
>
> Park Road
>
> Pinelands
>
> 7405
>
>
> Tel: +27215067300 (W)
>
> Fax: +27215067375 (W)
>
> Cell: +27825639602
>

[casper] Help with Xilinx and Simulink

[Heystek Grobler]

Good Day

My name is Heystek Grobler. I am an electrical en electronic engineering
science student and for my final year project (skripsie) I'm developing a
wideband spectrometer on a ROACH-2 board.

Currently I have a problem with Xilinx System Generator and MATLAB. The
Simulink Model runs as a simulation but as soon as I run it in Xilinx
System Generator to compile it for the board it crashes and gives a "design
error" as and "block error".

I was hoping that if possible, that you could provide me with assistance to
get Xilinx and Simulink up and running. So far I followed the CASPER
tutorials but got stuck with this problem/

I hope to hear from you soon.

Have a wonderful day