Re: gEDA-user: icarus, fork, and recursive tasks
DJ Delorie wrote: task automatic twait Tried that first. Icarus didn't support it. Actually, Icarus Verilog should support automatic tasks, even the 0.9 version that you say you're running. Maybe there is a bug that is tripped by a specific use? -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog 0.9.3 is Available
The developers are pleased to announce the next stable release in the 0.9 series, version 0.9.3. Icarus Verilog is a mostly complete implementation of the hardware description language Verilog, as described in IEEE Std 1364-2005. It also includes a number of user requested extensions. It is freely available (open source), is supported on most operating systems, and will be available as a precompiled package for many of these systems. Icarus Verilog 0.9.3 improves language coverage over the previous stable release, but is primarily a bug fix release. Therefore, we recommend people using the 0.9.2 release upgrade to 0.9.3 as soon as possible. Version 0.9.3 is the recommended version for all new users. More details, including known limitations, deviations from IEEE Std 1364-2005, where to obtain the source code, and links to some of the precompiled packages can be found in the Release Notes located here: http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_0_9_3 -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus verilog Synthesis
What are you trying to do? Are you really trying to synthesize your Verilog design, meaning you are trying to generate a bit stream to load into your FPGA? Or are you trying to compile and simulate your Verilog? Icarus Verilog is mostly a *simulator*, not a synthesizer. There were some synthesis capabilities back in the 0.8 release, but that support has been largely dropped in the 0.9 releases or current devel branch. Verilog code generator? OK, this suggests that you really are trying to *synthesize* (and not simulate) and no, not even the 0.8 release supported synthesis of user defined tasks. Ronald Mathias wrote: Hi, I have written a verilog code that makes use of a user defined task to do some computation. The task takes two parameters as input and one parameter as output. When I try to synthesize it, I get the following error: internal error: NetProc::nex_output not implemented on object type NetUTask internal error: NetProc::nex_output not implemented on object type NetUTask Does this mean that icarus verilog has not yet support for synthesis of user defined tasks? When I try to send the elaborated netlist to the verilog code generator back end, the task definition is missing from the output. Is this a bug or the verilog code generator backend is still not completely implemented ? Regards, Ronald -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Yet another Icarus question
This looks like a bug in Icarus Verilog, I'm afraid. Since all the
values in your expression have explicit sizes, the bit width need
not have carry space tacked on and the width should be 26bits.
In fact, in your example the bus is particularly nasty because it
causes the enablemask bits to be shifted up a bit in the concatenation!
I see that you filed a bug report, that's good. I'll probably bump
its priority a notch because in certain situations it is giving an
incorrect result without warning.
Patrick Doyle wrote:
Can anybody tell me if the following is an Icarus feature or a Verilog
feature. I would expect the two $display statements to show the same
results. For some reason, the first one expands the result to 27 bits
instead of the 26 bits I would have expected. The only difference
(hopefully) between the two lines of code is the addition of a set of
parentheses.
Obviously, I don't really think this is a feature, but is likely to
be a bug. But before I make such hasty accusations, I thought I
would ask for some other opinions (knowing full well that Cary and
Stephen follow this list :-)) I am running:
Icarus Verilog version 0.10.0 (devel) (s20090923-223-g9fbb12d)
If it is agreed that this is a bug, I can file the report.
--wpd
module check_this;
reg [5:0] offset;
reg [9:0] enablemask;
initial begin
enablemask = 10'b0_00110;
offset = 0;
$display(%b, {enablemask, (16'h0 + 8'h80 + offset )});
$display(%b, {enablemask, (16'h0 + (8'h80 + offset))});
end
endmodule // check_this
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Re: gEDA-user: OT Verilog syntax question
I'm a little surprised that Icarus Verilog doesn't already pay attention to the 4 in your %4b. In any case, this should do the trick for you: integer result; ... $display(%b, result[3:0]); ... or failing that, you can try: wire [3:0] tmp = result; ... $display(%b, tmp); Patrick Doyle wrote: Sorry to pester you folks with this, but I'm not sure whom else to ask. I have some verilog test code in which I would like to display an integer value, which is known to be between 0 and 15, as a binary vector, i.e. integer result; $display(%4b, result); of course I get a 64 bit vector displayed. Is there any way to cast my integer variable result as a 4 bit vector just for use in a $display statement? Thanks for any tips you can give me. --wpd ___ geda-user mailing list geda-user-3olirty5fqqavzljymc...@public.gmane.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's the best way to run a test version of iverilog?
Patrick Doyle wrote: If I want to compile and test a particular version of Icarus Verilog without messing my existing working installation, what's the best way to do that? I could configure it with a prefix of some temp directory and add that directory (/bin) to my path. Or I could just run it in the compile directory, confident that it will run the various executables from that directory and not from my path, if I were so confident. Or you can configure with the --suffix=str argument and go ahead and install as normal. For example: ./configure --suffix=-test make make install The result will be the commands iverilog-test, vvp-test, et al. installed along side any other iverilog install. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: What's the best way to run a test version of iverilog?
Patrick Doyle wrote: On Fri, Jul 9, 2010 at 3:20 PM, Stephen Williams steve-tqxsilaruq3qt0dzr+a...@public.gmane.org wrote: Patrick Doyle wrote: If I want to compile and test a particular version of Icarus Verilog without messing my existing working installation, what's the best way to do that? Or I could just run it in the compile directory, confident that it will run the various executables from that directory and not from my path, if I were so confident. Or you can configure with the --suffix=str argument and go ahead and install as normal. For example: Focusing on the word Or, which starts that sentence -- does that imply that I can run ./driver/iverilog and it will pick up the correct subprograms (ivl and ivlpp and whatever else) from the top level source directory? Or does . have to be in my path for it to do that? No, that will not work. In fact the iverilog command does not look in your search path but instead uses complete paths to locate its subprograms. There are command line options to iverilog that tells it where to look instead, but those are awkward and rarely used. I instead recommend either installing with a unique prefix, or install with a unique suffix. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Strange behavior from Icarus Verilog
Eric Brombaugh wrote: I ran this through Modelsim LE and got the following result: # -7.093308,7.093308,7.093308,7 Running it through my copy of Icarus 0.9.2 gives the same answer you got above, so I'm guessing that there's something odd going on with the way Icarus is parsing complex mathematical expressions. File a bug report, if not filed already, and we'll get this worked out. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Structure of Iverilog Windows Version
Ronald Mathias wrote: I have downloaded the windows version of icarus verilog version 0.8.1.7 from [1]http://bleyer.org/icarus/. When I install the executable, I get the executable vlpp.exe ivl.exe. in the lib\ivl directory. I know that vlpp.exe is the preprocessor. But I do not know what is ivl.exe used for. When I run ivl.exe separately, using the -h option the output is similar to vlpp.exe. The iverilog.exe binary is a shallow driver program. It calls other programs to do all the interesting work. In particular, it uses ivlpp to do preprocessing, and ivl to do parsing and elaboration. BTW Pablo has much more recent version of Icarus Verilog compiled for Windows. You might want to take a look. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: iVerilog/GTKWave - Viewing multi-dimensional arrays in GTKWave
Some things have indeed been done. At the very least, you can explicitly list in $dumpvars the array words that you want to dump. The list needs to be explicit to prevent the explosion of traces when you have large memories in your design. Denis Daly wrote: Hi, I'm trying to simulate a Verilog file with many multi-dimensional arrays. e.g. wire [31:0] bus[7:0]; It appears that these signals do not show up in the VCD file and thus can't be viewed in GTKWave. This was confirmed back in 2001 by Steve Williams. http://www.geda.seul.org/mailinglist/geda-dev44/msg00083.html Have there been any changes to iVerilog or GTKWave since 2001 to allow for easy viewing of these multi-dimensional arrays, without needing to instantiate new wires? It appears some tools like Modelsim and Aldec have implemented ways to do this. http://www.edaboard.com/ftopic148791.html Thanks, Denis Daly ___ geda-user mailing list geda-user-3olirty5fqqavzljymc...@public.gmane.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: hydraulic symbols and schematics
Stuart Brorson wrote: Do you foresee any other difficulties? ... aside from simulating a hydraulic circuit with spice or generating a layout. Actually, my first thought was: What kinds of simulations (if any) does one do in hydraulics? Are there any standard simulators? If so, generating a netlist to feed to such a simulator might be an interesting hobby project. I think Verilog-A/MS is a tool that people use for simulating a variety of conservative systems, including hydraulics. Hopefully, Icarus Verilog will start moving forward again on that front some- time soon. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: net= attributes, symbols and schematics
I'm planing a circuit where some chips have a wide variety of different power supply requirements. I'm debating with myself whether I should create symbols that have net= attributes for all the various power types, or if I should attach attributes from outside the symbol, or create pins for all the various power types of the chip, or whatever. In the past I've attached net= attributes to the symbol at the schematic level. That worked well enough, but I wonder if there is a better way, that might be more DRC-friendly. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Issue with Icarus for windows v0.9.1 lxt file generation
Jackson Nichol wrote: I am hoping that someone can help me with a problem that I am having. I have upgraded to Icarus Verilog for windows v0.9.1 from the www.bleyer.org/icarus site. Now when I run a simple test using the following two command line options iverilog -o tb.vvp -s tb tb.v vvp -l tb.log tb.vvp -lxt I am not able to open the resulting waves.lxt file in gtkwave for windows V3.2.1. It looks like the $stop system task is causing vvp to crash on the mingw32 build. Our guy who has a Windows machine to work with has noticed your post and is looking into this problem. Have you filed a bug report in our bugs tracker? If you can do that, it would greatly help us keep track of this issue for you. Thanks, -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus: Synthesize Verilog to Verilog
The Verilog target for Icarus Verilog needs attention. If it were it a usable (even compilable) state, it would be of use to you. Is it sits, getting it it working order would be a great summer project for somebody. Philipp Klaus Krause wrote: Is it possible to use Icarus to simplify Verilog code? I would like to use Berkeley VL2MV/VIS and SIS or ABC, however these tools understand only a very limited subset to verilog. Can Icarus be used to synthesize Verilog into a simplified Verilog? SIS and ABC seem to be a good tools for optimization and can do some technology mapping. The Verilog subset understood by VL2MV (which I use to convert Verilog to BLIF, which is used by SIS and ABC) is a bit limited, e.g. no functions, no multiplication or division. Details can be found in http://www.zemris.fer.hr/labosi/osstr/doc/vl2mv.pdf If Icarus could synthesize Verilog to a simplified Verilog usable by VL2MV, this would lead e.g. to an improved open flow for ASIC design. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Timing in Icarus Verilog not working
What verion of Icarus Verilog are you using? Icarus Verilog doesn't support specify blocks before the 0.9 release. I think with the 0.9 release, it is default turned off, you enable it with -gspecify. Philipp Klaus Krause wrote: I want to model gate delays, but everything happens without delay. Icarus gives no errors messages or warnings. I used gates such as the following: module and2 (A, B, O); input A ; input B ; output O ; and (O, A, B); specify // delay parameters specparam rise = 3.62329:3.62329:3.62329, fall = 4.98817:4.98817:4.98817; // path delays (A * O) = (rise, fall); (B * O) = (rise, fall); endspecify endmodule Philipp ___ geda-user mailing list geda-user-3olirty5fqqavzljymc...@public.gmane.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog Release 0.9.1
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 It's been *years* since we've made a new stable release, but the time has finally come. Icarus Verilog 0.9.1 is the first release of the 0.9 series! Get the source here: ftp://ftp.icarus.com/pub/eda/verilog/v0.9/verilog-0.9.1.tar.gz Since this is a major release, and the first of the 0.9 series, we've decided to put the release notes in the form of a wiki, so get the release notes here: http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_0_9 I'm considering keeping all the 0.9 series release notes on the wiki. Opinions on the matter to iverilog-devel. Packagers, This tarball should be ready to package for various distributions. The build has been tested on a variety of Linux and Windows configurations, so we should be set. I've even made up a source-rpm that should work on all rpm-based systems. - -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.4-svn0 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org iD8DBQFJyP/OrPt1Sc2b3ikRAoxUAJsEzptJVvrc2/cxpcxTwP4vkvNXBwCfdaj1 EmSDrEXBlBP5WemUbQdOtV8= =P+pC -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog: How to exit simulator with non-zero status?
Larry Doolittle wrote: Patrick - On Tue, Mar 03, 2009 at 12:37:17PM -0500, Patrick Doyle wrote: Should I have been able to find that somewhere else? (I am asking in a tone of voice of I would like to know where to look for answers such as these so I don't have to pester the mailing list and not in a whiny tone of voice of where's the docs?) That function/extension was extensively discussed on the mailing list. http://sourceforge.net/mailarchive/forum.php?thread_name=20080522154426.GA3860%40recycle.lbl.govforum_name=iverilog-devel I don't see it documented anywhere. Maybe it should go in extensions.txt? Sounds like this should be documented in the Verilog Portability Notes page, here: http://iverilog.wikia.com/wiki/Verilog_Portability_Notes -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Google SoC : Potential Candidate seeking Info
Aanjhan R wrote: The projects that am interested in are as follows (not in any specific order): 1. Usability improvements for ngspice/Gnucap - Under gaf 2. More interesting integrations with other tools. The new Tcl interface adds a bunch of possibilities. I know one guy is using it to allow remote control from emacs through a bridge server. (Under GTKWAVE - I would like to know if htere are specific interesting integrations as I am not getting the whole picture behind this project proposal) 3. Porting of missing analysis, (noise, pz, disto, hb, etc.) from other free simulators (under gnucap) 4. Add uwire (unresolved net) support - Under Icarus The uwire support is listed as moderate on our Projects page, but is probably too small for a GSoC project. Given the apparent bent towards analog in your selection of candidate projects, might I suggest you take a look at the gnucap Code Generator on the Icarus Verilog projects page? This is something that Al has been wanting, and also puts to use some of the nascent analog support in Icarus Verilog proper. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: order of defparam vs. #(.) parameters in icarus
Matt Ettus wrote: In some Xilinx models, they make instantiations like this: block instance(ports); defparam instance.param=VALUE This normally works ok. The problem is that inside the block, generate statements are being used which are dependent on the value of the parameter. What appears to be happening is that the block is instantiated, and before the defparam line is executed, the decisions are made with the default value of the parameter. The elaboration order of defparams and generate schemes is tricky business and there is a very specific order of events. I put a lot of painful effort into it, but I'm willing to check my work if there is a specific example that generates controversy. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Any discussion about combining schematics and symbols into one file?
Yamazaki R2 wrote: I think i might have brought this up before but I wanted to bring this up again. I know this would be kind of a big change to the way gEDA works, but it would be nice to combine component's schematic, symbol, and maybe pcb view into one file. Or at least the option to do so. On Mac OS X, there is the concept of a bundle. They are actually implemented as directories w/ a suffix. The bundle is treated as a unit. The application (Xcode, for example) is given the path to the bundle, and it finds therein all the files it needs. Normal file browsing tools can be used to browse into the bundle, if desired. Seems to me it would be pretty simple to define a bundle format for schematics as well. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Recommendations for laptop?
Stuart Brorson wrote: My old laptop has gotten old and is starting to act like it should be retired. I use it for hacking (including working on gEDA stuff on those now rare occasions when I get to it), writing, accessing the net, and as the primary computer when I travel. Its replacement (if I go that route) would be heavily used on a sporadic basis. It should be reasonably fast have a large RAM. My main tasks involve using OpenOffice and the various gcc tools (and gEDA related stuff). I'd have to say I'm terribly spoiled by my Macbook Pro. It cost me a pretty penny, but I simply will not buy anything else for myself or my family, period. (For desktops and servers, I still go Linux.) I'm going to sound like a commercial, so forgive me in advance. It is BSD-ish UNIX with most of the familiar Linux/UNIX/etc stuff built in, so you'll feel right at home. There are also package repositories (I use fink) for the traditional open source software packages, so installing the usual cast of Linux-universe tools is pretty debian-like. Even geda! The Pointy-Clicky interface is very nice, simple, clear and artfully elegant. Even sysadmin is elegant, and Just Works. (Apple has pretty much defines It Just Works.) When you start getting into advanced trickery (for example, I have TimeMachine backing up to my LInux server!) your Linux skills will serve you. OpenOffice, FireFox, gimp, and many other familiar monsters have native Mac binaries/installers. QT supports Mac, so many of the KDE tools port trivially to the mac. Development tools for the Mac, including all the SDKs, compilers and documentation, are *free*, and are gcc based. (Xcode includes gcc C/C++/Objective-C.) I just can't say enough good things about my Mackbook Pro. The only glaring issue, is the price. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: First Snapshot of Simbus
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I've successfully simulated a non-trivial PCI device using my new simbus package, so I think it's time to make the first snapshot: ftp://ftp.icarus.com/pub/eda/simbus/snapshots/simbus-20081125.tar.gz ftp://ftp.icarus.com/pub/eda/simbus/snapshots/simbus-20081125.txt I've also started wiki documentation at: http://iverilog.wikia.com/wiki/SIMBUS This snapshot includes the ability to connect pci device and host models written in Verilog and/or C/C++. The models are each in their own processes, and need not even be on the same computer, which allows you to split the simulation of your larger modeled system across a network of computers. I use simbus by writing my host testbench in C/C++ to test my PCI device written in Verilog. The C/C++ binding abstracts PCI commands so that it is fairly easy to write code to interact with the bus. It is also fairly easy to write and test driver code for your device, then port it to an operating system later. The package includes an example PCI memory device that can be a target and even a bus master when properly configured. This device, the pcimem device, is useful in particular as a target for the PCI device you are testing. The source for the pcimem device also demonstrates how you would connect your own PCI device model to simbus. * Future plans/Ideas A system builder tool would be helpful. It's a little clunky to assemble the server configuration file and start all the processed by hand. Support for other bus types. I'm likely to add CameraLink because our boards typically have CameraLink interfaces, but I can see the value of supporting I2C, Wishbone, AMBA, etc. - -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.4-svn0 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org iD8DBQFJLFCqrPt1Sc2b3ikRApCtAKCqIpqx51LZ7vG53eYPPtatUu/5wACgmF1E 33b9rLqlTe2Na1hAq64AonI= =Z/ub -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [iverilog] running the git source of Icarus Verilog
Günter Dannoritzer wrote: Jared Casper wrote: On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer [EMAIL PROTECTED] wrote: So with the latest development snapshot it gave me an assertion, but with the git version a segmentation fault. I saw this behavior as well, so I don't think it is your setup. Something must have changed in git between the snapshot and your bug report that prevented the assertion from firing and it went on to segfault. Note that the bug has been fixed in git now (although for some reason I had to make clean then re make for it to pick up the new parsing code, maybe there is a bug in the Makefiles?) Thanks, after an update both segfaults that I had are gone. Yes, the bugs were reported in the bugs database, and so were dealt with in due course. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [icarus] task automatic causes assertion
I think there is a bug report related to this in the icarus verilog bugs tracker already. automatic tasks are not supported yes, and there is a patch that I recently applied that reports this as a proper error. Günter Dannoritzer wrote: Hi, I tried compiling some Verilog code with a 'task automatic' statement using Icarus Verilog 0.9.devel s20080429 and got the following assertion: iverilog -o auto2.vvp auto.v auto.v:16: syntax error auto.v:3: assert: pform.cc:359: failed assertion lexical_scope == pform_cur_module sh: line 1: 8518 Done/usr/lib64/ivl/ivlpp -L -F/tmp/ivrlg2784ffa93 -f/tmp/ivrlg784ffa93 -p/tmp/ivrli784ffa93 8519 Aborted | /usr/lib64/ivl/ivl -C/tmp/ivrlh784ffa93 -C/usr/lib64/ivl/vvp.conf -- - -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [iverilog] running the git source of Icarus Verilog
Günter Dannoritzer wrote: Hi, I tried to install Icarus Verilog from git and wonder whether I did something wrong, as when things go wrong it crashes with a segmentation fault. I have to say that I have the latest development snapshot installed in parallel in the standard path. That should be fine. So what I did with the git version is that I checked it out to my home folder, did the 'source autoconf.sh' and then configured it with the --prefix set to a path in my home folder. Then just typed make and make install, without any other options. That should be fine, too. The installation went fine and in order to use it I prepended the new bin/ folder to my path. Also added the new lib/ and lib/ivl/ folder to the LD_LIBRARY_PATH in the shell I want to use it. The LD_LIBRARY_PATH bit is not necessary because the compiler and run time use explicit loading and not implicit loading to bring in any loadable modules. I don't think adding the paths to your LD_LIBRARY_PATH will hurt, but that is certainly not helping you. It seems to work with code that runs without error, but when I try other examples that cause problems it ends with a segmentation fault. Did I do something wrong with my installation? How can I check that it works correct? It is just as likely that you found a bug that is segfaulting instead of tripping an assert. That is rare in Icarus Verilog because we're so liberal with assertions, but it does happen from time to time. The best thing to do (as I se you have done) is to submit a bug report. Even assertions deserve a bug report because it should not trip the assert even with completely random input. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: poll: How do you geda?
Kai-Martin Knaak wrote: I am curious, just how heterogeneous the group of geda users and developers is. So I thought, I'd start this little non-random sample poll in the mailing list: * What OS do you run geda applications on? Linux (openSUSE 10.x) Mac OS X (10.5 Intel) * How did you install your copy of geda apps? Prepackaged rpms (opensuse build service, or fink for mac) * Which apps do you use. What is your typical workflow? gschem/pcb for board design, iverilog/gtkwave for fpga design. Usually, the vendor free tools for the actually FPGA synthesis. * Did you (have to) modify portions of geda to suit your needs? gschem/pcb, no. iverilog, yes because I do anyhow;-) * What is the general flavor of your projects? (analog, digital, HF) Digital. * What is the greatest weakness of gEDA? Editing lispy files to configure gschem is just plain wacky. There needs to be a preferences pane like the rest of the world now does it. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process
[EMAIL PROTECTED] wrote: Good day! I'm just a NB in Verilog design, sorry if my question is too stupid :) I've started with free Xilinx ISE, but now i'm trying to do my best to take part in icarus verilog community. I became familiar with IV modelling system, but synth restrain my activity - i get strange error with the simplest module: Are you really intending to *synthesize* with Icarus Verilog? It is most common in the Xilinx flow to use Icarus Verilog for simulation then use xst for synthesis. If that is the case for you, then you do not want to use the -tfpga flag to Icarus Verilog. That will attempt to synthesize, when I think you want to only simulate. Does this link help? http://iverilog.wikia.com/wiki/User_Guide -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Removing default title box
Stuart Brorson wrote: You're a power user. Power users generally know about system-gschemrc, right? Or is that an invalid assumption? That to me is an invalid and totally exasperating assumption, actually. My opinion (for what it's worth) is that even power users want things clear and convenient. Controlling defaults like the title box need to be set up in a Preferences pane when you have a graphical tool. That's the state of the art, and anything else is just plain exasperating. So I have to be a power user to set any of a multitude of gschem optional behaviors? What kind of attitude is that? (I don't know, maybe I'm spoiled by the Mac universe these days, but it strikes me that even power users appreciate clear interfaces.) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: A Verilog AMS program to try
Does anybody have access to a Verilog-AMS tool and can said person attempt to run the attached sample program? It is a very simple program, but it is an attempt to test some of my understanding of very basic principles of Verilog-AMS. I understand that Verilog-AMS tools are very few and very far between, but I would like to work on that problem. This example, though trivial in the extreme, covers a fair amount. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. `include disciplines.vams // Module provides at the output the absolute value of the input voltage module V_absolute(in,out); input in; output out; voltage in,out; analog V(out) + abs(V(in)); endmodule module main; real value; voltage drv, res; analog V(drv) + value; V_absolute U (drv, res); initial begin value = 1.0; #1 if (V(res) != abs(value)) begin $display(FAILED -- value=%g, res=%g, value, V(res)); $finish; end value = -1.0; #1 if (V(res) != abs(value)) begin $display(FAILED -- value=%g, res=%f, value, V(res)); $finish; end $display(PASSED); end endmodule // main ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A Verilog AMS program to try
Dan McMahill wrote: Stephen Williams wrote: Does anybody have access to a Verilog-AMS tool and can said person attempt to run the attached sample program? It is a very simple program, but it is an attempt to test some of my understanding of very basic principles of Verilog-AMS. I understand that Verilog-AMS tools are very few and very far between, but I would like to work on that problem. This example, though trivial in the extreme, covers a fair amount. I think you want to declare your signals that you have listed as 'voltage' as 'electrical'. Thats assuming verilog-ams doesn't do things differently from verilog-a which I'm more familiar with. I think it'll come out the same for me (given that the program is only using the potential nature) but OK change it to electrical. I still wonder if it will run as I expect. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: paging Steve Williams
When that happens, you can send to my gmail account at steveicarus at the usual gmail.com. In fact, at this instant that would be more convenient as I'm furiously hacking away on my mac, where I can read gmail. In the mean time, I'll look at the mail blocker. Spam musta come from comcast. Dan McMahill wrote: Hey Steve. I tried to send you an email and got this: --- Final-recipient: rfc822; [EMAIL PROTECTED] Action: failed Status: 5.1.1 Diagnostic-Code: smtp; 550 5.0.0 Subnet 76.96.62 - Comcast Cable - is a virus nest Last-attempt-Date: Sun, 11 May 2008 00:33:34 + - -Dan ___ geda-user mailing list [EMAIL PROTECTED] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus build problem?
Evan Lavelle wrote: I can't run configure after downloading from git and sourcing autoconf.sh. The output from configure ends with: checking for BZ2_bzdopen in -lbz2... yes checking for BZ2_bzdopen in -lbz2... (cached) yes ../../git2/verilog/vpi/configure: line 4002: syntax error near unexpected token `fmin' ../../git2/verilog/vpi/configure: line 4002: `AC_CHECK_FUNCS_ONCE(fmin fmax)' configure: error: /bin/sh '../../git2/verilog/vpi/configure' failed for vpi Almost surely a problem with your autoconf. I know that autoconf-2.61 on my openSUSE system works. What version are you using? It looks like your autoconf didn't expand the AC_CHECK_FUNCS_ONCE in the vpi/configure.in, so probably your autoconf it too old, or is broken. As an expedient (untested!) hack, you can try changing AC_CHECK_FUNCS_ONCE to AC_CHECK_FUNCS in vpi/configure.in and running the autoconf.sh script again, but better would be to get your autoconf installation up to date. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus build problem?
Evan Lavelle wrote: I was on autoconf 2.59, which comes with Centos 4.4. I couldn't immediately find a 2.61 rpm, so I did the AP_CHECK_FUNCS hack, which let everything compile. Thanks. Maybe I'll just change it to AC_CHECK_FUNCS and leave it at that. The difference is subtle and not really relevant for what I'm doing. Steve - just ran my regressions through the current devel code; you can find the results on bugzilla. If you can fix that lot you should be on about a 96 - 97% pass rate, vs. 97.4 for cver and 100 for ModelSim. I (or my loyal minions) should be able to fix that lot in a hurry. These are all relatively easy, some patches are already pushed. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB drill file question
More often then not, when I had problems like that with Icarus Verilog it turned out to be different handling (by the O/S) of dynamically allocated memory. One or the other (I forget which) will leave random data in malloc'ed memory. If malloc'ed data is not initialized, this can lead to code down-stream getting confused and crashing. Dan McMahill wrote: I was completely unable to reproduce this under linux or netbsd. I also tried things like running electricfence on netbsd and was never able to reproduce the crash there. Under windows though it always happens. The output of gdb was totally useless to me although maybe someone else would have better luck. I think we have 2 likely reasons for the crash. 1) There are some #ifdef WIN32 in a small number of places in the code that has to do with rendering so we do have a slightly different code path within gerbv. [*] 2) Bugs in gtk/gdk for windows. Unfortunately I don't have any more time to put into it and I don't have a sufficient cairo and gdk clue to be very effective anyway. -Dan [*] While looking for #ifdef WIN32, I found some totally inappropriate use of WIN32 and __sparc__ in the csv parser. We should fix that. There is code that looks for the processor (via __sparc__) and then makes assumptions about libc functions and other os, but not processor, dependent things. ___ geda-user mailing list [EMAIL PROTECTED] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
Attila Kinali wrote: On Fri, 25 Apr 2008 14:04:38 -0700 Stephen Williams [EMAIL PROTECTED] wrote: As you know, this year's Icarus Verilog GSoC candidate is working on a VHDL code generator back-end for Icarus Verilog. Hooray! But suddenly the obvious question comes up, How are we going to run these generated files? I'm here looking for suggestions. After rethinking about this. What speaks against adding a VHDL front-end to Icarus? VHDL and Verilog are feature wise very similar and those few differences are not that difficult. As a special benefit it would give us the first OSS simulator with both VHDL and Verilog support. It's not so obvious how that would work, or even whether it would be a good idea. One possibility might be to have e.g. the freehdl compiler generate vvp output, but would that be of use to anyone? Currently, vvp doesn't do any kind of linking, but if it did support linking, and if there is a VHDL compiler that can generate vvp code, then that could lead to a mixed language simulator, but the vvp semantics may not be a good match for VHDL. Anyhow, the parsing of VHDL is actually relatively easy, things get exciting when elaboration happens. That's where most of the VHDL complexity lives. That is to some degree true of Verilog as well, and most of the Icarus Verilog compiler is parse and elaborate. The code generator parts are a small part of the tool itself. I have a copy of 1076-1993 already. I got it when I was deciding which (Verilog or VHDL) to do. It's kinda dusty at the moment. If someone really wants to pursue this from the development perspective, then iverilog-devel at lists.sourceforge.net is where Icarus Verilog development talk happens. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
Attila Kinali wrote: On Sat, 26 Apr 2008 09:22:17 +0200 Hagen SANKOWSKI [EMAIL PROTECTED] wrote: Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs. Uhm... I don't think i have to comment on something uneducated like this, do i? Right, let's please not fall into this pit. I was hoping the mud would dry up and blow away. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Open VHDL Simulators?
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 As you know, this year's Icarus Verilog GSoC candidate is working on a VHDL code generator back-end for Icarus Verilog. Hooray! But suddenly the obvious question comes up, How are we going to run these generated files? I'm here looking for suggestions. Has anybody here used ghdl? freehdl? Relative merits? Which is most active? The most portable? Easiest to use? It just seems like ghdl has the most activity associated with it, but FreeHDL doesn't look completely dead either. So what to choose? - -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.4-svn0 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org iD8DBQFIEkdmrPt1Sc2b3ikRArWWAKC17w7CEuHfC/2zvkMLsGk9m5ntRgCdFmrU apT32uM2brCX9ejtdUii7Zo= =5EMx -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Iverilog synthesis problems
Darren Stevens wrote: Hello All, I've been trying to use a Digilent XLA development board fitted with a Xilinx spartan XCS10 fitted. Since the Xilinx free tools for this chip don't include a synthesis tool I've been trying to use Iverilog, with some success. I'm surprised by that. I thought the webpack releases support spartan chips of various sort via xst. However, iverilog 0.8 should work too. However when trying to make it a little more complicated i.e. adding gate usage by changing the always block to: always @(sw1 or sw2) begin led1 = sw1 | sw2; led2 = sw1 sw2; end causes ngdbuild to fail with the following errors: Checking timing specifications ... Checking expanded design ... WARNING:NgdBuild:486 - Attribute INIT is not allowed on symbol U10 of type LUT2. This attribute will be ignored. ERROR:NgdBuild:604 - logical block 'U10' with type 'LUT2' is unexpanded. Symbol 'LUT2' is not supported in target 'spartan'. WARNING:NgdBuild:486 - Attribute INIT is not allowed on symbol U9 of type LUT2. This attribute will be ignored. ERROR:NgdBuild:604 - logical block 'U9' with type 'LUT2' is unexpanded. Symbol 'LUT2' is not supported in target 'spartan'. The -tfpga code generator for virtex is almost certainly trying to implement your gates with LUT2 devices. It uses an INIT= attribute attached to the LUT2 to specify the logic. That's pretty basic and should work. Looks like ngdbuild is not OK with LUT2 devices on spartan chips? That is weird. What exactly is the software that comes with that devel board? Can you use a recent Webpack instead? -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog: specify path for $readmemh?
Günter Dannoritzer wrote: Hi, I am using the system task $readmemh to init some ROM. Now my question is, can I specify for the simulation with Icarus somewhere the path to the file I am using with $readmemh? I can think of 2 ways: You can use $value$plusargs at run time to get the path you want to use at run time as an extended argument to the vvp command. This won't work for synthesis, though. You can replace your text with a macro, and define that macro in your Makefile (-D) or your iverilog commands file (+define+). This will work with synthesis because you can also pass the correct definition of the path to your synthesizer command line. In rtl/ and tb/ I have my RTL implementation and in tb/ the test benches. In the sim/ folder I have a Makefile that does the compilation and simulation with Icarus Verilog. Now the $readmemh call is in some code in the rtl/ folder. The way I solved the path issue is that I moved the file that is read with the $readmemh call in the sim/ folder. Now the conflict happens with synthesis. In the syn/ folder I have a Makefile that calls synthesis with Xilinx webpack/ISE. It expects the file that is read in with the $readmemh call is in the rtl/ folder. I guess I could copy the ROM file in both locations or specify some macros and have two different $readmemh calls. Anyhow, is there a way to tell Icarus that the ROM file to be read with $readmemh is in another location than the folder the simulator (compiler) is called from? I did not find a command line switch that would apply to that issue. Thanks for the help. Guenter ___ geda-user mailing list [EMAIL PROTECTED] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PC emulator and HDL
Ahmad Sayed wrote: John Griessen wrote: Are you thinking of making your special parallel port driver GPL and eventually part of linux? That would make a great tutorial approach for iverilog... when i reach reasonable point, i'm going to do so, I just want with this discussion first to be sure what i'm going to do with this will be reasonable, and is not pointless Let me see if I can summarize. - You want to simulate a device that attaches to a parallel port, and you want to write that simulation in jHDL or Verilog. - You want to hook that simulation up to a PC emulator so that you can write the *real* device driver for your simulated device, and use that as the test bench. Kool idea. Personally, all my devices are either PCI-* or USB, but linking an emulated parallel port to a simulator would be an easier first project and would demonstrate the idea nicely. The passage of time is going to be an interesting one for you. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PC emulator and HDL
Ahmad Sayed wrote: Dear all, I have an idea of a project, but actually i'm software developer rather than hardware designer, so i need you to help me to figure out the usability of it, my idea in short focus on the circuit designed to work wih computer e.g. computer prephierals. I need to provide a method to simulate these circuits by using PC emulator, to be more specific you got your circuit in HDL, and you have this circuit ready with e.g. parallel port interface, you virtually connect this circuit to PC emulator e.g. bochs or qemu, and write a normal device driver in this guest Operating system. The PC emulator will treat the HDL code as real hardware component. I think this is an excellent idea, but a bigger one then you might realize. In particular, it is usual these days that people are writing their HDL to simulate PCI devices (for various versions of PCI), USB devices, etc. I think the emulators such as qemu do not emulate at that level. For example, for a PCI device, the HDL writer will need the test environment to create PCI cycles (including the clocks) at a *far* lower level then qemu, for example, provides. Emulating at the BUS cycle level would drastically slow down a PC emulator. For USB devices or firewire devices, you might be able make up a hookup point where you can tunnel from the emulator over to a simulation process. Note that for this to work, you are going to need to know a lot about the particular interface you are simulating, because the emulators themselves know nothing. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog vvp32 on 64bit systems
Günter Dannoritzer wrote: Stephen Williams wrote: Question: Does *anybody* use or even see value in the 32bit runtime support that Icarus Verilog includes in 64bit builds? In particular, there is support in the Icarus Verilog source for building simultaneously a vvp (64bit) and a vvp32 (32bit) to support 32bit VPI's transported from 32bit systems. I am not using vvp32, but I am also not a heavy user of the PLI. However, I did try to build openSUSE RPM's from the latest development snapshot and ran into problems related to vvp32, I did not have before. For openSUSE 10.2 x86_64 the build failed with some vvp32 errors. I haven't taken the time yet to look at them closer. Looks like yet another reason to drop the vvp32 support. So far I have a handful of reasons to drop it, and no reasons to keep it. It's starting to look like a rout. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog issues with Teal
Günter Dannoritzer wrote: Hi, I am looking into using Icarus Verilog with Teal/Truss, a C++ based verification framework. With Icarus 0.8.6 all tests but the last, with release of a_wire, are working. It's probably a matter of it not being implemented yet. Looks like a candidate for a bug report. The development snapshot has the same problem, but in addition the shown a_wire(0,0) = reg (reg::Z) assignments don't work. I searched through the bug-tracker and found issue # 1652096 vpi_put_value to net doesn't work Yes, that's true. It's been low priority because no one seemed to be particularly interested in it. Now that you register your interest, it may get more attention. Sounds like that this bug report describes the problem I am seeing with the Teal vreg_test. Is that a bigger issue to solve or is there someone working on its solution already? It's sitting in the database waiting for motivation. I wonder if this is the motivation that is needed?-) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog vvp32 on 64bit systems
Question: Does *anybody* use or even see value in the 32bit runtime support that Icarus Verilog includes in 64bit builds? In particular, there is support in the Icarus Verilog source for building simultaneously a vvp (64bit) and a vvp32 (32bit) to support 32bit VPI's transported from 32bit systems. I personally have never used the vvp32 and I'm starting to run into cases where it is actively getting in the way. I'm considering removing the whole business and forgetting about it, although there may be alternatives. Comments? -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Math functions and PLI
I believe the current Icarus Verilog vvp now has all the infrastructure needed to support real-valued system functions, and there are some PLI2 functions that return real values. So the PLI1 support is just a matter of providing the right translation layer code to make it work. Any volunteers? Larry Doolittle wrote: Matt - On Sun, Dec 16, 2007 at 10:43:38PM -0800, Larry Doolittle wrote: On Sun, Dec 16, 2007 at 06:19:38PM -0800, Matt Ettus wrote: http://www.chris.spear.net/pli/math.htm Unfortunately, when I go to use the result I still get the messages that Matt reports. Steve, what am I missing? [patch to math.c] Using that patch and the appended Makefile, I can get Icarus to at least attempt to load the VPI module. Now the problem is that Icarus (git as of last week) does not support VPI routines of type 3 (userrealfunction). See line 104 of libveriuser/veriusertfs.c , and the results of find verilog-0.9 -type f | xargs grep userrealfunction The error messages from vvp math.vvp are: veriusertfs: $exp, forcing forwref = true veriusertfs: $exp, unsupported type 3 veriusertfs: $log, forcing forwref = true veriusertfs: $log, unsupported type 3 veriusertfs: $log10, forcing forwref = true veriusertfs: $log10, unsupported type 3 veriusertfs: $sin, forcing forwref = true veriusertfs: $sin, unsupported type 3 veriusertfs: $sqrt, forcing forwref = true veriusertfs: $sqrt, unsupported type 3 veriusertfs: $pow, forcing forwref = true veriusertfs: $pow, unsupported type 3 $exp: This task not defined by any modules. I cannot compile it. $log: This task not defined by any modules. I cannot compile it. $log10: This task not defined by any modules. I cannot compile it. $log10: This task not defined by any modules. I cannot compile it. $sin: This task not defined by any modules. I cannot compile it. $sqrt: This task not defined by any modules. I cannot compile it. $pow: This task not defined by any modules. I cannot compile it. math.vvp: Program not runnable, 7 errors. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog Release 0.8.6
Werner Hoch wrote: Ok. I've build it now with the bz2 devel files from the i586 arch. (not yet in the build service) Is there an easy way to test the 32bit verilog files? I'm not an verilog user. Yes, run vvp32 instead of vvp. The reason for the vvp32 is to have a 32bit runtime that can run 32bit VPI plugings that were built for use on 32bit machines. So if you run your Verilog code with vvp32 instead of vvp, then you run the 32bit binary instead. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog Release 0.8.6
Dan McMahill wrote: Stephen Williams wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I've made a new release on the Icarus Verilog v0_8-branch git branch. This is 0.8.6, which includes various safe fixes and updates to the stable release. The source tarball and release notes are here: I haven't been able to build it because lround() seems to be a c99 thing and not in my old math.h and libm. Any chance of having a replacement implementation for systems which don't have lround? The lround function is indeed a c99 thing. All it does is round away from zero. Looks like I'm going to have to add a local implementation, so submit a bug report. I've been contemplating requiring c99 support. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA-dev: iverilog and Xilinx 8.2
Daniel O'Connor wrote: I now get.. [inchoate 9:43] ~/work/fpga/SA iverilog -y . -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/XilinxCoreLib SA_test2.v /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: syntax error /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: error: syntax error in parameter list. /usr/local/Xilinx/verilog/src/unisims/DCM.v:49: syntax error /usr/local/Xilinx/verilog/src/unisims/DCM.v:49: error: syntax error in parameter list. /usr/local/Xilinx/verilog/src/unisims/DCM.v:58: syntax error /usr/local/Xilinx/verilog/src/unisims/DCM.v:58: error: syntax error localparam list. ... Submit a bug report against devel. There is syntax in the DCM that Icarus Verilog is not supporting. I'm surprised because I've done my share of Xilinx FPGA work including DCMs and haven't noticed this until now. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA-dev: iverilog and Xilinx 8.2
Daniel O'Connor wrote: [moved to -user] On Sun, 2 Dec 2007, Stephen Williams wrote: 2) This looks like a problem long since fixed. Version? I originally had 0.8.5 - I tried 0.8.6 but no change. [inchoate 13:55] ~/projects/verilog-0.8.6 iverilog -V Icarus Verilog version 0.8.6 ($Name: $) Copyright 1998-2003 Stephen Williams The it seems likely that the fixes are in the devel branch and not the current stable release. Are you in a position to try the latest snapshots? Another tack is to look at the DCM.v source file. I believe there is a compatibility define that you can use to revert the definition to a simpler implementation that doesn't use as many advanced Verilog features. But if you are up to building and installing software and can use the iverilog devel snapshots you should be OK. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog Release 0.8.6
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I've made a new release on the Icarus Verilog v0_8-branch git branch. This is 0.8.6, which includes various safe fixes and updates to the stable release. The source tarball and release notes are here: ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.txt ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.tar.gz I've also premade an SRPM and a SuSE 10.1 x86_64 RPM. I hope that package managers can package this new release for the various distributions. Special thanks to Cary R. and Alan Feldstein, who put most of the effort into this new release. - -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.2 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org iD8DBQFHS0IurPt1Sc2b3ikRAsdLAKCjThO9ZtV6IS0A1UY0Oce1Fc79lwCgtKhD O3YMqFRVjhGrv6a9IBRAYa4= =Yvu5 -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog: library module search
Alan M. Feldstein wrote: I'm using -y dir-path in the command file to add to the library module search path after using an external tool to locate a module definitions in specific subdirectories of $(DV_ROOT)/libs The problem is that such a subdirectory will often contain Verilog files that each contain multiple module definitions. When there is a module that it needs, it uses the name of the module to generate a likely file name and searches for that file in the library path. For example, if you instantiate my_dev in your verilog, it will look for my_dev.v in the library path, and it will bring in that file. Icarus Verilog expects that file to contain your module, but it may also contain other modules, for example modules that my_dev itself uses. Those extra modules come along as baggage. If you have a single large file that contains your library, then the -y method won't work. Icarus Verilog won't know how to find your library modules. Use the -v method instead for those sorts of libraries. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: list of cell types emitted by icarus synthesis?
IVL_LO_* for logic gates, and IVL_LPM_* for more complex gates. That is of course a proper superset of what might come out of a completed synthesis as a small handful of devices are purely virtual. Adam Megacz wrote: Stephen Williams [EMAIL PROTECTED] writes: An approximation of the answer you are looking for is to look in the ivl_target.h header file. This will show all the different types of gates might be passed to the edif code generator. Of course, not all those gates are necessarily actually generated in a synthesized result, but you'll at least get an idea. Thanks, Stephen. In particular, do you mean the entries in the ivl_logic_t enum? That shouldn't be hard at all, although I don't see adders in there, and Icarus seems to emit adder cells (ADD8), which don't seem to be accounted for in that structure... I was just wondering what other sorts of stuff like this might crop up before I release anything. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: list of cell types emitted by icarus synthesis?
Adam Megacz wrote: Does anybody know where I might find a comprehensive list of the EDIF cell types emitted by icarus' synthesis back-end? I'd like to try to get an idea of where the finish line is in terms of supporting all the cell types it might throw at my stuff. An approximation of the answer you are looking for is to look in the ivl_target.h header file. This will show all the different types of gates might be passed to the edif code generator. Of course, not all those gates are necessarily actually generated in a synthesized result, but you'll at least get an idea. I've got the router in pretty good shape at this point. It's performing nicely when you consider that the placer just picks some random layout and never changes it. http://research.cs.berkeley.edu/project/slipway/ Next step is to do something non-braindead with the placer. - a -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog Release 0.8.5
This is the first time I've used git to spit out a release. I have to say, using the git-gui to scan the commits really puts the summary of changes right there in my face. Writing release notes is tons easier this way. Anyhow, the release tarball is here: ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.5.tar.gz ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.5.txt It's also tagged as v0_8_5 on the v0_8-devel branch within git. And, I've made a srpm and x86_64 binary rpm. Release Notes for Icarus Verilog 0.8.5 This is mostly a bug-fix release for the 0.8 stable branch. * Fix assertions from unary operators with certain operand widths. * Fix incorrect comparison results when in certain cases comparing two signed negative integers. * Latch synthesis has been added to the core synthesizer * Add nand gate support to the edif code generator * Minor compile time errors/warnings * Improved messages from the configure script -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Can't route
DJ Delorie wrote: In theory, via-in-pad lets you bring an extra row out on the top layer. It might mean the difference between 12 and 14 layers. Also, if you avoid masking the bottom side of the via, you suddenly have scope access to every pad of the BGA, which I've found to be amazingly useful in my day-job work. (No I didn't make those boards, and no they were not done with PCB.) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: icarus for-generate support
Matt Ettus wrote: Got another one for you. I am now using the latest git version as of this morning. I get the following assertion when trying to compile the attached files. They are short, but I put them in a tarball. The code shouldn't do anything useful yet, but I believe it is syntactically correct. The code has one for-generate in it which is pretty big, but straightforward. $ iverilog -y . buffer_pool.v ivl: vvp_scope.c:1086: draw_net_in_scope: Assertion `word_count == 1' failed. sh: line 1: 28410 Done/usr/local/lib/ivl/ivlpp -L -F/tmp/ivrlg26a6451cb -f/tmp/ivrlg6a6451cb 28411 Aborted | /usr/local/lib/ivl/ivl -C/tmp/ivrlh6a6451cb -C/usr/local/lib/ivl/vvp.conf -- - It appears that the problem is related to arrays (vs. vectors) of nets. Something in the vvp code generator is balking on an array. It probably handled the generate just fine. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: icarus for-generate support
Your example below is within the skills of Icarus Verilog, but there was a very recent fix for exactly this problem. According to my git logs, it was committed 6/11/2007, which is *after* the very last snapshot. So try the current git. (It should be in the present but stopped CVS as well.) Matt Ettus wrote: I have the following code in a module: genvari; generate for (i=0;i32;i=i+1) begin : gen_srl16 SRL16E srl16e(.Q(dataout[i]), .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]), .CE(write),.CLK(clk),.D(datain[i])); end endgenerate Icarus gives me the following compilation error: shortfifo.v:18: error: Index of dataout needs to be constant in this context. shortfifo.v:18: : Index expression is: i shortfifo.v:18: error: Output port expression must support continuous assignment. shortfifo.v:18: : Port of SRL16E is Q -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Why gperf (was Re: Icarus Verilog going git.)
Dave McGuire wrote: On Jun 16, 2007, at 1:04 AM, Samuel A. Falvo II wrote: Fortunately, gperf is an easy one to deal with. And damn cool to *use*, too...I've used it in a number of projects and it has been fantastic. I did not even know it existed until just now. It's said that GCC uses gperf for its keyword tables and so forth -- I could have sworn they used Flex and Bison? Those don't use gperf as far as I'm aware. Hmmm It does use flex and bison...but reserved word lookups are done with gperf. I don't know why that job isn't done by the lexer; I've not dug into the GCC sources. I am curious about it though. Compilers do generally use flex/bison for the syntax and the general lexical syntax, but normally there are so many keywords that making a flex rule for every keyword would make for a horribly inefficient flex state machine. So what is normally done in this case is to make a flex rule to match identifiers, and then test in a hash table if that identifier is a keyword. If it is, return the lex code for that keyword. Otherwise, return the lex code for an identifier. This generates a more compact lexical analyzer machine. The gperf program is good at making those hash tables. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog going git.
Dave McGuire wrote: On Jun 16, 2007, at 1:19 AM, Samuel A. Falvo II wrote: Well, yeah, it was authored by Linus Torvalds, so that's to be expected. I think it's gotten a _little_ looser since then, but it's still predominantly assuming a Posix-compatible environment. Not OS X or Solaris, at least not early last year. I use git on Mac OS X via a fink package. I would *not* have gone to git if I couldn't use it on my Mac:-) (In fact, the Mac is a PowerBook, so the off-line development support that git offers is one of my motivations for this transition.) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog going git.
Well, I've made my choice and I'm starting the transition over to using git for Icarus Verilog. I've made my personal repository and I've made anonymous access to it at the url: git://icarus.com/~steve-icarus/verilog It this repository you'll be able to *immediately* pull anything that I push into it. This is an improvement over the anonymous CVS access where it only came available overnight after an rsync. I expect to keep the CVS repository around for a while, although I'll not be committing to it, so it will gradually become obsolete and I'll remove it at that time. I'm in the process of changing the documentation to point at the git repository instead of CVS. I'll be following with interest the similar progress with the geda git repository to see what sorts of use styles are worked out while I gain experience with it. (Gaining experience with git is in fact one of my motivations for this switch.) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog going git.
Samuel A. Falvo II wrote: On 6/15/07, Stephen Williams [EMAIL PROTECTED] wrote: Well, I've made my choice and I'm starting the transition over to using git for Icarus Verilog. I've made my personal repository and I've made anonymous access to it at the url: Nice! I've never liked CVS or its ilk because the workflow just doesn't match how I work. I've been a darcs user, and have recently employed git for another project of my own, plus I'm using git at work for my own changes to the corporate products, and I'm very, very happy with it. Well then, I just started into the git instructions in the Installation section of the Icarus Verilog documentation at iverilog.wikia.com. If you have something to add, please do. I'm still flailing a bit:-/ -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [icarus] completely open source fpga toolchain
Adam Megacz wrote: Stephen Williams [EMAIL PROTECTED] writes: The v0.8 releases of Icarus Verilog have decent synthesis. The synthesis is not at all Xilinx specific, but the code generators are. But they needn't be. The FPGA target generates EDIF, so if your intermediate form takes EDIF, the way to move forward is to work on the fpga code generator to generate code for your device. Hey, thanks for the advice. I've got 0.8.4 generating EDIF that parses and flattens it into a netlist my PAR tools can handle. One difficulty, though: the primitive cells that iverilog emits are pretty complex. Is there any way to ask it to break down multipliers and adders into stuff no larger than a LUT4? The reason it generates at that level is that in some cases it is the appropriate level. For example, there *are* multipliers in many modern FPGA primitive sets. It is a whole lot easer for a code generator to break down a multiplier into gates, then to merge up gates into a multiplier. Also, what's the difference between the tgt-edif and tgt-fpga directories? Licensing, mostly. The tgt-edif target source code uses a BSD style license, whereas the tgt-fpga target (which is currently a superset) uses the GPL license. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: speaker source
DJ Delorie wrote: FYI, this is what a prototype mp3 player module looks like: http://www.delorie.com/electronics/alarmclock/mp3-proto.html You can see how small the test speakers are in that photo. We can also see that the desk is heaped up a couple of layers deep. Not unlike my desk, actually:-) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Looking for a gadget
I'm looking for a simple gadget that can connect two RS232 ports to an ethernet. I have a pair of solar grid-tie inverters in an under-the-house utility room. I have ethernet down there but no computers nearby and I would like to hook the RS232 monitoring ports to software or a workstation upstairs. The plan is to put up a simple system monitoring web page. I know I can get some black-box TCP-IP port servers for a few hundred dollars, but I would like to prefer something more open if anyone knows of such a thing. At the price of the commercial stuff, I can almost build my own from scratch (including a PCB!) so I wouldn't be surprised if someone around here had some good options. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: iVerilog's Strengths [bug?]
[EMAIL PROTECTED] wrote: module test; tri blah; assign (pull1, strong0) blah = 0 ? 0 : 1; assign blah = 0; initial $display(Blah should be 0: %d, blah); endmodule Output: Blah should be 0: x Bug. It appears that the muxz device (the ternary operator) is not properly strength-aware. By the way, the strengths are associated with the *driver* and not the value. There is a subtle but important difference, but you are correct that the result of the above should be 0, not x. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: [icarus] completely open source fpga toolchain
This is pretty kool. You've got a big job in front of you! Adam Megacz wrote: So, now that the abits work is published [1] I plan on turning my attention to connecting the dots, so to speak. I've pretty much resigned myself to the fact that I'll have to implement PAR by hand (VPR has licensing issues, and there are far more architecture-portable algorithms now anyways [2]). Moving up the stack one more level: are there any open-source synthesis (ie technology mapping) tools out there? How Xilinx-specific is Icarus' mapper? How much effort is it likely to take to retarget it to Atmel CLB's? My first impulse is to start with that, but I figured I'd check here in case anybody has any hints on a better route to take. The v0.8 releases of Icarus Verilog have decent synthesis. The synthesis is not at all Xilinx specific, but the code generators are. But they needn't be. The FPGA target generates EDIF, so if your intermediate form takes EDIF, the way to move forward is to work on the fpga code generator to generate code for your device. Or you can write a code generator from scratch. Either way is not hard to get started. There is lots of detail, but it should be pretty easy to get the basics working. You want to look at the ivl_target.h header file which defines the loadable target API. CAVEAT: Synthesis in the devel trunk is broken, and has been temporarily abandoned. There was until very recently precious little interest in synthesis, so I didn't let it get in the way of the other tasks I've been working on. Getting synthesis back on line with the devel branch should be a big job. Therefore, for now I recommend using the 0.8 branch for synthesis work, at least for a proof of concept. If there is interest in putting serious work into it, then getting 0.9 synthesis together can be worked out later. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: iverilog: Parameters of Parameters
[EMAIL PROTECTED] wrote: module A (input theInput, output theOutput); parameter delay = 2; // Do something endmodule module B (input theInput, output theOutput); parameter delay = a.delay + 5; A a(theInput, theOutput); // Do something endmodule The idea is that I'd like to know some kind of total accumulative delay during elaboration. [ ... ] Basically, I'm whining for a feature. I've looked at the thread in comp.lang.verilog. The parameter definition circularity problem is nasty, but a carefully contained extension (a la the way Modelsim handles it) seems plausible. This is a good candidate for the Feature Request list, I think. Be warned that bug reports are getting far more of my time then feature requests, but at least if they are in the list they will not get forgotten. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: BUGS: iverilog reals
Looks like there are some bug reports in here. I'm pretty busy with
a big task at the moment so I may not get to these right away, so
that makes filing bug reports even more important.
[EMAIL PROTECTED] wrote:
The following compiles
(and probably shouldn't, unfortunately):
module reals;
wire [63:0] blah = $realtobits(6.35e25);
endmodule
Why shouldn't it compile?
but when run produces:
./a.out:7: syntax error
Obviously a bug.
/ [ 2 ] /
The following compiles:
module reals;
SomeModule someModule
(
$realtobits(3.14+3.15)
);
endmodule
module SomeModule
(
input [63:0] in
);
endmodule
but when run produces:
internal error: 13vvp_arith_sum: recv_real(3.14) not implemented
../../src/vvp/vvp_net.cc:1386: failed assertion `0'
Abort trap
Bug to be reported. Different from above, so make it a different
bug report.
/ [ 3 ] /
There was some problem with realtobits/bitstoreal that
was fixed with the following change:
Index: vvp/vpi_tasks.cc
===
RCS file: /home/demon/anoncvs/verilog/vvp/vpi_tasks.cc,v
retrieving revision 1.35
diff -u -r1.35 vpi_tasks.cc
--- vvp/vpi_tasks.cc12 Apr 2007 04:45:53 - 1.35
+++ vvp/vpi_tasks.cc28 Apr 2007 03:25:34 -
@@ -577,7 +577,7 @@
vpip_cur_task = (struct __vpiSysTaskCall*)ref;
if (vpip_cur_task-defn-info.calltf) {
- assert(vpi_mode_flag == VPI_MODE_NONE);
+ /*assert(vpi_mode_flag == VPI_MODE_NONE);*/
vpi_mode_flag = VPI_MODE_CALLTF;
vpip_cur_task-defn-info.calltf(vpip_cur_task-defn-info.user_data);
vpi_mode_flag = VPI_MODE_NONE;
This fix doesn't address the question whether that assertion
is correct and something else bad might be happening. I don't want
to just remove the assert (which is there for a reason) without
addressing the cause.
--
Steve WilliamsThe woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep.
___
geda-user mailing list
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gEDA-user: Re: Efficient Memories
*sigh* This is bad enough to be called a bug. If you have a small example that triggers this aspect, can you file it as a bug report? You have my permisison to nudge its priority up to 6 because this is actually quite embarrassing:-( [EMAIL PROTECTED] wrote: On 5 Apr 2007, at 11:22:18 AM, Stephen Williams wrote: [EMAIL PROTECTED] wrote: I've made a BMP image format creating module for fun. I maintain a 640x480 24-bits per pixel buffer and then write the data out to a file. At first I used a reg array, but came to find that each element of such a structure is expressed in vvp assembly as distinct reg. This made the vvp assembly 32 MB and unrunnable. Now independent of all the above, I'm surprised that 32Meg makes a vvp file unrunnable. I can believe slow to load, but unless you are very memory constrained, it shouldn't be that much slower then in older snapshots before exploded arrays. Try vvp -v foo.vvp to get a bit more detail what might be going on. Here are the results from (1) Large reg (byte) array:reg [7:0] data [0:sizeImage-1]; // sizeImage = 640*480*3 bytes (2) Large reg vector:reg [sizeImage*8-1:0] data; (1) (a) Running iverilog produces in 11.6 seconds the file a.out, which is 35 MB: Using language generation: IEEE1364-2001+Extensions,specify,xtypes PARSING INPUT LOCATING TOP-LEVEL MODULES test ... done, 0.02 seconds. ELABORATING DESIGN ... done, 0.68 seconds. RUNNING FUNCTORS -F cprop ... -F nodangle ... ... 1 iterations deleted 0 dangling signals and 0 events. (count=0) ... done, 0.01 seconds. CODE GENERATION -t dll ... invoking target_design ... done, 11.6 seconds. STATISTICS lex_string: add_count=44 hit_count=123 (1)(b) Running vvp -v a.out takes 1.22 hours to compile and 15.3 seconds to run (fill all locations and write file). Compiling VVP ... Compile cleanup... ... Linking ... Removing symbol tables ...0 functors 0 table 0 bufif 0 resolv 0 variable ... 901 opcodes (16384 bytes) ... 921630 nets ...0 memories ...5 scopes ... 4404.64 seconds, 0.0/0.0/0.0 KBytes size/rss/shared Running ... ... 15.3602 seconds, 0.0/0.0/0.0 KBytes size/rss/shared Event counts: (event pool = 0) 20007 thread schedule events 0 propagation events 0 assign events 0 other events (2) (a) Running iverilog produces in 0.03 seconds the file a.out, which is 32 KB: Using language generation: IEEE1364-2001+Extensions,specify,xtypes PARSING INPUT LOCATING TOP-LEVEL MODULES test ... done, 0.01 seconds. ELABORATING DESIGN ... done, 0.01 seconds. RUNNING FUNCTORS -F cprop ... -F nodangle ... ... 1 iterations deleted 0 dangling signals and 0 events. (count=0) ... done, 0 seconds. CODE GENERATION -t dll ... invoking target_design ... done, 0.03 seconds. STATISTICS lex_string: add_count=47 hit_count=123 (1)(b) Running vvp -v a.out takes 0.02812 seconds to compile and 11.7084 seconds seconds to run (fill all locations and write file). Compiling VVP ... Compile cleanup... ... Linking ... Removing symbol tables ...0 functors 0 table 0 bufif 0 resolv 0 variable ... 907 opcodes (16384 bytes) ... 33 nets ...0 memories ...5 scopes ... 0.02812 seconds, 0.0/0.0/0.0 KBytes size/rss/shared Running ... ... 11.7084 seconds, 0.0/0.0/0.0 KBytes size/rss/shared Event counts: (event pool = 0) 20007 thread schedule events 0 propagation events 0 assign events 0 other events In other words, exploding the arrays has a significantly bad impact on performance. As comparison: import time time1=time.time(); a = range(1024*768*3*8); print time.time() - time1 gives: 1.99313998222 seconds and: time1 = time.time() for i in xrange(1024*768*3*8): a[i] = 0; print time.time() - time1 gives: 13.961877107620239 seconds. Why not go ahead and compile vvp assembly? What makes python faster? Thanks for your time. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http
gEDA-user: Re: Efficient Memories
[EMAIL PROTECTED] wrote: I've made a BMP image format creating module for fun. I maintain a 640x480 24-bits per pixel buffer and then write the data out to a file. At first I used a reg array, but came to find that each element of such a structure is expressed in vvp assembly as distinct reg. This made the vvp assembly 32 MB and unrunnable. Aw shucks! The reason I started doing that is because individual words are first class objects and there have been bug reports of not being able to continuous assign from memory words. Also, when net arrays are added into the mix, *every* word of a net array should be continuous assigned to. Also, to make matters still more interesting, people have been asking for a way to VCD dump memory words, and exploding arrays is a step (most of the way) towards doing that. Now independent of all the above, I'm surprised that 32Meg makes a vvp file unrunnable. I can believe slow to load, but unless you are very memory constrained, it shouldn't be that much slower then in older snapshots before exploded arrays. Try vvp -v foo.vvp to get a bit more detail what might be going on. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Icarus Verilog PLI example: PLI_INT32 vs static int
Günter Dannoritzer wrote: I modified the vpi_user.c to not needing the other application that comes along with that chapter 2 example and compiled it with: iverilog-vpi pow_vpi.c vpi_user.c iverilog -opow_test.vvp pow_test.v vvp -M. mpow_vpi pow_test.vvp The output I am getting is: $pow PLI application is being used. Segmentation fault I don't know what you are doing wrong, if anything. Please file this as a bug report so that it doesn't get lost, because I will want to deal with this. You have looked at the User Guide in the iverilog.wikia.com wiki documentation, yes? If those examples fail for you, then report that bug with a high priority!-O -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Icarus Verilog PLI example: PLI_INT32 vs static int
Günter Dannoritzer wrote: Hi, I am trying out some examples from the Sutherland PLI book and for the calltf, compiletf, and sizetf routines the book uses PLI_INT32 type as return type. On the Icarus VPI page http://iverilog.wikia.com/wiki/Using_VPI page in hello.c example I see the use of static int for that. When I compile my code with PLI_INT32 I am getting some warnings. What is the reason for that difference? Can I still use PLI_INT32 or will that not work? I am getting a segementation fault now and try to understand whether it has to do with that change? int is PLI_INT32 in your case. The static part is something else altogether and perhaps more germain to your problem. You don't say what's crashing, Stu's example or mine, etc., so we have very little to go on. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog release 0.8.4
This is a new release of the 0.8.4 stable branch of Icarus Verilog. The 0.8.4 release is for those people who are sticking with the stable branch in order to avoid the occasional breakages of the development snapshots, but still want some more important bug fixes. The release is here: ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.4.tar.gz ftp://ftp.icarus.com/pub/eda/verilog/v0.8/verilog-0.8.4.txt Binaries are being put in place as I have them available. There is already a SuSE 10.1 rpm for x86_64, although I how that Werner will pick this up for packaging for all the SuSE systems. Other binaries will come when they are available. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Icarus Verilog with Xilinx simprims...
Evan Lavelle wrote: Günter Dannoritzer wrote: Andy Peters wrote: Does iverilog support SDF backannotation? The SDF has the delay information. Here are some information about that and a link to a previous discussion: http://iverilog.wikia.com/wiki/Graffiti#SDF_support I added a section to your entry covering the reasons for doing timing simulations (same URL). Haven't quite got the hang of this wiki yet. I tried to add it as a second-level heading under 'SDF support', but it's gone in as a main heading... I've changed your section to be one heading level down, assuming that is your desire. Thanks for contributing. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Where are the bugs databases?
I'm fiddling with gschem/gattrib/gsch2pcb/pcb and find that I may want to report bugs. What I need now, though, is a place front and center that has links to the various bug reporting databases. I know that there are a few on sourceforge, but there is nothing written (other then mailing list lore) saying where they are and what their boundaries are. I suggest a page just for links to the bugs databases that includes a 1 line description of what parts of geda goes for each. And on that note, where do I report bugs in gsch2pcb? -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB GTK Layer controls
Are the Layers controls dialog box buttons connected to anything? I try to move one of the existing layers out of the group that it is in to a group of its own (I'm trying to create a ground plane) but it doesn't stick. It's as if the radio button of the group select are not connected to anything. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Nested for loop?
[EMAIL PROTECTED] wrote: Nested for loops don't seem to work in iverilog. it would seem that only the inner loop is updated. Consider the following: module TestMultiplier; reg signed [7:0 ] x, y; wire signed [15:0] z; initial begin $dumpvars; for (x = -128; x 128; x = x + 1) for (y = -128; y 128; y = y + 1) #1 $display(%d * %d = %d, x, y, x*y); end endmodule Here x is always -128 Any help would be appreciated. Look more closely. What is the bit pattern for +128, in 8 bits? What is the bit patters for -128 in 8 bits? And for extra credit, what comes after 127 when counting in 8 bits (signed)? -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Nested for loop?
[EMAIL PROTECTED] wrote: On Sat, Mar 10, 2007 at 10:11:32PM -0500, [EMAIL PROTECTED] wrote: Nested for loops don't seem to work in iverilog. it would seem that only the inner loop is updated. reg signed [7:0 ] x, y; for (x = -128; x 128; x = x + 1) Stop right there. x128 is _always_ true, since the largest value representable in an 8-bit signed is 127. for (y = -128; y 128; y = y + 1) Aw, shucks, you were too explicit! You're ruining a teachable moment. (Or at least a good Doh! I'll never make that mistake again moment. ... having made that same mistake myself a few lots of times.) (Big :-) implied.) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: gEDA-announce: Information about Google Summer of Code and the gEDA Project
Stuart Brorson wrote: * Any open-source organization can have several proposed projects for a Google-supported student to work on. The list of projects is being formulated and will be posted on the gEDA website soon. Once that's done, students are invited to apply to work on one or another of the projects. I've started a section in the Graffiti page of the Icarus Verilog documentation wiki: http://iverilog.wikia.com/wiki/Graffiti and I've sent the initial contents directly to Dan. If any other Icarus Verilog ideas pop up, I can vet them and pass them on. (Hmm... I just thought of another idea...) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: gEDA-announce: Free Dog Meeting on March 8th in Reading, MA!
Stuart Brorson wrote: The meeting will be an open and informal working session. Bring your laptop *and* wireless card! Some items on the agenda are: * Steve's FPGA design flow Is that me you are speaking of? Should I be trying to figure out irc stuffies? -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: google checkout buttons to implement SW development bounties
John Griessen wrote: Creating google checkout buttons is easy -- if you have no shipping costs, (as in FOSS added to project CVS or SVN repository), you could have a series of them for small project chunks, and they get paid as you go... Take for instance the $500 project. divide it into 5 buttons of $100 each and talk with the not well known or trusted customer and arr4ange for them to click and pay two of them after some work delivered, or all systems STOP. I imagine clients creating bounties, not developers. How's this scenario (method 1): Client creates bounty by filling in a form. Bounty gets added to a table with a buy now button assigned to it. Developer claims the bounty by filling in a claim form. Client completes the transaction by buying the bounty. Or like this (method 2): Client creates a bounty by filling in a form. The form includes an offer (in a currency that the commerce system supports). The developer claims a bounty by filling in a form with the claim materials. A claim is posted with the buy button. The client accepts the claim by buying it. Either way, accepting the claim automatically closes it. The second method might be better amenable to multiple clients raising the bounty by filling in a me too form. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: google checkout buttons to implement SW development bounties
al davis wrote: Why all that overhead? The people who made the software have already established a track record. Anyone funding it will do so based on that. We don't need the middleman. They can just send a check. An advantage of electronic payments is that they can be done internationally with little fuss by credit card. I can't see paying just anyone who comes along for enhancements to an active project. Well, that's up to the client to decide, isn't it? The only place I see for broadcast bounties I see is to get something new. I have been considering offering a bounty for someone to make a good quality replacement for autotools. It's even on GNU's list of needs, but they want to do in in guile which is a mistake. It must be written entirely in make and /bin/sh. Client says: I need bug #123456 fixed and I'm willing to pay you $250 to get to the head of the line. Or Client says: I want intrinsic support for imaginary numbers, and I'm willing to pay $475 to get this working. Steve: At a OSEDA dinner you told me that you have had some paying customers, who paid you for Icarus Verilog improvements. You said it was not enough to quit the day job, but it sounded like a lot of money to me, compared to average salaries where I live. What arrangements do you have? How do you negotate? Etc That has dried up and I haven't got new work along those lines. I was basically hired on as a consultant, with a consulting contract and 1099s. It worked for a little while because it was ongoing so didn't require a fresh contract for each little task. But it did bind me to them as I have finite time to enter into multiple time commitments. That sort of thing is really only practical if people can get their company to enter into a contract. It requires negotiations and approvals and legal department's sign off -- Phone calls, paper mails back and forth for signatures, etc. Not at all conducive to impuse buying:-) A boiler-plate contract helps somewhat. The market I'm hoping to tap into is the little one-offs that can be expensed without all these negotiations. There are plenty of $200 tasks that a client can just expense with only the sign-off of a supervisor after the fact. All they need is a receipt. If someone wants to contract me (er um geda developer) for ongoing support, that's a separate path that doesn't need this kind of lubrication. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: google checkout buttons to implement SW development bounties
John Griessen wrote: Stephen Williams wrote: al davis wrote: An advantage of electronic payments is that they can be done internationally with little fuss by credit card. I can't see paying just anyone who comes along for enhancements to an active project. Well, that's up to the client to decide, isn't it? This is the point in the negotiations where splitting a job up into a couple or several smaller chunks might make it go, instead of stalling at the Why should I trust you to deliver/Why should I trust you to pay? stage. Creating the google checkout buttons or invoices to suit negotiations is easy for the seller/developer. Sure. The bounties should be for tasks that are small enough that they naturally fit this criteria. Larger tasks (i.e. tasks that have value in the thousands of dollars) are too big for this sort of system and are more suited to conventional contracts. There are so many scammers who will sound so solid on the phone until you ask them to do something...like send a payment... I would make it part of my terms that a small amount of money moves and a small amount of work gets done, then larger and larger til done... Even if it all is in the expensable petty cash range of money for a bounty setting business. If you are talking about large enough sums that you feel the need to have signed contracts, then your on the path to a more conventional agreement. That said, anonymous clients should not be allowed (log in required) and a history of bad behavior should be somehow made visible. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB question
OK, I'm an idiot. How do I create a local (as in local to my design directory) library of PCB footprints? All the documentation I see suggests that it will automatically search in the packages directory in the current workig directory. No?! -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: PCB question
DJ Delorie wrote: OK, I'm an idiot. How do I create a local (as in local to my design directory) library of PCB footprints? All the documentation I see suggests that it will automatically search in the packages directory in the current workig directory. No?! Note that a local directory *overrides* the global one, as pcb only supports one library at a time (er, one each of m4 and newlib). In my gsch2pcb project file, I do something like this: elements-dir footprints For PCB, you set the lib-newlib variable (settings in gtk, Xdefaults in lesstif). Xdefaults example: Pcb.lib-newlib: /envy/dj/geda/gedasymbols/www/user/dj_delorie/footprints I'm puzzled by this response. Under File-Preferences in the Library tab there is an entry box for Element directories that asks for a colon separated list of directories. Where does this list get stored? Where is this settings file for the gtk hid? -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: PCB question
DJ Delorie wrote:
I'm puzzled by this response. Under File-Preferences in the
Library tab there is an entry box for Element directories that
asks for a colon separated list of directories. Where does this
list get stored?
These are the times I like it when I'm wrong. Both gtk and lesstif
allow colon-separated lists, to provide for multiple newlib
directories. However, it does seem to override the default library.
Where is this settings file for the gtk hid?
IIRC gtk uses the standard gconf stuff.
Note that PCB (any hid) attempts to load settings from
$prefix/share/pcb/settings, ~/.pcb/settings, and ./pcb.settings.
You can use :SaveSettings() to save them:
SaveSettings()
SaveSettings(local)
Saves settings.
If you pass no arguments, the settings are stored in
@code{$HOME/.pcb/settings}. If you pass the word @code{local} they're
saved in @code{./pcb.settings}.
OK, wart alert. I go into preferences and I expect to see the
current search path there. It's blank. OK, so I put in a search
path and do what the text in the box says to do, and it doesn't
work. Nothing changes.
So I do a :SaveSettings() and uncomment the lib-newlib setting
and suddenly the packages library directory works perfectly and
according to all the hints I found about a ./packages directory.
I'll file bug reports for these.
--
Steve WilliamsThe woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep.
___
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gEDA-user: Re: How to maybe get your favorite misfeatures fixed (was: Re: PCB question)
DJ Delorie wrote: Thank you Steve. Not speaking for the PCB developers, but I'm sure they appreciate the bug reports; I know I do. We appreciate all the feedback, with the understanding that we can only get to a tiny percentage of it at a time, as there's only a few of us, and we only do this as a hobby. I'll tell you what. I'll pay you to fix your bugs if you pay me to fix mine. Deal? :-) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Which are the biggest looking gEDA warts?
John Griessen wrote: wart -- Is there a way to set up iverilog with gtkwave? Why is ver 2.0 seemingly dead? and the latest version debian package is 1.3.81? And gtkwave seems to have two home page sites saying they have the most recent version -- one 1.3.24 and the other 3.0.22? GTKWave just works with Icarus Verilog VCD output. In fact, the the VCD dumper for Icarus Verilog was written by Tony. (So are the lxt dumpers, by the way.) I suppose, though, that there should be a heading in the User Guide for using GTKWave. Also, I agree that the status of GTKWave needs to be clarified, documentation written and the web pages made to be mutually consistent. Tony? You there? For my part, the Icarus Verilog documentation could use a chapter in the User Guide that describes in more detail exactly how to work GTKWave with Icarus Verilog. (For those who do not know, documentation for Icarus Verilog lives here: http://iverilog.wikia.com) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Which are the biggest looking gEDA warts?
Dan McMahill wrote: John Griessen wrote: wart -- Is there a way to set up iverilog with gtkwave? Why is ver 2.0 seemingly dead? and the latest version debian package is 1.3.81? And gtkwave seems to have two home page sites saying they have the most recent version -- one 1.3.24 and the other 3.0.22? I have one word for that. ok, maybe 2. mm dinotrace. Seriously, I don't know why I don't hear more about dinotrace here and less about gtkwave. Not to bash gtkwave, but dinotrace has been around for a long time and has worked fairly well everytime I needed a vcd viewer to go with some verilog sims. Because GTKwave is the most talked about? It's also neatly ported and packaged for many platforms. Also, when you get more advanced, there is the LXT2 format that Icarus Verilog and GTKWave support that is a compressed waveform dump format. But instructions for using dinotrace with Icarus Verilog are certainly welcome: http://iverilog.wikia.com I recommend starting with a note in the FAQ page that would point to a dinotrace page. For that matter, GTKWave instructions can stand to be better on the iverilog.wikia.com documentation. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gattrib for symbols?
Can I use gattrib to edit the attributes of a symbol? I have some largish symbols that I'm incrementally working on, and editing attributes such as pintype and pinseq are a burden. (Meaning I see no way to do it within gschem.) But when I try to load a symbol file into gattrib I get a SEGV: (gdb) run microsd-1.sym Starting program: /usr/bin/gattrib microsd-1.sym gEDA/gattrib version 20070216 gEDA/gattrib comes with ABSOLUTELY NO WARRANTY; see COPYING for more details. This is free software, and you are welcome to redistribute it under certain conditions; please see the COPYING file for more details. [Thread debugging using libthread_db enabled] [New Thread 47904931222720 (LWP 14699)] Error while reading shared library symbols: Cannot find new threads: generic error Loading file [/home/u/wing/steve/picturel/mmc/demoboard/microsd-1.sym] Program received signal SIGSEGV, Segmentation fault. [Switching to Thread 47904931222720 (LWP 14699)] 0x2b91bbd5f970 in strcmp () from /lib64/libc.so.6 (gdb) where #0 0x2b91bbd5f970 in strcmp () from /lib64/libc.so.6 #1 0x0042a016 in s_string_list_sort_master_comp_attrib_list () #2 0x0042d053 in gattrib_main () #3 0x2b91bb5c1b61 in scm_boot_guile () from /usr/lib64/libguile.so.12 #4 0x0042cd83 in main () -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Icarus Verilog: Need for --enable-vvp32 in x86_64 ./configure call?
Günter Dannoritzer wrote: Stephen Williams wrote: To add an add-on like a vpi package, you don't need to rebuild the Icarus Verilog package! Just have the myhdl rpm drop the .vpi in the right directory at install time. How does that affect Icarus Verilog packaging? Yes, I undestand that. I was thinking about just adding it to the proper Icarus folder, as part of the myhdl package. What made me think about doing it the other way is that if someone does not install Icarus, that folder does not need to exist. So adding it to Icarus out of the Icarus rpm package everything will work fine when installed in connection with the myhdl package. If somebody decides for some reason to install Icarus from source, the .vpi installation would need to be done by hand. The way you handle that is to create a sub-package that depends on Icarus Verilog. Users can install your main package without requiring Icarus Verilog, but if they install the icarus verilog interface, they will naturally require the Icarus Verilog package. You only need one myhdl.spec file that creates multiple packages. It's a fairly common thing to do. Concerning the packaging, I am not sure how I will do that. I am not that experienced with the creation of spec files yet. I would like to have it that I can put the Icarus source and the vpi source in a folder and the spec file will do the proper steps to compile both and then add the vpi file to the correct folder. That way I can just replace the Icarus source by future releases and run the build process again. My first goal will be to adjust the spec file so that the Icarus source will build correct by itself for the 64 bit platform. Werner Hoch is already using the OPensuse system to build the stable releases of Icarus Verilog (0.8 branch). http://iverilog.wikia.com/wiki/Installation_Guide#SuSE_Linux.2FopenSUSE -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Icarus Verilog: Need for --enable-vvp32 in x86_64 ./configure call?
Günter Dannoritzer wrote:
One change done by Werner Hoch is to add build requires depending on
x86_64. I added another BuildRequires for openSuse 10.2:
-
%ifarch x86_64
BuildRequires: bzip2-32bit, glibc-devel-32bit, glibc-32bit, zlib-devel-32bit
BuildRequires: termcap-32bit, readline-32bit, readline-devel-32bit
%if 0%{?suse_version} == 1020
BuildRequires: gcc-32bit, libstdc++41-devel-32bit
%endif
%endif
--
That are the essential changes to your spec file.
Do you want me to add that as a ticket?
Yes, please. It appears that even though it's suse specific in
places it's harmless on other systems. I may be able to test that, or
arrange for some others (i.e. redhat users) to test it. I'm
running SuSE 10.1.
It would be nice to make sure the verilog.spec is robust as well
as portable.
--
Steve WilliamsThe woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep.
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gEDA-user: Re: licensing (GPL or otherwise) for hardware?
Michael Sokolov wrote: On some rare occasions a paid client will have me develop some piece of software or firmware that would actually have value to humanity. On those rare occasions I always ensure that the work gets open-sourced, if necessary without the client's knowledge. Other times I use my clients' ignorance of the precise terms of the GPL and other free software licenses and make them believe that they have to open-source the kernel module I wrote for example, even if they really don't have to. Remind me, if the opportunity ever arises, that I should not hire you for anything. We are about open source here, and *not* *theft*. For that matter, I'm not so sure I want you use any of my software, open source or not. If you don't feel bound to a contract you might sign with a client, what is there to convince me you'll feel yourself bound to the GPL or any other license I grant you without a signature. You're really willing to knowingly lie to a paying customer? GPL is not disrespect for intellectual property rights. Indeed it relies on intellectual property rights to protect the author(s) from misrepresentation, and, frankly, from theft. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Any Denali users out there?
In the interest of breaking down barriers to further Icarus Verilog use in the real world, I've been looking at adding support for Denali models. This because I've encountered interest from others in the past, and I do keep running into them during day job as well. I contacted Denali and there is some interest in getting Icarus Verilog supported with their stuff, but although there is interest on their side, they want to see some pull from customers first. So are there any friendly Icarus Verilog users out there (Linux preferably) who also want to use Denali models? It would help if you are already a Denali customer, or are interested in becoming one if only they supported Icarus Verilog;-) One existing Denali customer or new sale may be all it takes. I'm hoping to do this work on the devel branch, although since I expect it to be entirely VPI/PLI API work, I could be convinced to back-port to the v0.8 branch as well. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: strange build failure
Ales Hvezda wrote: Hi, [snip] It is possible for some good Samaritan to compile for windows and make available all the updated gEDA packages? I've had the make the Windows port available discussion many many times (both virtually and in person). Just this last week I was talking to another OSS developer (for a totally different program and *significantly* (100x to 1000x) larger user base) and he stated that the moment they released a Windows binary: the whining, the complaining, cluelessness, and general jerk behavior increased *a lot*. Right now I am absolutely thrilled with the quality of the users and discussions on the mailing lists and I have no intention of crashing a good thing. Well, I for one do not use Windows except under duress, but I think the above sentiment is a tad patronizing. Icarus Verilog includes Windows packages, and I have no reason to believe the Windows dolts are any worse then the Linux or MacOS variety. If anything, it's the Solaris folks that are the most cranky;-) -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: strange build failure
DJ Delorie wrote: Or be prepared to pay my consulting rates. Do we need a www.gedaconsulting.org ? I could get behind something like that. Or rather gedaconsulting.com. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: strange build failure
al davis wrote: On Tuesday 05 December 2006 14:23, Stuart Brorson wrote: Or be prepared to pay my consulting rates. To all reading this .. Please take this as an invitation. There are no problems, only unmet business opportunities. One way to increase the priority of any task is to pay for it. Speaking for myself, I would very much welcome financial support for my work. Lots of free software developers would do it full time if it paid the bills. On Tuesday 05 December 2006 14:29, DJ Delorie wrote: Do we need a www.gedaconsulting.org ? Make that www.gedaconsulting.com. Should I grab the name before some spammer gets it? Go for it! Setting up a geda support collective seems like a very kool idea. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Re: Vendor FPGA tools (was Re: Re: Pointer to 3d CAD?)
ldoolitt-dhTElhTvxjT/[EMAIL PROTECTED] wrote: I have added some odd features over the past couple of years. Like the ability to automatically create a .ucf file with timing goals in it based on the comments in the top level Verilog module: module stacker( input clk, // timespec 6.5 ns input gate, ... which is useful for keeping track of timing and cell usage for each of the components of a design. I use attributes for this sort of thing: module stacker( (* PERIOD=6.5ns *) input clk, ... xst understands this, as does Icarus Verilog. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog documentation Wiki
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Icarus Verilog has lacked a User Guide for too long now, so I've started a documentation Wiki here: http://iverilog.wikia.com. I've seeded it with some documentation that I've been hoarding for a while now, and also got the basics of the layout more or less how I would like it, so I'm opening it up to a wider audience. So dig in! - -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.2 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org iD8DBQFFOQfBrPt1Sc2b3ikRAv/QAKCsigKWz3pOoXGCTD8ugRT5lN0UngCg1KEa mNSYQD+XLvfPCfCwva2M4Bs= =yJOU -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Icarus Verilog Release 0.8.3
Hi, I've noted that the Icarus Verilog 0.8 branch gets widespread use, and also the devel branch is still unstable, so I'm still actively maintaining the 0.8 branch; and that leads us to the new release 0.8.3. This is a stable, incremental release of the compiler. It only fixes bugs and some portability issues on the 0.8 branch, so those who are relying on the stability of 0.8 should try 0.8.3. I've uploaded the source code, a soruce RPM, and an x86_64 binary for SuSE 10.1. Other packagers are highly encouraged to get to work on this release. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
