date:20200826

[gem5-dev] Re: Change in gem5/gem5[develop]: mem-cache: Create Compressor namespace

2020-08-26 Thread Nikos Nikoleris via gem5-dev


Do we also need to notify users about this? It might be worth sending an
email about this. In fact an email with a different subject to both
gem5-users and gem5-dev as people might ignore emails for a specific CL.

Nikos

On 25/08/2020 23:17, Daniel Carvalho via gem5-dev wrote:

Was about to send an e-mail with a heads up, but I guess I was too late.

As reported here
(https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-753),
itis not an issue caused by this patch itself. SCons does not trigger
recompilation when a change modifies the cxx_class; therefore,
params/BaseCache.hh is not recompiled and generates the error. To solve
this, one must manually delete this file and force a recompilation.

Regards,
Daniel

Em terça-feira, 25 de agosto de 2020 21:20:56 GMT+2, mike upton via
gem5-dev  escreveu:


This checkin breaks the build.

you can check at:
http://jenkins.gem5.org:8080/job/gem5_develop/136/



On Tue, Aug 25, 2020 at 8:13 AM Daniel Carvalho (Gerrit) via gem5-dev
mailto:gem5-dev@gem5.org>> wrote:

Daniel Carvalho *submitted* this change.

View Change 

Approvals: Nikos Nikoleris: Looks good to me, approved; Looks good
to me, approved kokoro: Regressions pass

mem-cache: Create Compressor namespace

Creation of the Compressor namespace. It encapsulates all the cache
compressors, and other classes used by them.

The following classes have been renamed:
BaseCacheCompressor -> Base
PerfectCompressor - Perfect
RepeatedQwordsCompressor -> RepeatedQwords
ZeroCompressor -> Zero

BaseDictionaryCompressor and DictionaryCompressor were not renamed
because the there is a high probability that users may want to
create a Dictionary class that encompasses the dictionary contained
by these compressors.

To apply this patch one must force recompilation (e.g., by deleting
it) of build//params/BaseCache.hh (and any other files that
were previously using these compressors).

Change-Id: I78cb3b6fb8e3e50a52a04268e0e08dd664d81230
Signed-off-by: Daniel R. Carvalho mailto:oda...@yahoo.com.br>>
Reviewed-on:https://gem5-review.googlesource.com/c/public/gem5/+/33294
Reviewed-by: Nikos Nikoleris mailto:nikos.nikole...@arm.com>>
Maintainer: Nikos Nikoleris mailto:nikos.nikole...@arm.com>>
Tested-by: kokoro mailto:noreply%2bkok...@google.com>>
---
M src/mem/cache/base.hh
M src/mem/cache/compressors/Compressors.py
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base.hh
M src/mem/cache/compressors/base_delta.cc
M src/mem/cache/compressors/base_delta.hh
M src/mem/cache/compressors/base_delta_impl.hh
M src/mem/cache/compressors/base_dictionary_compressor.cc
M src/mem/cache/compressors/cpack.cc
M src/mem/cache/compressors/cpack.hh
M src/mem/cache/compressors/dictionary_compressor.hh
M src/mem/cache/compressors/dictionary_compressor_impl.hh
M src/mem/cache/compressors/fpcd.cc
M src/mem/cache/compressors/fpcd.hh
M src/mem/cache/compressors/multi.cc
M src/mem/cache/compressors/multi.hh
M src/mem/cache/compressors/perfect.cc
M src/mem/cache/compressors/perfect.hh
M src/mem/cache/compressors/repeated_qwords.cc
M src/mem/cache/compressors/repeated_qwords.hh
M src/mem/cache/compressors/zero.cc
M src/mem/cache/compressors/zero.hh
22 files changed, 231 insertions(+), 165 deletions(-)

diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 3efc7c7..d30de3f 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -320,7 +320,7 @@
BaseTags *tags;

/** Compression method being used. */
- BaseCacheCompressor* compressor;
+ Compressor::Base* compressor;

/** Prefetcher */
Prefetcher::Base *prefetcher;
diff --git a/src/mem/cache/compressors/Compressors.py
b/src/mem/cache/compressors/Compressors.py
index eb1952a..46050f6 100644
--- a/src/mem/cache/compressors/Compressors.py
+++ b/src/mem/cache/compressors/Compressors.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2018 Inria
+# Copyright (c) 2018-2020 Inria
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -31,6 +31,7 @@
class BaseCacheCompressor(SimObject):
type = 'BaseCacheCompressor'
abstract = True
+ cxx_class = 'Compressor::Base'
cxx_header = "mem/cache/compressors/base.hh"

block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
@@ -41,6 +42,7 @@
class BaseDictionaryCompressor(BaseCacheCompressor):
type = 'BaseDictionaryCompressor'
abstract = True
+ cxx_class = 'Compressor::BaseDictionaryCompressor'
cxx_header = "mem/cache/compressors/dictionary_compressor.hh"

dictionary_size = Param.Int(Parent.cache_line_size,
@@ -48,49 +50,49 @@

class Base64Delta8(BaseDictionaryCompressor):
type = 'Base6

[gem5-dev] Change in gem5/gem5[develop]: tests: ignore 32-bit arm dual linux boot tests

2020-08-26 Thread Ciro Santilli (Gerrit) via gem5-dev

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33015 )


Change subject: tests: ignore 32-bit arm dual linux boot tests
..

tests: ignore 32-bit arm dual linux boot tests

As mentioned on the JIRA issue, uncacheable requests done after
cacheable requests had been done to the address make the cache writeback
and write trash data to memory.

We believe that the kernel must be doing earlier invalidation by set and
way earlier on to prevent this, but that is not implemented in gem5 yet.

The problem can be worked around by booting in atomic without caches and
checkpointing after init, because uncacheable accesses are only done on
early stages of CPU bringup, which is the more common use case anyways.

The aarch64 Linux kernel developers have stated that set and way
invalidates are not going to be used in aarch64, which further reduces the
importance of implementing this immediatly

JIRA: https://gem5.atlassian.net/browse/GEM5-640
Change-Id: Ieba31e707dcc09693d7a87ed9d51c3d1ffa3abe0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33015
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Giacomo Travaglini 
Maintainer: Jason Lowe-Power 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M tests/gem5/fs/linux/arm/test.py
1 file changed, 7 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index 39cb011..d68e434 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -53,17 +53,13 @@

 arm_fs_long_tests = [
 'realview-simple-atomic',
-'realview-simple-atomic-dual',
 'realview-simple-atomic-checkpoint',
 'realview-simple-timing',
-'realview-simple-timing-dual',
 'realview-switcheroo-atomic',
 'realview-switcheroo-timing',
 'realview-o3',
 'realview-o3-checker',
-'realview-o3-dual',
 'realview-minor',
-'realview-minor-dual',
 'realview-switcheroo-noncaching-timing',
 'realview-switcheroo-o3',
 'realview-switcheroo-full',
@@ -75,9 +71,15 @@
 'realview64-switcheroo-o3',
 'realview64-switcheroo-full',
 'realview-simple-timing-ruby',
-'realview-simple-timing-dual-ruby',
 'realview64-simple-timing-ruby',
 'realview64-simple-timing-dual-ruby',
+
+# https://gem5.atlassian.net/browse/GEM5-640
+#'realview-simple-atomic-dual',
+#'realview-simple-timing-dual',
+#'realview-o3-dual',
+#'realview-minor-dual',
+#'realview-simple-timing-dual-ruby',
 ]

 tarball = 'aarch-system-201901106.tar.bz2'

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieba31e707dcc09693d7a87ed9d51c3d1ffa3abe0
Gerrit-Change-Number: 33015
Gerrit-PatchSet: 4
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix coding style in addressTranslation methods

2020-08-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33434 )



Change subject: arch-arm: Fix coding style in addressTranslation methods
..

arch-arm: Fix coding style in addressTranslation methods

armFault -> arm_fault

Change-Id: I6263b105f8757b34dd15a06b16abe7289073614d
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/isa.cc
1 file changed, 10 insertions(+), 10 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6ef9fe3..0c312d0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2359,15 +2359,15 @@
   "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
   val, par);
 } else {
-ArmFault *armFault = static_cast(fault.get());
-armFault->update(tc);
+ArmFault *arm_fault = static_cast(fault.get());
+arm_fault->update(tc);
 // Set fault bit and FSR
-FSR fsr = armFault->getFsr(tc);
+FSR fsr = arm_fault->getFsr(tc);

 par.f = 1; // F bit
 par.fst = fsr.status; // FST
-par.ptw = (armFault->iss() >> 7) & 0x1; // S1PTW
-par.s = armFault->isStage2() ? 1 : 0; // S
+par.ptw = (arm_fault->iss() >> 7) & 0x1; // S1PTW
+par.s = arm_fault->isStage2() ? 1 : 0; // S

 DPRINTF(MiscRegs,
 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
@@ -2418,15 +2418,15 @@
"MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
val, par);
 } else {
-ArmFault *armFault = static_cast(fault.get());
-armFault->update(tc);
+ArmFault *arm_fault = static_cast(fault.get());
+arm_fault->update(tc);
 // Set fault bit and FSR
-FSR fsr = armFault->getFsr(tc);
+FSR fsr = arm_fault->getFsr(tc);

 par.f = 0x1; // F bit
 par.lpae = fsr.lpae;
-par.ptw = (armFault->iss() >> 7) & 0x1;
-par.s = armFault->isStage2() ? 1 : 0;
+par.ptw = (arm_fault->iss() >> 7) & 0x1;
+par.s = arm_fault->isStage2() ? 1 : 0;

 if (par.lpae) {
 // LPAE - rearange fault status

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6263b105f8757b34dd15a06b16abe7289073614d
Gerrit-Change-Number: 33434
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove deadcode from AArch64 address translation

2020-08-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33355 )


Change subject: arch-arm: Remove deadcode from AArch64 address translation
..

arch-arm: Remove deadcode from AArch64 address translation

There's no need to check for CPSR.WIDTH: if the 64 bit version
of the AT instruction/register is used, it means we are already
in AArch64 execution mode

Change-Id: I1263dcfd04e791eb390199546c177a926c71c6d5
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33355
Reviewed-by: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
1 file changed, 7 insertions(+), 16 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b42fdf1..1244d39 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2364,22 +2364,13 @@
 // Set fault bit and FSR
 FSR fsr = armFault->getFsr(tc);

-CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
-if (cpsr.width) { // AArch32
-newVal = ((fsr >> 9) & 1) << 11;
-// rearrange fault status
-newVal |= ((fsr >>  0) & 0x3f) << 1;
-newVal |= 0x1; // F bit
-newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
-newVal |= armFault->isStage2() ? 0x200 : 0;
-} else { // AArch64
-newVal = 1; // F bit
-newVal |= fsr << 1; // FST
-// TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
-newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
-newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
-newVal |= 1 << 11; // RES1
-}
+newVal = 1; // F bit
+newVal |= fsr << 1; // FST
+// TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
+newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
+newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
+newVal |= 1 << 11; // RES1
+
 DPRINTF(MiscRegs,
 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
 val, fsr, newVal);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1263dcfd04e791eb390199546c177a926c71c6d5
Gerrit-Change-Number: 33355
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Refactor Address Translation (AT) code

2020-08-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33354 )


Change subject: arch-arm: Refactor Address Translation (AT) code
..

arch-arm: Refactor Address Translation (AT) code

* Removed the nested switch
* Replace warn with warn_once as it's polluting the stdout

Change-Id: Iafbf43b68b7c3382cfcd1884305f8393bc63f981
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33354
Reviewed-by: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
2 files changed, 194 insertions(+), 235 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9106b43..b42fdf1 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1992,133 +1992,47 @@
 misc_reg = MISCREG_IFAR_S;
 break;
   case MISCREG_ATS1CPR:
+addressTranslation(TLB::S1CTran, BaseTLB::Read, 0, val);
+return;
   case MISCREG_ATS1CPW:
+addressTranslation(TLB::S1CTran, BaseTLB::Write, 0, val);
+return;
   case MISCREG_ATS1CUR:
+addressTranslation(TLB::S1CTran, BaseTLB::Read,
+TLB::UserMode, val);
+return;
   case MISCREG_ATS1CUW:
+addressTranslation(TLB::S1CTran, BaseTLB::Write,
+TLB::UserMode, val);
+return;
   case MISCREG_ATS12NSOPR:
+if (!haveSecurity)
+panic("Security Extensions required for ATS12NSOPR");
+addressTranslation(TLB::S1S2NsTran, BaseTLB::Read, 0, val);
+return;
   case MISCREG_ATS12NSOPW:
+if (!haveSecurity)
+panic("Security Extensions required for ATS12NSOPW");
+addressTranslation(TLB::S1S2NsTran, BaseTLB::Write, 0, val);
+return;
   case MISCREG_ATS12NSOUR:
+if (!haveSecurity)
+panic("Security Extensions required for ATS12NSOUR");
+addressTranslation(TLB::S1S2NsTran, BaseTLB::Read,
+TLB::UserMode, val);
+return;
   case MISCREG_ATS12NSOUW:
+if (!haveSecurity)
+panic("Security Extensions required for ATS12NSOUW");
+addressTranslation(TLB::S1S2NsTran, BaseTLB::Write,
+TLB::UserMode, val);
+return;
   case MISCREG_ATS1HR:
+addressTranslation(TLB::HypMode, BaseTLB::Read, 0, val);
+return;
   case MISCREG_ATS1HW:
-{
-  Request::Flags flags = 0;
-  BaseTLB::Mode mode = BaseTLB::Read;
-  TLB::ArmTranslationType tranType = TLB::NormalTran;
-  Fault fault;
-  switch(misc_reg) {
-case MISCREG_ATS1CPR:
-  tranType = TLB::S1CTran;
-  mode = BaseTLB::Read;
-  break;
-case MISCREG_ATS1CPW:
-  tranType = TLB::S1CTran;
-  mode = BaseTLB::Write;
-  break;
-case MISCREG_ATS1CUR:
-  flags= TLB::UserMode;
-  tranType = TLB::S1CTran;
-  mode = BaseTLB::Read;
-  break;
-case MISCREG_ATS1CUW:
-  flags= TLB::UserMode;
-  tranType = TLB::S1CTran;
-  mode = BaseTLB::Write;
-  break;
-case MISCREG_ATS12NSOPR:
-  if (!haveSecurity)
-  panic("Security Extensions required for ATS12NSOPR");
-  tranType = TLB::S1S2NsTran;
-  mode = BaseTLB::Read;
-  break;
-case MISCREG_ATS12NSOPW:
-  if (!haveSecurity)
-  panic("Security Extensions required for ATS12NSOPW");
-  tranType = TLB::S1S2NsTran;
-  mode = BaseTLB::Write;
-  break;
-case MISCREG_ATS12NSOUR:
-  if (!haveSecurity)
-  panic("Security Extensions required for ATS12NSOUR");
-  flags= TLB::UserMode;
-  tranType = TLB::S1S2NsTran;
-  mode = BaseTLB::Read;
-  break;
-case MISCREG_ATS12NSOUW:
-  if (!haveSecurity)
-  panic("Security Extensions required for ATS12NSOUW");
-  flags= TLB::UserMode;
-  tranType = TLB::S1S2NsTran;
-  mode = BaseTLB::Write;
-  break;
-case MISCREG_ATS1HR: // only really useful from secure  
mode.

-  tra

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Rewrite addressTranslation to use BitUnions

2020-08-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33356 )


Change subject: arch-arm: Rewrite addressTranslation to use BitUnions
..

arch-arm: Rewrite addressTranslation to use BitUnions

Change-Id: I48877d026213a0dec8b8f96deef59bdbc9a40564
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33356
Reviewed-by: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs_types.hh
2 files changed, 29 insertions(+), 26 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 1244d39..6ef9fe3 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2345,7 +2345,7 @@
 Fault fault = getDTBPtr(tc)->translateFunctional(
 req, tc, mode, tran_type);

-RegVal newVal;
+PAR par = 0;
 if (fault == NoFault) {
 Addr paddr = req->getPaddr();
 uint64_t attr = getDTBPtr(tc)->getAttr();
@@ -2354,28 +2354,26 @@
 attr |= 0x100;
 attr &= ~ uint64_t(0x80);
 }
-newVal = (paddr & mask(47, 12)) | attr;
+par = (paddr & mask(47, 12)) | attr;
 DPRINTF(MiscRegs,
   "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
-  val, newVal);
+  val, par);
 } else {
 ArmFault *armFault = static_cast(fault.get());
 armFault->update(tc);
 // Set fault bit and FSR
 FSR fsr = armFault->getFsr(tc);

-newVal = 1; // F bit
-newVal |= fsr << 1; // FST
-// TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
-newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
-newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
-newVal |= 1 << 11; // RES1
+par.f = 1; // F bit
+par.fst = fsr.status; // FST
+par.ptw = (armFault->iss() >> 7) & 0x1; // S1PTW
+par.s = armFault->isStage2() ? 1 : 0; // S

 DPRINTF(MiscRegs,
 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
-val, fsr, newVal);
+val, fsr, par);
 }
-setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
+setMiscRegNoEffect(MISCREG_PAR_EL1, par);
 return;
 }

@@ -2398,7 +2396,7 @@
 Fault fault = getDTBPtr(tc)->translateFunctional(
 req, tc, mode, tran_type);

-RegVal newVal;
+PAR par = 0;
 if (fault == NoFault) {
 Addr paddr = req->getPaddr();
 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
@@ -2413,36 +2411,36 @@
 max_paddr_bit = 31;
 }

-newVal = (paddr & mask(max_paddr_bit, 12)) |
+par = (paddr & mask(max_paddr_bit, 12)) |
 (getDTBPtr(tc)->getAttr());

 DPRINTF(MiscRegs,
"MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
-   val, newVal);
+   val, par);
 } else {
 ArmFault *armFault = static_cast(fault.get());
 armFault->update(tc);
 // Set fault bit and FSR
 FSR fsr = armFault->getFsr(tc);

-newVal = ((fsr >> 9) & 1) << 11;
-if (newVal) {
+par.f = 0x1; // F bit
+par.lpae = fsr.lpae;
+par.ptw = (armFault->iss() >> 7) & 0x1;
+par.s = armFault->isStage2() ? 1 : 0;
+
+if (par.lpae) {
 // LPAE - rearange fault status
-newVal |= ((fsr >>  0) & 0x3f) << 1;
+par.fst = fsr.status;
 } else {
 // VMSA - rearange fault status
-newVal |= ((fsr >>  0) & 0xf) << 1;
-newVal |= ((fsr >> 10) & 0x1) << 5;
-newVal |= ((fsr >> 12) & 0x1) << 6;
+par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
+par.fs5 = fsr.ext;
 }
-newVal |= 0x1; // F bit
-newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
-newVal |= armFault->isStage2() ? 0x200 : 0;
 DPRINTF(MiscRegs,
"MISCREG: Translated addr 0x%08x fault fsr %#x: PAR:  
0x%08x\n",

-   val, fsr, newVal);
+   val, fsr, par);
 }
-setMiscRegNoEffect(MISCREG_PAR, newVal);
+setMiscRegNoEffect(MISCREG_PAR, par);
 return;
 }

diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index f6bfee4..7196496 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2019 ARM Limited
+ * Copyright (c) 2010-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -650,7 +650,12 @@
 Bitfield<39, 12> pa;
 Bitfield<11> lpae;
 Bitfield<9>  ns;
+Bitfield<9>  s;
 Bitfield<8, 7>   sh;
+Bitfield<8>  ptw;
+Bitfield<6, 1

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Introduce HavePACExt helper

2020-08-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33454 )



Change subject: arch-arm: Introduce HavePACExt helper
..

arch-arm: Introduce HavePACExt helper

This will check for presence of pointer authentication extension.
According to the reference manual, Pointer authentication is
implemented if the value of at least one of

ID_AA64ISAR1_EL1.{APA, API, GPA, GPI}

is not 0b.

Change-Id: I4e98e65758e8edc953794e5b618d2c6c3f6000ae
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
2 files changed, 9 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index ad0a3da..a189c4a 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -315,6 +315,14 @@
 }

 bool
+HavePACExt(ThreadContext *tc)
+{
+AA64ISAR1 id_aa64isar1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
+return id_aa64isar1.api | id_aa64isar1.apa |
+id_aa64isar1.gpi | id_aa64isar1.gpa;
+}
+
+bool
 HaveVirtHostExt(ThreadContext *tc)
 {
 AA64MMFR1 id_aa64mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index f00f606..f17ebc5 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -151,6 +151,7 @@
 return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
 }

+bool HavePACExt(ThreadContext *tc);
 bool HaveVirtHostExt(ThreadContext *tc);
 bool HaveSecureEL2Ext(ThreadContext *tc);
 bool IsSecureEL2Enabled(ThreadContext *tc);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4e98e65758e8edc953794e5b618d2c6c3f6000ae
Gerrit-Change-Number: 33454
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Check if PAC is implemented before executing insts

2020-08-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33455 )



Change subject: arch-arm: Check if PAC is implemented before executing insts
..

arch-arm: Check if PAC is implemented before executing insts

If Armv8.3-PAuth (PAC) extension is not supported, most instrucions
will trigger an Undefined Instruction fault; except for a group of
them living in the HINT space; those should be treated as NOP.

Change-Id: Idec920ed15e0310ec9132a3cb3701cdb7e7cf9d1
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/isa/insts/pauth.isa
1 file changed, 66 insertions(+), 44 deletions(-)



diff --git a/src/arch/arm/isa/insts/pauth.isa  
b/src/arch/arm/isa/insts/pauth.isa

index 4c5b371..4806e6a 100644
--- a/src/arch/arm/isa/insts/pauth.isa
+++ b/src/arch/arm/isa/insts/pauth.isa
@@ -1,5 +1,6 @@
 // -*- mode:c++ -*-

+// Copyright (c) 2020 ARM Limited
 // Copyright (c) 2020 Metempsy Technology Consulting
 // All rights reserved
 //
@@ -41,20 +42,39 @@
 decoder_output = ""
 exec_output = ""

+def pacEnabledCode(hint):
+if hint:
+code = """
+if (!HavePACExt(xc->tcBase())) {
+return NoFault;
+}
+"""
+else:
+code = """
+if (!HavePACExt(xc->tcBase())) {
+return std::make_shared(
+machInst, true);
+}
+"""
+return code

-def buildPauthObject(mnem, templateBase, opcode, optArgs=[]):
+def buildPauthObject(mnem, templateBase, opcode, hint, optArgs=[]):
 global header_output, decoder_output, exec_output
-pac_code = '''//uint64_t val = 0;
-uint64_t res;
-fault = %(op)s(xc->tcBase(), %(op1)s, %(op2)s, &res);
-XDest = res;
-'''
+pac_code = '''
+%(enabled)s
+
+uint64_t res;
+fault = %(op)s(xc->tcBase(), %(op1)s, %(op2)s, &res);
+XDest = res;
+'''
 if templateBase=='DataX2Reg':
-code = pac_code % {"op1": 'Op164',
+code = pac_code % {"enabled": pacEnabledCode(hint),
+   "op1": 'Op164',
"op2": 'Op264',
"op":  opcode }
 else:
-code = pac_code % {"op1": 'XDest',
+code = pac_code % {"enabled": pacEnabledCode(hint),
+   "op1": 'XDest',
"op2": 'Op164',
"op":  opcode }

@@ -63,13 +83,15 @@
 decoder_output += eval(templateBase + "Constructor").subst(iop)
 exec_output += BasicExecute.subst(iop)

-def buildXPauthObject(mnem, optArgs=[]):
+def buildXPauthObject(mnem, hint, optArgs=[]):
 global header_output, decoder_output, exec_output
 templateBase = "XPauthOpRegReg"

-code =  'uint64_t res;\n'\
-'fault = stripPAC(xc->tcBase(), XDest, data, &res);\n'
-code += 'XDest = res;'
+code = pacEnabledCode(hint) + """
+uint64_t res;
+fault = stripPAC(xc->tcBase(), XDest, data, &res);
+XDest = res;
+"""
 regoptype = 'RegOp'

 iop = InstObjParams(mnem, mnem, regoptype, code, optArgs)
@@ -78,42 +100,42 @@
 exec_output += BasicExecute.subst(iop)


-buildPauthObject("Pacda",  "DataX1Reg", 'addPACDA')
-buildPauthObject("Pacdza", "DataX1Reg", 'addPACDA')
-buildPauthObject("Pacdb",  "DataX1Reg", 'addPACDB')
-buildPauthObject("Pacdzb", "DataX1Reg", 'addPACDB')
-buildPauthObject("Pacga",  "DataX2Reg", 'addPACGA')
+buildPauthObject("Pacda",  "DataX1Reg", 'addPACDA', hint=False)
+buildPauthObject("Pacdza", "DataX1Reg", 'addPACDA', hint=False)
+buildPauthObject("Pacdb",  "DataX1Reg", 'addPACDB', hint=False)
+buildPauthObject("Pacdzb", "DataX1Reg", 'addPACDB', hint=False)
+buildPauthObject("Pacga",  "DataX2Reg", 'addPACGA', hint=False)

-buildPauthObject("Pacia", "DataX1Reg", 'addPACIA')
-buildPauthObject("Pacia1716", "DataX1Reg", 'addPACIA')
-buildPauthObject("Paciasp",   "DataX1Reg", 'addPACIA')
-buildPauthObject("Paciaz","DataX1Reg", 'addPACIA')
-buildPauthObject("Paciza","DataX1Reg", 'addPACIA')
+buildPauthObject("Pacia", "DataX1Reg", 'addPACIA', hint=False)
+buildPauthObject("Pacia1716", "DataX1Reg", 'addPACIA', hint=True)
+buildPauthObject("Paciasp",   "DataX1Reg", 'addPACIA', hint=True)
+buildPauthObject("Paciaz","DataX1Reg", 'addPACIA', hint=True)
+buildPauthObject("Paciza","DataX1Reg", 'addPACIA', hint=False)

-buildPauthObject("Pacib", "DataX1Reg", 'addPACIB')
-buildPauthObject("Pacib1716", "DataX1Reg", 'addPACIB')
-buildPauthObject("Pacibsp",   "DataX1Re

[gem5-dev] Change in gem5/gem5[develop]: python: Add DeprecatedParam type

2020-08-26 Thread Jason Lowe-Power (Gerrit) via gem5-dev

Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31954 )


Change subject: python: Add DeprecatedParam type
..

python: Add DeprecatedParam type

There are times when we need to change the name of parameter, but this
breaks the external-facing python API used in configuration files. Using
this "type" for a parameter will warn users that they are using the old
name, but allow for backwards compatibility.

Declaring a SimObject parameter of type `DeprecatedParam` allows the
python configuration files to use the old name transparently. This
leverages some of the SimObject magic to remember the names of
deprecated parameters and the DeprecatedParam object stores the
"translation" from old name to new name.

This has been tested with Ports, "normal" parameters, and SimObject
parameters. It has not been tested with checkpointing as there are no
checkpointing tests in gem5 right now. The testing was manually adding
some deprecated params and checking that config scripts still run
correctly that use the old, deprecated, variables.

Change-Id: I0465a748c08a24278d6b1a9d9ee1bcd67baa5b13
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31954
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/m5/SimObject.py
M src/python/m5/params.py
2 files changed, 105 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 7f12856..7c4c809 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -467,6 +467,12 @@
 cls._params = multidict() # param descriptions
 cls._ports = multidict()  # port descriptions

+# Parameter names that are deprecated. Dict[str, DeprecatedParam]
+# The key is the "old_name" so that when the old_name is used in
+# python config files, we will use the DeprecatedParam object to
+# translate to the new type.
+cls._deprecated_params = multidict()
+
 # class or instance attributes
 cls._values = multidict()   # param values
 cls._hr_values = multidict() # human readable param values
@@ -495,6 +501,7 @@
 cls._base = base
 cls._params.parent = base._params
 cls._ports.parent = base._ports
+cls._deprecated_params.parent = base._deprecated_params
 cls._values.parent = base._values
 cls._hr_values.parent = base._hr_values
 cls._children.parent = base._children
@@ -532,6 +539,15 @@
 elif isinstance(val, Port):
 cls._new_port(key, val)

+# Deprecated variable names
+elif isinstance(val, DeprecatedParam):
+new_name, new_val = cls._get_param_by_value(val.newParam)
+# Note: We don't know the (string) name of this variable  
until

+# here, so now we can finish setting up the dep_param.
+val.oldName = key
+val.newName = new_name
+cls._deprecated_params[key] = val
+
 # init-time-only keywords
 elif key in cls.init_keywords:
 cls._set_keyword(key, val, cls.init_keywords[key])
@@ -604,6 +620,18 @@
 cls._port_refs[attr] = ref
 return ref

+def _get_param_by_value(cls, value):
+"""Given an object, value, return the name and the value from the
+internal list of parameter values. If this value can't be found,  
raise

+a runtime error. This will search both the current object and its
+parents.
+"""
+for k,v in cls._value_dict.items():
+if v == value:
+return k,v
+raise RuntimeError("Cannot find parameter {} in parameter list"
+   .format(value))
+
 # Set attribute (called on foo.attr = value when foo is an
 # instance of class cls).
 def __setattr__(cls, attr, value):
@@ -1255,6 +1283,11 @@
 return ref

 def __getattr__(self, attr):
+if attr in self._deprecated_params:
+dep_param = self._deprecated_params[attr]
+dep_param.printWarning(self._name, self.__class__.__name__)
+return getattr(self, self._deprecated_params[attr].newName)
+
 if attr in self._ports:
 return self._get_port_ref(attr)

@@ -1287,6 +1320,11 @@
 object.__setattr__(self, attr, value)
 return

+if attr in self._deprecated_params:
+dep_param = self._deprecated_params[attr]
+dep_param.printWarning(self._name, self.__class__.__name__)
+return setattr(self, self._deprecated_params[attr].newName,  
value)

+
 if attr in self._ports:

[gem5-dev] Force scons to use local libraries over system libraries

2020-08-26 Thread Hsuan Hsu via gem5-dev

Hi, is it possible to change the library path search order, so that scons 
searches a specific path before the system path?

We need to link our gem5 with libz 1.2.9, but there is already a 
/usr/lib/libz.so whose version is 1.2.8 incompatible with our work. Also, we 
don't have permission to update the system libraries.

We have already tried adding the following statement to gem5/SConstruct:

main.Prepend(LIBPATH=['PATH/TO/OUR/LIBZ'])

but that path is still searched after the system path:

scons build/ARM/gem5.opt --verbose
...
g++  -o  build/ARM/marshal  ...  -L/usr/lib  ...  -L/PATH/TO/OUR/LIBZ  
...  -lz  ...

and thus results in a link error.

Thanks,
Hsuan
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[gem5-dev] Re: switching to python 3 for config scripts?

2020-08-26 Thread Jason Lowe-Power via gem5-dev

Hey Gabe,

We've had many discussions on this in the past couple of months. The
underlying problem is that each distro has decided to do something
different with /usr/bin/python. Some of them allow it to point to python3
others force it to point to python2. This screws up Scons, our scripts, and
lots of other things.

The only solution, as far as we can tell, is to drop support for python2
and switch everything to use python3. I think we should do this after
gem5-20.1 is released.

I've found that if you install python3 and create a symlink from
/usr/bin/python to /usr/bin/python3 (apt install python-is-python3 on
Ubuntu, but not possible on OpenSUSE except manually, not sure about arch)
thing work OK.

Cheers,
Jason

On Tue, Aug 25, 2020 at 11:42 PM Gabe Black via gem5-dev 
wrote:

> Hi folks. We've been moving to python 3 for many things, but for gem5's
> built in python, aka config scripts, we still default to python 2 instead
> of python 3. When do we plan to change that? I ask because I ran into a
> problem where the python 2.7 pyconfig.h doesn't compile correctly on my
> desktop, and since 2.7 is EOL I don't think my distribution (Arch Linux) is
> going to fix it.
>
> I can get it to work by manually saying I want to use python3-config, but
> would it make sense for that to be the default?
>
> Gabe
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[gem5-dev] Change in gem5/gem5[develop]: misc: Updated port classes & refs to remove slaveBind()/UnBind()

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32309 )


Change subject: misc: Updated port classes & refs to remove  
slaveBind()/UnBind()

..

misc: Updated port classes & refs to remove slaveBind()/UnBind()

Change-Id: I9106397b8816d8148dd916510bbcf65ed499d303
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32309
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/mem/port.cc
M src/mem/port.hh
M src/mem/token_port.cc
3 files changed, 8 insertions(+), 8 deletions(-)

Approvals:
  Gabe Black: Looks good to me, but someone else must approve; Looks good  
to me, approved

  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/port.cc b/src/mem/port.cc
index 6460b59..b901571 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -131,7 +131,7 @@
 _responsePort = response_port;
 Port::bind(peer);
 // response port also keeps track of request port
-_responsePort->slaveBind(*this);
+_responsePort->responderBind(*this);
 }

 void
@@ -139,7 +139,7 @@
 {
 panic_if(!isConnected(), "Can't unbind request port %s which is "
 "not bound.", name());
-_responsePort->slaveUnbind();
+_responsePort->responderUnbind();
 _responsePort = &defaultResponsePort;
 Port::unbind();
 }
@@ -164,7 +164,7 @@
 }

 /**
- * Slave port
+ * Response port
  */
 ResponsePort::ResponsePort(const std::string& name, SimObject* _owner,
 PortID id) : Port(name, id), _requestPort(&defaultRequestPort),
@@ -177,14 +177,14 @@
 }

 void
-ResponsePort::slaveUnbind()
+ResponsePort::responderUnbind()
 {
 _requestPort = &defaultRequestPort;
 Port::unbind();
 }

 void
-ResponsePort::slaveBind(RequestPort& request_port)
+ResponsePort::responderBind(RequestPort& request_port)
 {
 _requestPort = &request_port;
 Port::bind(request_port);
diff --git a/src/mem/port.hh b/src/mem/port.hh
index f378f07..c933af62 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -423,13 +423,13 @@
  * Called by the request port to unbind. Should never be called
  * directly.
  */
-void slaveUnbind();
+void responderUnbind();

 /**
  * Called by the request port to bind. Should never be called
  * directly.
  */
-void slaveBind(RequestPort& request_port);
+void responderBind(RequestPort& request_port);

 /**
  * Default implementations.
diff --git a/src/mem/token_port.cc b/src/mem/token_port.cc
index 1a8439d..46d9116 100644
--- a/src/mem/token_port.cc
+++ b/src/mem/token_port.cc
@@ -109,7 +109,7 @@
 void
 TokenSlavePort::unbind()
 {
-SlavePort::slaveUnbind();
+SlavePort::responderUnbind();
 tokenMasterPort = nullptr;
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9106397b8816d8148dd916510bbcf65ed499d303
Gerrit-Change-Number: 32309
Gerrit-PatchSet: 5
Gerrit-Owner: Shivani Parekh 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Emily Brickey 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Shivani Parekh 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: update port terminology

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32310 )


Change subject: learning-gem5: update port terminology
..

learning-gem5: update port terminology

Change-Id: I0ca705cf93396b5c34a0ac4dce30411c5c866733
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32310
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/learning_gem5/part2/SimpleCache.py
M src/learning_gem5/part2/SimpleMemobj.py
M src/learning_gem5/part2/simple_cache.hh
M src/learning_gem5/part2/simple_memobj.hh
4 files changed, 22 insertions(+), 22 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/learning_gem5/part2/SimpleCache.py  
b/src/learning_gem5/part2/SimpleCache.py

index bd5ebfc..40892b5 100644
--- a/src/learning_gem5/part2/SimpleCache.py
+++ b/src/learning_gem5/part2/SimpleCache.py
@@ -36,7 +36,7 @@
 # Vector port example. Both the instruction and data ports connect to  
this

 # port which is automatically split out into two ports.
 cpu_side = VectorSlavePort("CPU side port, receives requests")
-mem_side = MasterPort("Memory side port, sends requests")
+mem_side = RequestPort("Memory side port, sends requests")

 latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")

diff --git a/src/learning_gem5/part2/SimpleMemobj.py  
b/src/learning_gem5/part2/SimpleMemobj.py

index aee81c4..b72ebe2 100644
--- a/src/learning_gem5/part2/SimpleMemobj.py
+++ b/src/learning_gem5/part2/SimpleMemobj.py
@@ -32,6 +32,6 @@
 type = 'SimpleMemobj'
 cxx_header = "learning_gem5/part2/simple_memobj.hh"

-inst_port = SlavePort("CPU side port, receives requests")
-data_port = SlavePort("CPU side port, receives requests")
-mem_side = MasterPort("Memory side port, sends requests")
+inst_port = ResponsePort("CPU side port, receives requests")
+data_port = ResponsePort("CPU side port, receives requests")
+mem_side = RequestPort("Memory side port, sends requests")
diff --git a/src/learning_gem5/part2/simple_cache.hh  
b/src/learning_gem5/part2/simple_cache.hh

index dbc128b..4e57c87 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -51,7 +51,7 @@
  * Port on the CPU-side that receives requests.
  * Mostly just forwards requests to the cache (owner)
  */
-class CPUSidePort : public SlavePort
+class CPUSidePort : public ResponsePort
 {
   private:
 /// Since this is a vector port, need to know what number this one  
is

@@ -71,7 +71,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 CPUSidePort(const std::string& name, int id, SimpleCache *owner) :
-SlavePort(name, owner), id(id), owner(owner), needRetry(false),
+ResponsePort(name, owner), id(id), owner(owner),  
needRetry(false),

 blockedPacket(nullptr)
 { }

@@ -137,7 +137,7 @@
  * Port on the memory-side that receives responses.
  * Mostly just forwards requests to the cache (owner)
  */
-class MemSidePort : public MasterPort
+class MemSidePort : public RequestPort
 {
   private:
 /// The object that owns this object (SimpleCache)
@@ -151,7 +151,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 MemSidePort(const std::string& name, SimpleCache *owner) :
-MasterPort(name, owner), owner(owner), blockedPacket(nullptr)
+RequestPort(name, owner), owner(owner), blockedPacket(nullptr)
 { }

 /**
diff --git a/src/learning_gem5/part2/simple_memobj.hh  
b/src/learning_gem5/part2/simple_memobj.hh

index b7c57ca..11a4b36 100644
--- a/src/learning_gem5/part2/simple_memobj.hh
+++ b/src/learning_gem5/part2/simple_memobj.hh
@@ -48,7 +48,7 @@
  * Mostly just forwards requests to the owner.
  * Part of a vector of ports. One for each CPU port (e.g., data, inst)
  */
-class CPUSidePort : public SlavePort
+class CPUSidePort : public ResponsePort
 {
   private:
 /// The object that owns this object (SimpleMemobj)
@@ -65,7 +65,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 CPUSidePort(const std::string& name, SimpleMemobj *owner) :
-SlavePort(name, owner), owner(owner), needRetry(false),
+ResponsePort(name, owner), owner(owner), needRetry(false),
 blockedPacket(nullptr)
 { }

@@ -79,7 +79,7 @@

 /**
  * Get a list of the non-overlapping address ranges the owner is
- * responsible for. All slave ports must override this function
+ * responsible for. All response ports must override this function
  * and return a populated list with at least one item.

[gem5-dev] Change in gem5/gem5[develop]: arch: update port terminology

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32311 )


Change subject: arch: update port terminology
..

arch: update port terminology

Change-Id: Ifcf90534d8e5ff5fc68538ec87dc541517ea404d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32311
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Giacomo Travaglini 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/ArmTLB.py
M src/arch/generic/BaseTLB.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/pagetable_walker.hh
M src/arch/x86/X86LocalApic.py
M src/arch/x86/X86TLB.py
M src/arch/x86/pagetable_walker.hh
7 files changed, 11 insertions(+), 11 deletions(-)

Approvals:
  Gabe Black: Looks good to me, but someone else must approve; Looks good  
to me, approved

  Giacomo Travaglini: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 721d062..a821a04 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -54,7 +54,7 @@
 # to the Stage2MMU, and shared by the two table walkers, but we
 # access it through the ITB and DTB walked objects in the CPU for
 # symmetry with the other ISAs.
-port = MasterPort("Port used by the two table walkers")
+port = RequestPort("Port used by the two table walkers")

 sys = Param.System(Parent.any, "system object parameter")

diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 02776e6..cca7da6 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -34,4 +34,4 @@
 cxx_header = "arch/generic/tlb.hh"
 # Ports to connect with other TLB levels
 slave  = VectorSlavePort("Port closer to the CPU side")
-master = MasterPort("Port closer to memory side")
+master = RequestPort("Port closer to memory side")
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index 884b71f..4844feb 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -37,7 +37,7 @@
 type = 'RiscvPagetableWalker'
 cxx_class = 'RiscvISA::Walker'
 cxx_header = 'arch/riscv/pagetable_walker.hh'
-port = MasterPort("Port for the hardware table walker")
+port = RequestPort("Port for the hardware table walker")
 system = Param.System(Parent.any, "system object")
 num_squash_per_cycle = Param.Unsigned(4,
 "Number of outstanding walks that can be squashed per cycle")
diff --git a/src/arch/riscv/pagetable_walker.hh  
b/src/arch/riscv/pagetable_walker.hh

index 60826a0..d9ab569 100644
--- a/src/arch/riscv/pagetable_walker.hh
+++ b/src/arch/riscv/pagetable_walker.hh
@@ -58,11 +58,11 @@
 {
   protected:
 // Port for accessing memory
-class WalkerPort : public MasterPort
+class WalkerPort : public RequestPort
 {
   public:
 WalkerPort(const std::string &_name, Walker * _walker) :
-  MasterPort(_name, _walker), walker(_walker)
+  RequestPort(_name, _walker), walker(_walker)
 {}

   protected:
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index a28f6f3..442a5e1 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -48,11 +48,11 @@
 type = 'X86LocalApic'
 cxx_class = 'X86ISA::Interrupts'
 cxx_header = 'arch/x86/interrupts.hh'
-int_master = MasterPort("Port for sending interrupt messages")
-int_slave = SlavePort("Port for receiving interrupt messages")
+int_master = RequestPort("Port for sending interrupt messages")
+int_slave = ResponsePort("Port for receiving interrupt messages")
 int_latency = Param.Latency('1ns', \
 "Latency for an interrupt to propagate through this device.")
-pio = SlavePort("Programmed I/O port")
+pio = ResponsePort("Programmed I/O port")
 system = Param.System(Parent.any, "System this device is part of")

 pio_latency = Param.Latency('100ns', 'Programmed IO latency')
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index bb35526..d9dd980 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -43,7 +43,7 @@
 type = 'X86PagetableWalker'
 cxx_class = 'X86ISA::Walker'
 cxx_header = 'arch/x86/pagetable_walker.hh'
-port = MasterPort("Port for the hardware table walker")
+port = RequestPort("Port for the hardware table walker")
 system = Param.System(Parent.any, "system object")
 num_squash_per_cycle = Param.Unsigned(4,
 "Number of outstanding walks that can be squashed per cycle")
diff --git a/src/arch/x86/pagetable_walker.hh  
b/src/arch/x86/pagetable_walker.hh

index a269426..55bb098 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -57,11 +57,11 @@
 {
   protected:
 // Port for

[gem5-dev] Change in gem5/gem5[develop]: systemc,sim: Update port terminology

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32316 )


Change subject: systemc,sim: Update port terminology
..

systemc,sim: Update port terminology

Change-Id: Iaeafe94245e383fcb1146c99c893fd56fe9bb636
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32316
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/sim/System.py
M src/sim/system.hh
M src/systemc/tlm_bridge/TlmBridge.py
M src/systemc/tlm_bridge/gem5_to_tlm.hh
M src/systemc/tlm_bridge/tlm_to_gem5.hh
5 files changed, 10 insertions(+), 10 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/System.py b/src/sim/System.py
index e028f48..dcef74b 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -51,7 +51,7 @@
 class System(SimObject):
 type = 'System'
 cxx_header = "sim/system.hh"
-system_port = MasterPort("System port")
+system_port = RequestPort("System port")

 cxx_exports = [
 PyBindMethod("getMemoryMode"),
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 9480821..8e2c472 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -79,7 +79,7 @@
  * master for debug access and for non-structural entities that do
  * not have a port of their own.
  */
-class SystemPort : public MasterPort
+class SystemPort : public RequestPort
 {
   public:

@@ -87,7 +87,7 @@
  * Create a system port with a name and an owner.
  */
 SystemPort(const std::string &_name, SimObject *_owner)
-: MasterPort(_name, _owner)
+: RequestPort(_name, _owner)
 { }
 bool recvTimingResp(PacketPtr pkt) override
 { panic("SystemPort does not receive timing!\n"); return false; }
@@ -237,7 +237,7 @@
  *
  * @return a reference to the system port we own
  */
-MasterPort& getSystemPort() { return _systemPort; }
+RequestPort& getSystemPort() { return _systemPort; }

 /**
  * Additional function to return the Port of a memory object.
diff --git a/src/systemc/tlm_bridge/TlmBridge.py  
b/src/systemc/tlm_bridge/TlmBridge.py

index 6218153..1851464 100644
--- a/src/systemc/tlm_bridge/TlmBridge.py
+++ b/src/systemc/tlm_bridge/TlmBridge.py
@@ -37,7 +37,7 @@

 system = Param.System(Parent.any, "system")

-gem5 = SlavePort('gem5 slave port')
+gem5 = ResponsePort('gem5 slave port')
 addr_ranges = VectorParam.AddrRange([],
 'Addresses served by this port\'s TLM side')

@@ -49,7 +49,7 @@

 system = Param.System(Parent.any, "system")

-gem5 = MasterPort('gem5 master port')
+gem5 = RequestPort('gem5 master port')


 class Gem5ToTlmBridge32(Gem5ToTlmBridgeBase):
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.hh  
b/src/systemc/tlm_bridge/gem5_to_tlm.hh

index afc8ad9..7e69e3c 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.hh
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.hh
@@ -85,7 +85,7 @@
 class Gem5ToTlmBridge : public Gem5ToTlmBridgeBase
 {
   private:
-class BridgeSlavePort : public SlavePort
+class BridgeSlavePort : public ResponsePort
 {
   protected:
 Gem5ToTlmBridge &bridge;
@@ -130,7 +130,7 @@
   public:
 BridgeSlavePort(const std::string &name_,
 Gem5ToTlmBridge &bridge_) :
-SlavePort(name_, nullptr), bridge(bridge_)
+ResponsePort(name_, nullptr), bridge(bridge_)
 {}
 };

diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.hh  
b/src/systemc/tlm_bridge/tlm_to_gem5.hh

index 03bac29..e2e7540 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.hh
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.hh
@@ -89,7 +89,7 @@
 TlmSenderState(tlm::tlm_generic_payload &trans) : trans(trans) {}
 };

-class BridgeMasterPort : public MasterPort
+class BridgeMasterPort : public RequestPort
 {
   protected:
 TlmToGem5Bridge &bridge;
@@ -105,7 +105,7 @@
   public:
 BridgeMasterPort(const std::string &name_,
  TlmToGem5Bridge &bridge_) :
-MasterPort(name_, nullptr), bridge(bridge_)
+RequestPort(name_, nullptr), bridge(bridge_)
 {}
 };


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32316
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaeafe94245e383fcb1146c99c893fd56fe9bb636
Gerrit-Change-Number: 32316
Gerrit-PatchSet: 5
Gerrit-Owner: Shivani Parekh 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Shivani Parekh 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: update port terminology

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32313 )


Change subject: gpu-compute: update port terminology
..

gpu-compute: update port terminology

Change-Id: I3121c4afb1e137aebe09c1d694e9484844d02b9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32313
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matt Sinclair 
Reviewed-by: Matt Poremba 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/gpu-compute/GPU.py
M src/gpu-compute/LdsState.py
M src/gpu-compute/X86GPUTLB.py
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/lds_state.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
9 files changed, 37 insertions(+), 36 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matt Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index aec4f48..05df84d 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -161,11 +161,12 @@

 memory_port = VectorMasterPort("Port to the memory system")
 translation_port = VectorMasterPort('Port to the TLB hierarchy')
-sqc_port = MasterPort("Port to the SQC (I-cache")
-sqc_tlb_port = MasterPort("Port to the TLB for the SQC (I-cache)")
-scalar_port = MasterPort("Port to the scalar data cache")
-scalar_tlb_port = MasterPort("Port to the TLB for the scalar data  
cache")
-gmTokenPort = MasterPort("Port to the GPU coalesecer for sharing  
tokens")

+sqc_port = RequestPort("Port to the SQC (I-cache")
+sqc_tlb_port = RequestPort("Port to the TLB for the SQC (I-cache)")
+scalar_port = RequestPort("Port to the scalar data cache")
+scalar_tlb_port = RequestPort("Port to the TLB for the scalar data  
cache")
+gmTokenPort = RequestPort("Port to the GPU coalesecer for sharing  
tokens")

+
 perLaneTLB = Param.Bool(False, "enable per-lane TLB")
 prefetch_depth = Param.Int(0, "Number of prefetches triggered at a  
time"\

"(0 turns off prefetching)")
@@ -193,7 +194,7 @@
 max_cu_tokens = Param.Int(4, "Maximum number of tokens, i.e., the  
number"\
 " of instructions that can be sent to  
coalescer")

 ldsBus = Bridge() # the bridge between the CU and its LDS
-ldsPort = MasterPort("The port that goes to the LDS")
+ldsPort = RequestPort("The port that goes to the LDS")
 localDataStore = Param.LdsState("the LDS for this CU")

 vector_register_file = VectorParam.VectorRegisterFile("Vector  
register "\

diff --git a/src/gpu-compute/LdsState.py b/src/gpu-compute/LdsState.py
index 2cf8c3a..6bd0a7e 100644
--- a/src/gpu-compute/LdsState.py
+++ b/src/gpu-compute/LdsState.py
@@ -44,4 +44,4 @@
 bankConflictPenalty = Param.Int(1, 'penalty per LDS bank conflict  
when '\

 'accessing data')
 banks = Param.Int(32, 'Number of LDS banks')
-cuPort = SlavePort("port that goes to the compute unit")
+cuPort = ResponsePort("port that goes to the compute unit")
diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py
index 701743d..bd22bee 100644
--- a/src/gpu-compute/X86GPUTLB.py
+++ b/src/gpu-compute/X86GPUTLB.py
@@ -40,7 +40,7 @@
 class X86PagetableWalker(SimObject):
 type = 'X86PagetableWalker'
 cxx_class = 'X86ISA::Walker'
-port = SlavePort("Port for the hardware table walker")
+port = ResponsePort("Port for the hardware table walker")
 system = Param.System(Parent.any, "system object")

 class X86GPUTLB(ClockedObject):
diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index 7e0947f..9a41233 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -2590,7 +2590,7 @@
 computeUnit->cu_id, gpuDynInst->simdId,
 gpuDynInst->wfSlotId);
 return false;
-} else if (!MasterPort::sendTimingReq(pkt)) {
+} else if (!RequestPort::sendTimingReq(pkt)) {
 // need to stall the LDS port until a recvReqRetry() is received
 // this indicates that there is more space
 stallPort();
@@ -2634,7 +2634,7 @@

 DPRINTF(GPUPort, "CU%d: retrying LDS send\n", computeUnit->cu_id);

-if (!MasterPort::sendTimingReq(packet)) {
+if (!RequestPort::sendTimingReq(packet)) {
 // Stall port
 stallPort();
 DPRINTF(GPUPort, ": LDS send failed again\n");
diff --git a/src/gpu-compute/compute_unit.hh  
b/src/gpu-compute/compute_unit.hh

index cf51a86..211dd53 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -649,11 +649,11 @@
 GMTokenPor

[gem5-dev] Change in gem5/gem5[develop]: dev: Update port terminology

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32315 )


Change subject: dev: Update port terminology
..

dev: Update port terminology

Change-Id: I48bd6718471f034f7c3226279efe7ada0d9c81e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32315
Reviewed-by: Giacomo Travaglini 
Reviewed-by: Gabe Black 
Maintainer: Giacomo Travaglini 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/dev/Device.py
M src/dev/arm/Gic.py
M src/dev/arm/SMMUv3.py
M src/dev/arm/gic_v3_its.hh
M src/dev/arm/smmu_v3_ports.cc
M src/dev/arm/smmu_v3_ports.hh
M src/dev/dma_device.cc
M src/dev/dma_device.hh
M src/dev/x86/I82094AA.py
9 files changed, 19 insertions(+), 18 deletions(-)

Approvals:
  Gabe Black: Looks good to me, but someone else must approve; Looks good  
to me, approved

  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/Device.py b/src/dev/Device.py
index 8950763..d9f351d 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -46,7 +46,7 @@
 type = 'PioDevice'
 cxx_header = "dev/io_device.hh"
 abstract = True
-pio = SlavePort("Programmed I/O port")
+pio = ResponsePort("Programmed I/O port")
 system = Param.System(Parent.any, "System this device is part of")

 def generateBasicPioDeviceNode(self, state, name, pio_addr,
@@ -79,7 +79,7 @@
 type = 'DmaDevice'
 cxx_header = "dev/dma_device.hh"
 abstract = True
-dma = MasterPort("DMA port")
+dma = RequestPort("DMA port")

 _iommu = None

diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 59ade75..e2229b8 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -177,7 +177,7 @@
 type = 'Gicv3Its'
 cxx_header = "dev/arm/gic_v3_its.hh"

-dma = MasterPort("DMA port")
+dma = RequestPort("DMA port")
 pio_size = Param.Unsigned(0x2, "Gicv3Its pio size")

 # CIL [36] = 0: ITS supports 16-bit CollectionID
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 5be09de..0b9ab21 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -43,9 +43,9 @@
 type = 'SMMUv3SlaveInterface'
 cxx_header = 'dev/arm/smmu_v3_slaveifc.hh'

-slave = SlavePort('Device port')
-ats_master = MasterPort('ATS master port')
-ats_slave  = SlavePort('ATS slave port')
+slave = ResponsePort('Device port')
+ats_master = RequestPort('ATS master port')
+ats_slave  = ResponsePort('ATS slave port')

 port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')
 wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)')
@@ -74,10 +74,11 @@
 type = 'SMMUv3'
 cxx_header = 'dev/arm/smmu_v3.hh'

-master = MasterPort('Master port')
-master_walker = MasterPort(
+master = RequestPort('Master port')
+master_walker = RequestPort(
 'Master port for SMMU initiated HWTW requests (optional)')
-control = SlavePort('Control port for accessing memory-mapped  
registers')

+control = ResponsePort(
+'Control port for accessing memory-mapped registers')
 sample_period = Param.Clock('10us', 'Stats sample period')
 reg_map = Param.AddrRange('Address range for control registers')
 system = Param.System(Parent.any, "System this device is part of")
diff --git a/src/dev/arm/gic_v3_its.hh b/src/dev/arm/gic_v3_its.hh
index 8575f7e..54beb3e 100644
--- a/src/dev/arm/gic_v3_its.hh
+++ b/src/dev/arm/gic_v3_its.hh
@@ -77,14 +77,14 @@
 friend class ::ItsTranslation;
 friend class ::ItsCommand;
   public:
-class DataPort : public MasterPort
+class DataPort : public RequestPort
 {
   protected:
 Gicv3Its &its;

   public:
 DataPort(const std::string &_name, Gicv3Its &_its) :
-MasterPort(_name, &_its),
+RequestPort(_name, &_its),
 its(_its)
 {}

diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc
index f972fcf..3f54250 100644
--- a/src/dev/arm/smmu_v3_ports.cc
+++ b/src/dev/arm/smmu_v3_ports.cc
@@ -42,7 +42,7 @@
 #include "dev/arm/smmu_v3_slaveifc.hh"

 SMMUMasterPort::SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu) :
-MasterPort(_name, &_smmu),
+RequestPort(_name, &_smmu),
 smmu(_smmu)
 {}

@@ -60,7 +60,7 @@

 SMMUMasterTableWalkPort::SMMUMasterTableWalkPort(const std::string &_name,
  SMMUv3 &_smmu) :
-MasterPort(_name, &_smmu),
+RequestPort(_name, &_smmu),
 smmu(_smmu)
 {}

diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh
index 9d54f13..ee68bbb 100644
--- a/src/dev/arm/smmu_v3_ports.hh
+++ b/src/dev/arm/smmu_v3_ports.hh
@@ -44,7 +44,7 @@
 class SMMUv3;
 class SMMUv3SlaveInterface;

-class SMMUMasterPort : public MasterPort
+class SMMUMasterPort : public RequestPort
 {
   protected:
 SMMUv3 &smmu;
@@ -58,7 +58,7 @

[gem5-dev] Change in gem5/gem5[develop]: cpu: update port terminology

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32312 )


Change subject: cpu: update port terminology
..

cpu: update port terminology

Change-Id: I891e7a74683c1775c75a62454fcfdecb7511b7e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32312
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
---
M src/cpu/BaseCPU.py
M src/cpu/base.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/kvm/base.hh
M src/cpu/minor/cpu.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/noncaching.cc
M src/cpu/simple/noncaching.hh
M src/cpu/simple/timing.hh
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/RubyDirectedTester.hh
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
M src/cpu/testers/memtest/MemTest.py
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/Check.cc
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/trace/trace_cpu.hh
29 files changed, 67 insertions(+), 67 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 96e96fc..ee6c646 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -175,8 +175,8 @@

 tracer = Param.InstTracer(default_tracer, "Instruction tracer")

-icache_port = MasterPort("Instruction Port")
-dcache_port = MasterPort("Data Port")
+icache_port = RequestPort("Instruction Port")
+dcache_port = RequestPort("Data Port")
 _cached_ports = ['icache_port', 'dcache_port']

 if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index a00e83d..5c0c709 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -162,7 +162,7 @@
 virtual PortProxy::SendFunctionalFunc
 getSendFunctional()
 {
-auto port = dynamic_cast(&getDataPort());
+auto port = dynamic_cast(&getDataPort());
 assert(port);
 return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); };
 }
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index d9d6d7e..b016938 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -113,13 +113,13 @@
 }

 void
-CheckerCPU::setIcachePort(MasterPort *icache_port)
+CheckerCPU::setIcachePort(RequestPort *icache_port)
 {
 icachePort = icache_port;
 }

 void
-CheckerCPU::setDcachePort(MasterPort *dcache_port)
+CheckerCPU::setDcachePort(RequestPort *dcache_port)
 {
 dcachePort = dcache_port;
 }
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 6bd7022..3c04064 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -99,9 +99,9 @@

 void setSystem(System *system);

-void setIcachePort(MasterPort *icache_port);
+void setIcachePort(RequestPort *icache_port);

-void setDcachePort(MasterPort *dcache_port);
+void setDcachePort(RequestPort *dcache_port);

 Port &
 getDataPort() override
@@ -127,8 +127,8 @@

 System *systemPtr;

-MasterPort *icachePort;
-MasterPort *dcachePort;
+RequestPort *icachePort;
+RequestPort *dcachePort;

 ThreadContext *tc;

diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index eff7a3c..e999499 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -572,15 +572,15 @@


 /**
- * KVM memory port.  Uses default MasterPort behavior and provides an
+ * KVM memory port.  Uses default RequestPort behavior and provides an
  * interface for KVM to transparently submit atomic or timing requests.
  */
-class KVMCpuPort : public MasterPort
+class KVMCpuPort : public RequestPort
 {

   public:
 KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu)
-: MasterPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
+: RequestPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
 { }
 /**
  * Interface to send Atomic or Timing IO request.  Assumes that  
the pkt

diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index b8ca087..579a96b 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -95,7 +95,7 @@
   public:
 /** Provide a non-protected base class for Minor's Ports as derived
  *  classes are created by Fetch1 and Execute */
-class MinorCPUPort : public MasterPort
+class MinorCPUPort : public RequestPort
 {
   public:
 /** The e

[gem5-dev] Change in gem5/gem5[develop]: mem: Deprecate SlavePort and MasterPort classes

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32308 )


Change subject: mem: Deprecate SlavePort and MasterPort classes
..

mem: Deprecate SlavePort and MasterPort classes

After this change, if you use these classes or inherit from these
classes, the compiler will now give you a warning that these names are
deprecated. Instead, you should use ResponsePort and RequestPort,
respectively.

This patch simply deprecates these names. The following patches will
convert all of the code in gem5 to use these new names. The first step
is converting the class names and the uses of these classes, then we
will update the variable names to be more precise as well.

Change-Id: I5e6e90b2916df4dbfccdaabe97423f377a1f6e3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32308
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/port.cc
M src/mem/port.hh
2 files changed, 118 insertions(+), 97 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/port.cc b/src/mem/port.cc
index 47e94f4..6460b59 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -50,7 +50,7 @@
 namespace
 {

-class DefaultMasterPort : public MasterPort
+class DefaultRequestPort : public RequestPort
 {
   protected:
 [[noreturn]] void
@@ -60,7 +60,7 @@
 }

   public:
-DefaultMasterPort() : MasterPort("default_master_port", nullptr) {}
+DefaultRequestPort() : RequestPort("default_request_port", nullptr) {}

 // Atomic protocol.
 Tick recvAtomicSnoop(PacketPtr) override { blowUp(); }
@@ -75,7 +75,7 @@
 void recvFunctionalSnoop(PacketPtr) override { blowUp(); }
 };

-class DefaultSlavePort : public SlavePort
+class DefaultResponsePort : public ResponsePort
 {
   protected:
 [[noreturn]] void
@@ -85,7 +85,7 @@
 }

   public:
-DefaultSlavePort() : SlavePort("default_slave_port", nullptr) {}
+DefaultResponsePort() : ResponsePort("default_response_port", nullptr)  
{}


 // Atomic protocol.
 Tick recvAtomic(PacketPtr) override { blowUp(); }
@@ -103,54 +103,55 @@
 AddrRangeList getAddrRanges() const override { return AddrRangeList();  
}

 };

-DefaultMasterPort defaultMasterPort;
-DefaultSlavePort defaultSlavePort;
+DefaultRequestPort defaultRequestPort;
+DefaultResponsePort defaultResponsePort;

 } // anonymous namespace

 /**
- * Master port
+ * Request port
  */
-MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID  
_id)

-: Port(name, _id), _slavePort(&defaultSlavePort), owner(*_owner)
+RequestPort::RequestPort(const std::string& name, SimObject* _owner,
+PortID _id) : Port(name, _id), _responsePort(&defaultResponsePort),
+owner(*_owner)
 {
 }

-MasterPort::~MasterPort()
+RequestPort::~RequestPort()
 {
 }

 void
-MasterPort::bind(Port &peer)
+RequestPort::bind(Port &peer)
 {
-auto *slave_port = dynamic_cast(&peer);
-fatal_if(!slave_port, "Can't bind port %s to non-slave port %s.",
+auto *response_port = dynamic_cast(&peer);
+fatal_if(!response_port, "Can't bind port %s to non-response port %s.",
  name(), peer.name());
-// master port keeps track of the slave port
-_slavePort = slave_port;
+// request port keeps track of the response port
+_responsePort = response_port;
 Port::bind(peer);
-// slave port also keeps track of master port
-_slavePort->slaveBind(*this);
+// response port also keeps track of request port
+_responsePort->slaveBind(*this);
 }

 void
-MasterPort::unbind()
+RequestPort::unbind()
 {
-panic_if(!isConnected(), "Can't unbind master port %s which is not  
bound.",

- name());
-_slavePort->slaveUnbind();
-_slavePort = &defaultSlavePort;
+panic_if(!isConnected(), "Can't unbind request port %s which is "
+"not bound.", name());
+_responsePort->slaveUnbind();
+_responsePort = &defaultResponsePort;
 Port::unbind();
 }

 AddrRangeList
-MasterPort::getAddrRanges() const
+RequestPort::getAddrRanges() const
 {
-return _slavePort->getAddrRanges();
+return _responsePort->getAddrRanges();
 }

 void
-MasterPort::printAddr(Addr a)
+RequestPort::printAddr(Addr a)
 {
 auto req = std::make_shared(
 a, 1, 0, Request::funcMasterId);
@@ -165,32 +166,32 @@
 /**
  * Slave port
  */
-SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
-: Port(name, id), _masterPort(&defaultMasterPort),
+ResponsePort::ResponsePort(const std::string& name, SimObject* _owner,
+PortID id) : Port(name, id), _requestPort(&defaultRequestPort),
 defaultBackdoorWarned(false), owner(*_owner)
 {
 }

-SlavePort::~SlavePort()
+ResponsePort::~ResponsePort()
 {
 }

 void
-SlavePort::slaveUnbind()
+ResponsePort::slaveUnbind()
 {
-_masterPort = &defaultMasterPort;
+_reque

[gem5-dev] Change in gem5/gem5[develop]: mem: Update port terminology

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32314 )


Change subject: mem: Update port terminology
..

mem: Update port terminology

Change-Id: Ib4fc8cad7139d4971e74930295a69e576f6da3cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32314
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/AddrMapper.py
M src/mem/Bridge.py
M src/mem/CommMonitor.py
M src/mem/ExternalMaster.py
M src/mem/MemChecker.py
M src/mem/MemDelay.py
M src/mem/SerialLink.py
M src/mem/XBar.py
M src/mem/addr_mapper.hh
M src/mem/bridge.cc
M src/mem/bridge.hh
M src/mem/cache/Cache.py
M src/mem/cache/base.hh
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
M src/mem/comm_monitor.hh
M src/mem/external_master.hh
M src/mem/hmc_controller.cc
M src/mem/mem_checker_monitor.hh
M src/mem/mem_delay.cc
M src/mem/mem_delay.hh
M src/mem/noncoherent_xbar.cc
M src/mem/noncoherent_xbar.hh
M src/mem/packet_queue.cc
M src/mem/packet_queue.hh
M src/mem/port_proxy.hh
M src/mem/qos/QoSMemSinkCtrl.py
M src/mem/qport.hh
M src/mem/ruby/network/MessageBuffer.py
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Controller.py
M src/mem/ruby/system/Sequencer.py
M src/mem/serial_link.cc
M src/mem/serial_link.hh
M src/mem/snoop_filter.cc
M src/mem/snoop_filter.hh
M src/mem/token_port.cc
M src/mem/token_port.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
41 files changed, 155 insertions(+), 153 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py
index 1e8dfea..52d7ef8 100644
--- a/src/mem/AddrMapper.py
+++ b/src/mem/AddrMapper.py
@@ -48,8 +48,8 @@
 abstract = True

 # one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")


 # Range address mapper that maps a set of original ranges to a set of
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 95caa0c..a89e7f9 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -42,8 +42,8 @@
 class Bridge(ClockedObject):
 type = 'Bridge'
 cxx_header = "mem/bridge.hh"
-slave = SlavePort('Slave port')
-master = MasterPort('Master port')
+slave = ResponsePort('Slave port')
+master = RequestPort('Master port')
 req_size = Param.Unsigned(16, "The number of requests to buffer")
 resp_size = Param.Unsigned(16, "The number of responses to buffer")
 delay = Param.Latency('0ns', "The latency of this bridge")
diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index b1229c7..0fd884d 100644
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -47,8 +47,8 @@
 system = Param.System(Parent.any, "System that the monitor belongs  
to.")


 # one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")

 # control the sample period window length of this monitor
 sample_period = Param.Clock("1ms", "Sample period for histograms")
diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalMaster.py
index bcc3836..6d8b5df 100644
--- a/src/mem/ExternalMaster.py
+++ b/src/mem/ExternalMaster.py
@@ -41,7 +41,7 @@
 type = 'ExternalMaster'
 cxx_header = "mem/external_master.hh"

-port = MasterPort("Master port")
+port = RequestPort("Master port")

 port_type = Param.String('stub', 'Registered external port handler'
 ' to pass this port to in instantiation')
diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py
index 0671962..714ea79 100644
--- a/src/mem/MemChecker.py
+++ b/src/mem/MemChecker.py
@@ -46,10 +46,10 @@
 cxx_header = "mem/mem_checker_monitor.hh"

 # one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
-cpu_side = SlavePort("Alias for slave")
-mem_side = MasterPort("Alias for master")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")
+cpu_side = ResponsePort("Alias for slave")
+mem_side = RequestPort("Alias for master")
 warn_only = Param.Bool(False, "Warn about violations only")
 memchecker = Param.MemChecker("Instance shared with other monitors")

diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py
index fdc0350..7ffb608 100644
--- a/src/mem/MemDelay.py
+++ b/src/mem/MemDelay.py
@@ -41,8 +41,8 @@
 cxx_header = 'mem/mem_delay.hh'
 abstract = True

-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")

 class SimpleMemDelay(MemDelay):
 type = 'SimpleMemDelay'
di

[gem5-dev] Re: Change in gem5/gem5[develop]: mem-cache: Create Compressor namespace

2020-08-26 Thread Jason Lowe-Power via gem5-dev

It's a good idea to send an email to gem5-users. However, with our new
release model, it should affect many fewer people. It's probably not true
today, but the vision is that the only people who will care if develop
breaks something are people subscribed to gem5-dev :).

Cheers,
Jason

On Wed, Aug 26, 2020 at 12:32 AM Nikos Nikoleris via gem5-dev <
gem5-dev@gem5.org> wrote:

> Do we also need to notify users about this? It might be worth sending an
> email about this. In fact an email with a different subject to both
> gem5-users and gem5-dev as people might ignore emails for a specific CL.
>
> Nikos
>
> On 25/08/2020 23:17, Daniel Carvalho via gem5-dev wrote:
> > Was about to send an e-mail with a heads up, but I guess I was too late.
> >
> > As reported here
> > (
> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-753),
> > itis not an issue caused by this patch itself. SCons does not trigger
> > recompilation when a change modifies the cxx_class; therefore,
> > params/BaseCache.hh is not recompiled and generates the error. To solve
> > this, one must manually delete this file and force a recompilation.
> >
> > Regards,
> > Daniel
> >
> > Em terça-feira, 25 de agosto de 2020 21:20:56 GMT+2, mike upton via
> > gem5-dev  escreveu:
> >
> >
> > This checkin breaks the build.
> >
> > you can check at:
> > http://jenkins.gem5.org:8080/job/gem5_develop/136/
> >
> >
> >
> > On Tue, Aug 25, 2020 at 8:13 AM Daniel Carvalho (Gerrit) via gem5-dev
> > mailto:gem5-dev@gem5.org>> wrote:
> >
> > Daniel Carvalho *submitted* this change.
> >
> > View Change <
> https://gem5-review.googlesource.com/c/public/gem5/+/33294>
> >
> > Approvals: Nikos Nikoleris: Looks good to me, approved; Looks good
> > to me, approved kokoro: Regressions pass
> >
> > mem-cache: Create Compressor namespace
> >
> > Creation of the Compressor namespace. It encapsulates all the cache
> > compressors, and other classes used by them.
> >
> > The following classes have been renamed:
> > BaseCacheCompressor -> Base
> > PerfectCompressor - Perfect
> > RepeatedQwordsCompressor -> RepeatedQwords
> > ZeroCompressor -> Zero
> >
> > BaseDictionaryCompressor and DictionaryCompressor were not renamed
> > because the there is a high probability that users may want to
> > create a Dictionary class that encompasses the dictionary contained
> > by these compressors.
> >
> > To apply this patch one must force recompilation (e.g., by deleting
> > it) of build//params/BaseCache.hh (and any other files that
> > were previously using these compressors).
> >
> > Change-Id: I78cb3b6fb8e3e50a52a04268e0e08dd664d81230
> > Signed-off-by: Daniel R. Carvalho  oda...@yahoo.com.br>>
> > Reviewed-on:
> https://gem5-review.googlesource.com/c/public/gem5/+/33294
> > Reviewed-by: Nikos Nikoleris  nikos.nikole...@arm.com>>
> > Maintainer: Nikos Nikoleris  nikos.nikole...@arm.com>>
> > Tested-by: kokoro  noreply%2bkok...@google.com>>
> > ---
> > M src/mem/cache/base.hh
> > M src/mem/cache/compressors/Compressors.py
> > M src/mem/cache/compressors/base.cc
> > M src/mem/cache/compressors/base.hh
> > M src/mem/cache/compressors/base_delta.cc
> > M src/mem/cache/compressors/base_delta.hh
> > M src/mem/cache/compressors/base_delta_impl.hh
> > M src/mem/cache/compressors/base_dictionary_compressor.cc
> > M src/mem/cache/compressors/cpack.cc
> > M src/mem/cache/compressors/cpack.hh
> > M src/mem/cache/compressors/dictionary_compressor.hh
> > M src/mem/cache/compressors/dictionary_compressor_impl.hh
> > M src/mem/cache/compressors/fpcd.cc
> > M src/mem/cache/compressors/fpcd.hh
> > M src/mem/cache/compressors/multi.cc
> > M src/mem/cache/compressors/multi.hh
> > M src/mem/cache/compressors/perfect.cc
> > M src/mem/cache/compressors/perfect.hh
> > M src/mem/cache/compressors/repeated_qwords.cc
> > M src/mem/cache/compressors/repeated_qwords.hh
> > M src/mem/cache/compressors/zero.cc
> > M src/mem/cache/compressors/zero.hh
> > 22 files changed, 231 insertions(+), 165 deletions(-)
> >
> > diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
> > index 3efc7c7..d30de3f 100644
> > --- a/src/mem/cache/base.hh
> > +++ b/src/mem/cache/base.hh
> > @@ -320,7 +320,7 @@
> > BaseTags *tags;
> >
> > /** Compression method being used. */
> > - BaseCacheCompressor* compressor;
> > + Compressor::Base* compressor;
> >
> > /** Prefetcher */
> > Prefetcher::Base *prefetcher;
> > diff --git a/src/mem/cache/compressors/Compressors.py
> > b/src/mem/cache/compressors/Compressors.py
> > index eb1952a..46050f6 100644
> > --- a/src/mem/cache/compressors/Compressors.py
> > +++ b/src/mem/cache/compressors/Compressors.py
> > @@ -1,4 +1,4 @@
> > -# Copyright (c) 2018 Inria
> > +# Copyright (c) 2018-2020 Inria
> > # All rights

[gem5-dev] Change in gem5/gem5[develop]: mem: convert queued to new style stats

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33475 )



Change subject: mem: convert queued to new style stats
..

mem: convert queued to new style stats

Queued inside src/mem/cache/prefetch converted and dependent on base

Change-Id: I3d5907b58efefc4d8522b89f073507f2548bff2f
---
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
2 files changed, 30 insertions(+), 43 deletions(-)



diff --git a/src/mem/cache/prefetch/queued.cc  
b/src/mem/cache/prefetch/queued.cc

index c2ae090..841a91d 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -97,7 +97,7 @@
   latency(p->latency), queueSquash(p->queue_squash),
   queueFilter(p->queue_filter), cacheSnoop(p->cache_snoop),
   tagPrefetch(p->tag_prefetch),
-  throttleControlPct(p->throttle_control_percentage)
+  throttleControlPct(p->throttle_control_percentage),  
stats_queued(this)

 {
 }

@@ -174,13 +174,13 @@
 addr_prio.first = blockAddress(addr_prio.first);

 if (!samePage(addr_prio.first, pfi.getAddr())) {
-pfSpanPage += 1;
+stats_queued.pfSpanPage += 1;
 }

 bool can_cross_page = (tlb != nullptr);
 if (can_cross_page || samePage(addr_prio.first, pfi.getAddr())) {
 PrefetchInfo new_pfi(pfi,addr_prio.first);
-pfIdentified++;
+stats_queued.pfIdentified++;
 DPRINTF(HWPrefetch, "Found a pf candidate addr: %#x, "
 "inserting into prefetch queue.\n", new_pfi.getAddr());
 // Create and insert the request
@@ -214,7 +214,7 @@
 PacketPtr pkt = pfq.front().pkt;
 pfq.pop_front();

-pfIssued++;
+stats_pbase.pfIssued++;
 issuedPrefetches += 1;
 assert(pkt != nullptr);
 DPRINTF(HWPrefetch, "Generating prefetch for %#x.\n", pkt->getAddr());
@@ -222,32 +222,19 @@
 processMissingTranslations(queueSize - pfq.size());
 return pkt;
 }
-
-void
-Queued::regStats()
-{
-Base::regStats();
-
-pfIdentified
-.name(name() + ".pfIdentified")
-.desc("number of prefetch candidates identified");
-
-pfBufferHit
-.name(name() + ".pfBufferHit")
-.desc("number of redundant prefetches already in prefetch queue");
-
-pfInCache
-.name(name() + ".pfInCache")
-.desc("number of redundant prefetches already in cache/mshr  
dropped");

-
-pfRemovedFull
-.name(name() + ".pfRemovedFull")
-.desc("number of prefetches dropped due to prefetch queue size");
-
-pfSpanPage
-.name(name() + ".pfSpanPage")
-.desc("number of prefetches that crossed the page");
-}
+//Base::regStats();
+Queued::QueuedStats::QueuedStats(Stats::Group *parent)
+: Stats::Group(parent),
+ADD_STAT(pfIdentified, "number of prefetch candidates identified"),
+ADD_STAT(pfBufferHit,
+ "number of redundant prefetches already in prefetch queue"),
+ADD_STAT(pfInCache,
+ "number of redundant prefetches already in cache/mshr dropped"),
+ADD_STAT(pfRemovedFull,
+ "number of prefetches dropped due to prefetch queue size"),
+ADD_STAT(pfSpanPage, "number of prefetches that crossed the page")
+{
+}


 void
@@ -285,7 +272,7 @@
 // check if this prefetch is already redundant
 if (cacheSnoop && (inCache(target_paddr, it->pfInfo.isSecure()) ||
 inMissQueue(target_paddr, it->pfInfo.isSecure( {
-pfInCache++;
+stats_queued.pfInCache++;
 DPRINTF(HWPrefetch, "Dropping redundant in "
 "cache/MSHR prefetch addr:%#x\n", target_paddr);
 } else {
@@ -314,7 +301,7 @@

 /* If the address is already in the queue, update priority and leave */
 if (it != queue.end()) {
-pfBufferHit++;
+stats_queued.pfBufferHit++;
 if (it->priority < priority) {
 /* Update priority value and position in the queue */
 it->priority = priority;
@@ -421,7 +408,7 @@
 if (has_target_pa && cacheSnoop &&
 (inCache(target_paddr, new_pfi.isSecure()) ||
 inMissQueue(target_paddr, new_pfi.isSecure( {
-pfInCache++;
+stats_queued.pfInCache++;
 DPRINTF(HWPrefetch, "Dropping redundant in "
 "cache/MSHR prefetch addr:%#x\n", target_paddr);
 return;
@@ -452,7 +439,7 @@
 {
 /* Verify prefetch buffer space for request */
 if (queue.size() == queueSize) {
-pfRemovedFull++;
+stats_queued.pfRemovedFull++;
 /* Lowest priority packet */
 iterator it = queue.end();
 panic_if (it == queue.begin(),
diff --git a/src/mem/cache/prefetch/queued.hh  
b/src/mem/cache/prefetch/queued.hh

index 5af9093..106c989 100644
--- a/src/mem/cache/prefetch/queued.hh
+++ b/src/mem/cache/prefetch/queued.hh
@@ -167,13 +167,15 @@

[gem5-dev] Change in gem5/gem5[develop]: mem: convert base to new style stats

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33474 )



Change subject: mem: convert base to new style stats
..

mem: convert base to new style stats

Base inside src/mem/cache/prefetch converted

Change-Id: I5b51fcdce43309bb588599325f10366968dca82d
---
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
2 files changed, 12 insertions(+), 19 deletions(-)



diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index d4223aa..87d5d54 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -94,7 +94,8 @@
   onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
   masterId(p->sys->getMasterId(this)),  
pageBytes(p->sys->getPageBytes()),

   prefetchOnAccess(p->prefetch_on_access),
-  useVirtualAddresses(p->use_virtual_addresses), issuedPrefetches(0),
+  useVirtualAddresses(p->use_virtual_addresses),
+  stats_pbase(this), issuedPrefetches(0),
   usefulPrefetches(0), tlb(nullptr)
 {
 }
@@ -109,18 +110,12 @@
 blkSize = cache->getBlockSize();
 lBlkSize = floorLog2(blkSize);
 }
+Base::StatGroup::StatGroup(Stats::Group *parent)
+: Stats::Group(parent),
+ADD_STAT(pfIssued, "number of hwpf issued")
+{
+}

-void
-Base::regStats()
-{
-ClockedObject::regStats();
-
-pfIssued
-.name(name() + ".num_hwpf_issued")
-.desc("number of hwpf issued")
-;
-
-}

 bool
 Base::observeAccess(const PacketPtr &pkt, bool miss) const
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 7009db7..a9e13e4 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -48,8 +48,8 @@

 #include 

-#include "arch/isa_traits.hh"
 #include "arch/generic/tlb.hh"
+#include "arch/isa_traits.hh"
 #include "base/statistics.hh"
 #include "base/types.hh"
 #include "mem/packet.hh"
@@ -318,8 +318,10 @@
 Addr pageOffset(Addr a) const;
 /** Build the address of the i-th block inside the page */
 Addr pageIthBlockAddress(Addr page, uint32_t i) const;
-
-Stats::Scalar pfIssued;
+struct StatGroup : public Stats::Group {
+StatGroup(Stats::Group *parent);
+Stats::Scalar pfIssued;
+} stats_pbase;

 /** Total prefetches issued */
 uint64_t issuedPrefetches;
@@ -349,10 +351,6 @@

 virtual Tick nextPrefetchReadyTime() const = 0;

-/**
- * Register local statistics.
- */
-void regStats() override;

 /**
  * Register probe points for this object.

--
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Gerrit-Change-Id: I5b51fcdce43309bb588599325f10366968dca82d
Gerrit-Change-Number: 33474
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Gerrit-Owner: Eden Avivi 
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix up the selectFunc syscall to work with g++ 10.2.

2020-08-26 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33415 )


Change subject: sim: Fix up the selectFunc syscall to work with g++ 10.2.
..

sim: Fix up the selectFunc syscall to work with g++ 10.2.

This is no longer willing to implicitly cast between the locally defined
Linux::fd_set type and the system fd_set type. That's pretty reasonable
since those types are really independent of one another, and we
shouldn't be using them interchangeably in the first place. That's a
pre-existing condition though, and I just want to get the existing code
to compile for now.

Change-Id: I41d5f3695dfe5f0e406d074d31d13c6e3282df64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33415
Reviewed-by: Ciro Santilli 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/syscall_emul.hh
1 file changed, 4 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Ciro Santilli: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index b23e860..05a29f9 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -95,6 +95,7 @@
 #include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "kern/linux/linux.hh"
 #include "mem/page_table.hh"
 #include "params/Process.hh"
 #include "sim/emul_driver.hh"
@@ -2360,9 +2361,9 @@
 if (retval == -1)
 return -errno;

-FD_ZERO(readfds);
-FD_ZERO(writefds);
-FD_ZERO(errorfds);
+FD_ZERO(reinterpret_cast((typename OS::fd_set *)readfds));
+FD_ZERO(reinterpret_cast((typename OS::fd_set *)writefds));
+FD_ZERO(reinterpret_cast((typename OS::fd_set *)errorfds));

 /**
  * We need to translate the host file descriptor set into a target file

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I41d5f3695dfe5f0e406d074d31d13c6e3282df64
Gerrit-Change-Number: 33415
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33497 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed SMMUATSMasterPort and SMMUATSSlavePort

Change-Id: I91791f8ce585e07b0b3beb383612808931fcb7f0
---
M src/dev/arm/smmu_v3_ports.cc
M src/dev/arm/smmu_v3_ports.hh
M src/dev/arm/smmu_v3_slaveifc.hh
3 files changed, 14 insertions(+), 14 deletions(-)



diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc
index b6d5970..71e1f97 100644
--- a/src/dev/arm/smmu_v3_ports.cc
+++ b/src/dev/arm/smmu_v3_ports.cc
@@ -136,7 +136,7 @@
 return list;
 }

-SMMUATSMasterPort::SMMUATSMasterPort(const std::string &_name,
+SMMUATSRequestPort::SMMUATSRequestPort(const std::string &_name,
  SMMUv3SlaveInterface &_ifc) :
 QueuedRequestPort(_name, &_ifc, reqQueue, snoopRespQueue),
 ifc(_ifc),
@@ -145,12 +145,12 @@
 {}

 bool
-SMMUATSMasterPort::recvTimingResp(PacketPtr pkt)
+SMMUATSRequestPort::recvTimingResp(PacketPtr pkt)
 {
 return ifc.atsMasterRecvTimingResp(pkt);
 }

-SMMUATSSlavePort::SMMUATSSlavePort(const std::string &_name,
+SMMUATSResponsePort::SMMUATSResponsePort(const std::string &_name,
SMMUv3SlaveInterface &_ifc) :
 QueuedResponsePort(_name, &_ifc, respQueue),
 ifc(_ifc),
@@ -158,19 +158,19 @@
 {}

 void
-SMMUATSSlavePort::recvFunctional(PacketPtr pkt)
+SMMUATSResponsePort::recvFunctional(PacketPtr pkt)
 {
 panic("Functional access on ATS port!");
 }

 Tick
-SMMUATSSlavePort::recvAtomic(PacketPtr pkt)
+SMMUATSResponsePort::recvAtomic(PacketPtr pkt)
 {
 return ifc.atsSlaveRecvAtomic(pkt);
 }

 bool
-SMMUATSSlavePort::recvTimingReq(PacketPtr pkt)
+SMMUATSResponsePort::recvTimingReq(PacketPtr pkt)
 {
 return ifc.atsSlaveRecvTimingReq(pkt);
 }
diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh
index 15b37aa..650e1df 100644
--- a/src/dev/arm/smmu_v3_ports.hh
+++ b/src/dev/arm/smmu_v3_ports.hh
@@ -106,7 +106,7 @@
 virtual ~SMMUControlPort() {}
 };

-class SMMUATSMasterPort : public QueuedRequestPort
+class SMMUATSRequestPort : public QueuedRequestPort
 {
   protected:
 SMMUv3SlaveInterface &ifc;
@@ -116,11 +116,11 @@
 virtual bool recvTimingResp(PacketPtr pkt);

   public:
-SMMUATSMasterPort(const std::string &_name, SMMUv3SlaveInterface  
&_ifc);

-virtual ~SMMUATSMasterPort() {}
+SMMUATSRequestPort(const std::string &_name, SMMUv3SlaveInterface  
&_ifc);

+virtual ~SMMUATSRequestPort() {}
 };

-class SMMUATSSlavePort : public QueuedResponsePort
+class SMMUATSResponsePort : public QueuedResponsePort
 {
   protected:
 SMMUv3SlaveInterface &ifc;
@@ -134,8 +134,8 @@
 { return AddrRangeList(); }

   public:
-SMMUATSSlavePort(const std::string &_name, SMMUv3SlaveInterface &_ifc);
-virtual ~SMMUATSSlavePort() {}
+SMMUATSResponsePort(const std::string &_name, SMMUv3SlaveInterface  
&_ifc);

+virtual ~SMMUATSResponsePort() {}
 };

 #endif /* __DEV_ARM_SMMU_V3_PORTS_HH__ */
diff --git a/src/dev/arm/smmu_v3_slaveifc.hh  
b/src/dev/arm/smmu_v3_slaveifc.hh

index 4aa2608..fd4cc1d 100644
--- a/src/dev/arm/smmu_v3_slaveifc.hh
+++ b/src/dev/arm/smmu_v3_slaveifc.hh
@@ -73,8 +73,8 @@
 const Cycles mainTLBLat;

 SMMUResponsePort *slavePort;
-SMMUATSSlavePort  atsSlavePort;
-SMMUATSMasterPort atsMasterPort;
+SMMUATSResponsePort  atsSlavePort;
+SMMUATSRequestPort atsMasterPort;

 // in bytes
 const unsigned portWidth;

--
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[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33502 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed MonitorMasterPort and MonitorSlavePort

Change-Id: Ibb605458532ce40b8635d3f62d8831c7032de82e
---
M src/mem/comm_monitor.hh
M src/mem/mem_checker_monitor.hh
2 files changed, 24 insertions(+), 24 deletions(-)



diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh
index 33cf4d8..ec7521a 100644
--- a/src/mem/comm_monitor.hh
+++ b/src/mem/comm_monitor.hh
@@ -112,17 +112,17 @@
 };

 /**
- * This is the master port of the communication monitor. All recv
+ * This is the request port of the communication monitor. All recv
  * functions call a function in CommMonitor, where the
- * send function of the slave port is called. Besides this, these
+ * send function of the response port is called. Besides this, these
  * functions can also perform actions for capturing statistics.
  */
-class MonitorMasterPort : public RequestPort
+class MonitorRequestPort : public RequestPort
 {

   public:

-MonitorMasterPort(const std::string& _name, CommMonitor& _mon)
+MonitorRequestPort(const std::string& _name, CommMonitor& _mon)
 : RequestPort(_name, &_mon), mon(_mon)
 { }

@@ -174,21 +174,21 @@

 };

-/** Instance of master port, facing the memory side */
-MonitorMasterPort masterPort;
+/** Instance of request port, facing the memory side */
+MonitorRequestPort masterPort;

 /**
- * This is the slave port of the communication monitor. All recv
+ * This is the response port of the communication monitor. All recv
  * functions call a function in CommMonitor, where the
- * send function of the master port is called. Besides this, these
+ * send function of the request port is called. Besides this, these
  * functions can also perform actions for capturing statistics.
  */
-class MonitorSlavePort : public ResponsePort
+class MonitorResponsePort : public ResponsePort
 {

   public:

-MonitorSlavePort(const std::string& _name, CommMonitor& _mon)
+MonitorResponsePort(const std::string& _name, CommMonitor& _mon)
 : ResponsePort(_name, &_mon), mon(_mon)
 { }

@@ -235,8 +235,8 @@

 };

-/** Instance of slave port, i.e. on the CPU side */
-MonitorSlavePort slavePort;
+/** Instance of response port, i.e. on the CPU side */
+MonitorResponsePort slavePort;

 void recvFunctional(PacketPtr pkt);

diff --git a/src/mem/mem_checker_monitor.hh b/src/mem/mem_checker_monitor.hh
index c2fb80d..2f1f533 100644
--- a/src/mem/mem_checker_monitor.hh
+++ b/src/mem/mem_checker_monitor.hh
@@ -83,17 +83,17 @@
 };

 /**
- * This is the master port of the communication monitor. All recv
+ * This is the request port of the communication monitor. All recv
  * functions call a function in MemCheckerMonitor, where the
- * send function of the slave port is called. Besides this, these
+ * send function of the response port is called. Besides this, these
  * functions can also perform actions for capturing statistics.
  */
-class MonitorMasterPort : public RequestPort
+class MonitorRequestPort : public RequestPort
 {

   public:

-MonitorMasterPort(const std::string& _name, MemCheckerMonitor&  
_mon)
+MonitorRequestPort(const std::string& _name, MemCheckerMonitor&  
_mon)

 : RequestPort(_name, &_mon), mon(_mon)
 { }

@@ -140,21 +140,21 @@

 };

-/** Instance of master port, facing the memory side */
-MonitorMasterPort masterPort;
+/** Instance of request port, facing the memory side */
+MonitorRequestPort masterPort;

 /**
- * This is the slave port of the communication monitor. All recv
+ * This is the response port of the communication monitor. All recv
  * functions call a function in MemCheckerMonitor, where the
- * send function of the master port is called. Besides this, these
+ * send function of the request port is called. Besides this, these
  * functions can also perform actions for capturing statistics.
  */
-class MonitorSlavePort : public ResponsePort
+class MonitorResponsePort : public ResponsePort
 {

   public:

-MonitorSlavePort(const std::string& _name, MemCheckerMonitor& _mon)
+MonitorResponsePort(const std::string& _name, MemCheckerMonitor&  
_mon)

 : ResponsePort(_name, &_mon), mon(_mon)
 { }

@@ -196,8 +196,8 @@

 };

-/** Instance of slave port, i.e. on the CPU side */
-MonitorSlavePort slavePort;
+/** Instance of response port, i.e. on the CPU side */
+MonitorResponsePort slavePort;

 void recvFunctional(PacketPtr pkt);


--
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[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave termonology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33495 )



Change subject: misc: Master/Slave termonology
..

misc: Master/Slave termonology

Changed IntMasterPort and IntSlavePort

Change-Id: I72dd40f1f08b8d4e41d31bb640e1b9a334f9d007
---
M src/arch/x86/interrupts.hh
M src/dev/x86/i82094aa.hh
M src/dev/x86/intdev.hh
3 files changed, 7 insertions(+), 7 deletions(-)



diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index c1b2565..d0c984e 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -174,8 +174,8 @@
 int initialApicId;

 // Ports for interrupts.
-IntSlavePort intSlavePort;
-IntMasterPort intMasterPort;
+IntResponsePort intSlavePort;
+IntRequestPort intMasterPort;

 // Port for memory mapped register accesses.
 PioPort pioPort;
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index 2c81e27..678a24f 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -82,7 +82,7 @@

 std::vector *> inputs;

-IntMasterPort intMasterPort;
+IntRequestPort intMasterPort;

   public:
 typedef I82094AAParams Params;
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index 815406a..befcb7e 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -53,12 +53,12 @@
 {

 template 
-class IntSlavePort : public SimpleTimingPort
+class IntResponsePort : public SimpleTimingPort
 {
 Device * device;

   public:
-IntSlavePort(const std::string& _name, SimObject* _parent,
+IntResponsePort(const std::string& _name, SimObject* _parent,
  Device* dev) :
 SimpleTimingPort(_name, _parent), device(dev)
 {
@@ -94,7 +94,7 @@
 }

 template 
-class IntMasterPort : public QueuedRequestPort
+class IntRequestPort : public QueuedRequestPort
 {
   private:
 ReqPacketQueue reqQueue;
@@ -113,7 +113,7 @@
 static void defaultOnCompletion(PacketPtr pkt) { delete pkt; }

   public:
-IntMasterPort(const std::string& _name, SimObject* _parent,
+IntRequestPort(const std::string& _name, SimObject* _parent,
   Device* dev, Tick _latency) :
 QueuedRequestPort(_name, _parent, reqQueue, snoopRespQueue),
 reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),

--
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[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33496 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed SMMUMasterPort and SMMUSlavePort

Change-Id: I913d141d87207e0f416bc951e06ba7a4e778a839
---
M src/dev/arm/smmu_v3.hh
M src/dev/arm/smmu_v3_ports.cc
M src/dev/arm/smmu_v3_ports.hh
M src/dev/arm/smmu_v3_slaveifc.cc
M src/dev/arm/smmu_v3_slaveifc.hh
5 files changed, 17 insertions(+), 17 deletions(-)



diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh
index 8f35cdf..a1295a6 100644
--- a/src/dev/arm/smmu_v3.hh
+++ b/src/dev/arm/smmu_v3.hh
@@ -90,7 +90,7 @@
 const System &system;
 const MasterID masterId;

-SMMUMasterPortmasterPort;
+SMMURequestPortmasterPort;
 SMMUMasterTableWalkPort masterTableWalkPort;
 SMMUControlPort   controlPort;

diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc
index e950f56..b6d5970 100644
--- a/src/dev/arm/smmu_v3_ports.cc
+++ b/src/dev/arm/smmu_v3_ports.cc
@@ -41,19 +41,19 @@
 #include "dev/arm/smmu_v3.hh"
 #include "dev/arm/smmu_v3_slaveifc.hh"

-SMMUMasterPort::SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu) :
+SMMURequestPort::SMMURequestPort(const std::string &_name, SMMUv3 &_smmu) :
 RequestPort(_name, &_smmu),
 smmu(_smmu)
 {}

 bool
-SMMUMasterPort::recvTimingResp(PacketPtr pkt)
+SMMURequestPort::recvTimingResp(PacketPtr pkt)
 {
 return smmu.masterRecvTimingResp(pkt);
 }

 void
-SMMUMasterPort::recvReqRetry()
+SMMURequestPort::recvReqRetry()
 {
 return smmu.masterRecvReqRetry();
 }
@@ -76,7 +76,7 @@
 return smmu.masterTableWalkRecvReqRetry();
 }

-SMMUSlavePort::SMMUSlavePort(const std::string &_name,
+SMMUResponsePort::SMMUResponsePort(const std::string &_name,
  SMMUv3SlaveInterface &_ifc,
  PortID _id)
 :
@@ -86,20 +86,20 @@
 {}

 void
-SMMUSlavePort::recvFunctional(PacketPtr pkt)
+SMMUResponsePort::recvFunctional(PacketPtr pkt)
 {
 if (!respQueue.trySatisfyFunctional(pkt))
 recvAtomic(pkt);
 }

 Tick
-SMMUSlavePort::recvAtomic(PacketPtr pkt)
+SMMUResponsePort::recvAtomic(PacketPtr pkt)
 {
 return ifc.recvAtomic(pkt);
 }

 bool
-SMMUSlavePort::recvTimingReq(PacketPtr pkt)
+SMMUResponsePort::recvTimingReq(PacketPtr pkt)
 {
 return ifc.recvTimingReq(pkt);
 }
diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh
index a8bf84e..15b37aa 100644
--- a/src/dev/arm/smmu_v3_ports.hh
+++ b/src/dev/arm/smmu_v3_ports.hh
@@ -44,7 +44,7 @@
 class SMMUv3;
 class SMMUv3SlaveInterface;

-class SMMUMasterPort : public RequestPort
+class SMMURequestPort : public RequestPort
 {
   protected:
 SMMUv3 &smmu;
@@ -53,8 +53,8 @@
 virtual void recvReqRetry();

   public:
-SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu);
-virtual ~SMMUMasterPort() {}
+SMMURequestPort(const std::string &_name, SMMUv3 &_smmu);
+virtual ~SMMURequestPort() {}
 };

 // Separate master port to send MMU initiated requests on
@@ -71,7 +71,7 @@
 virtual ~SMMUMasterTableWalkPort() {}
 };

-class SMMUSlavePort : public QueuedResponsePort
+class SMMUResponsePort : public QueuedResponsePort
 {
   protected:
 SMMUv3SlaveInterface &ifc;
@@ -82,10 +82,10 @@
 virtual bool recvTimingReq(PacketPtr pkt);

   public:
-SMMUSlavePort(const std::string &_name,
+SMMUResponsePort(const std::string &_name,
   SMMUv3SlaveInterface &_ifc,
   PortID _id = InvalidPortID);
-virtual ~SMMUSlavePort() {}
+virtual ~SMMUResponsePort() {}

 virtual AddrRangeList getAddrRanges() const
 { return AddrRangeList { AddrRange(0, UINT64_MAX) }; }
diff --git a/src/dev/arm/smmu_v3_slaveifc.cc  
b/src/dev/arm/smmu_v3_slaveifc.cc

index 5b3dd98..5d57b5c 100644
--- a/src/dev/arm/smmu_v3_slaveifc.cc
+++ b/src/dev/arm/smmu_v3_slaveifc.cc
@@ -59,7 +59,7 @@
 mainTLBSem(p->tlb_slots),
 microTLBLat(p->utlb_lat),
 mainTLBLat(p->tlb_lat),
-slavePort(new SMMUSlavePort(csprintf("%s.slave", name()), *this)),
+slavePort(new SMMUResponsePort(csprintf("%s.slave", name()), *this)),
 atsSlavePort(name() + ".atsSlave", *this),
 atsMasterPort(name() + ".atsMaster", *this),
 portWidth(p->port_width),
diff --git a/src/dev/arm/smmu_v3_slaveifc.hh  
b/src/dev/arm/smmu_v3_slaveifc.hh

index e1f8ef2..4aa2608 100644
--- a/src/dev/arm/smmu_v3_slaveifc.hh
+++ b/src/dev/arm/smmu_v3_slaveifc.hh
@@ -50,7 +50,7 @@

 class SMMUTranslationProcess;
 class SMMUv3;
-class SMMUSlavePort;
+class SMMUResponsePort;

 class SMMUv3SlaveInterface : public ClockedObject
 {
@@ -72,7 +72,7 @@
 const Cycles microTLBLat;
 const Cycles mainTLBLat;

-SMMUSlavePort *slavePort;
+SMMUResponsePort *slavePort;
 SMMUATSSlavePort  atsSlavePort;
 SMMUATSMasterPort atsMasterPort;


--
To view, visit https://gem5-revie

[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33498 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed TokenMasterPort and TokenSlavePort

Change-Id: Ib78b4bbdf5872bff7aa73bbe219636ea2bb5fcd4
---
M src/gpu-compute/compute_unit.hh
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/token_port.cc
M src/mem/token_port.hh
4 files changed, 23 insertions(+), 23 deletions(-)



diff --git a/src/gpu-compute/compute_unit.hh  
b/src/gpu-compute/compute_unit.hh

index 211dd53..f8947f1 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -628,12 +628,12 @@

 void exitCallback();

-class GMTokenPort : public TokenMasterPort
+class GMTokenPort : public TokenRequestPort
 {
   public:
 GMTokenPort(const std::string& name, SimObject *owner,
 PortID id = InvalidPortID)
-: TokenMasterPort(name, owner, id)
+: TokenRequestPort(name, owner, id)
 { }
 ~GMTokenPort() { }

diff --git a/src/mem/ruby/system/GPUCoalescer.hh  
b/src/mem/ruby/system/GPUCoalescer.hh

index 401f70b..0aee3ca 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -201,12 +201,12 @@
 class GPUCoalescer : public RubyPort
 {
   public:
-class GMTokenPort : public TokenSlavePort
+class GMTokenPort : public TokenResponsePort
 {
   public:
 GMTokenPort(const std::string& name, ClockedObject *owner,
 PortID id = InvalidPortID)
-: TokenSlavePort(name, owner, id)
+: TokenResponsePort(name, owner, id)
 { }
 ~GMTokenPort() { }

diff --git a/src/mem/token_port.cc b/src/mem/token_port.cc
index 5a2462a..dd5dc06 100644
--- a/src/mem/token_port.cc
+++ b/src/mem/token_port.cc
@@ -40,13 +40,13 @@
 #include "debug/TokenPort.hh"

 void
-TokenMasterPort::bind(Port &peer)
+TokenRequestPort::bind(Port &peer)
 {
 RequestPort::bind(peer);
 }

 void
-TokenMasterPort::recvTokens(int num_tokens)
+TokenRequestPort::recvTokens(int num_tokens)
 {
 panic_if(!tokenManager, "TokenManager not set for %s.\n", name());

@@ -54,7 +54,7 @@
 }

 bool
-TokenMasterPort::haveTokens(int num_tokens)
+TokenRequestPort::haveTokens(int num_tokens)
 {
 panic_if(!tokenManager, "TokenManager not set for %s.\n", name());

@@ -62,7 +62,7 @@
 }

 void
-TokenMasterPort::acquireTokens(int num_tokens)
+TokenRequestPort::acquireTokens(int num_tokens)
 {
 panic_if(!tokenManager, "TokenManager not set for %s.\n", name());

@@ -70,13 +70,13 @@
 }

 void
-TokenMasterPort::setTokenManager(TokenManager *_tokenManager)
+TokenRequestPort::setTokenManager(TokenManager *_tokenManager)
 {
 tokenManager = _tokenManager;
 }

 void
-TokenSlavePort::sendTokens(int num_tokens)
+TokenResponsePort::sendTokens(int num_tokens)
 {
 fatal_if(!tokenMasterPort, "Tried sendTokens to non-token master!\n");

@@ -85,12 +85,12 @@
 }

 void
-TokenSlavePort::bind(Port& peer)
+TokenResponsePort::bind(Port& peer)
 {
-// TokenSlavePort is allowed to bind to either TokenMasterPort or a
+// TokenResponsePort is allowed to bind to either TokenRequestPort or a
 // RequestPort as fallback. If the type is a RequestPort,  
tokenMasterPort

 // is set to nullptr to indicate tokens should not be exchanged.
-auto *token_master_port = dynamic_cast(&peer);
+auto *token_master_port = dynamic_cast(&peer);
 auto *master_port = dynamic_cast(&peer);
 if (!token_master_port && !master_port) {
 fatal("Attempt to bind port %s to unsupported slave port %s.",
@@ -107,14 +107,14 @@
 }

 void
-TokenSlavePort::unbind()
+TokenResponsePort::unbind()
 {
 ResponsePort::responderUnbind();
 tokenMasterPort = nullptr;
 }

 void
-TokenSlavePort::recvRespRetry()
+TokenResponsePort::recvRespRetry()
 {
 // fallback to QueuedResponsePort-like impl for now
 panic_if(respQueue.empty(),
@@ -129,7 +129,7 @@
 }

 bool
-TokenSlavePort::sendTimingResp(PacketPtr pkt)
+TokenResponsePort::sendTimingResp(PacketPtr pkt)
 {
 bool success = ResponsePort::sendTimingResp(pkt);

diff --git a/src/mem/token_port.hh b/src/mem/token_port.hh
index 358ee03..ddf652a 100644
--- a/src/mem/token_port.hh
+++ b/src/mem/token_port.hh
@@ -38,16 +38,16 @@
 #include "sim/clocked_object.hh"

 class TokenManager;
-class TokenSlavePort;
+class TokenResponsePort;

-class TokenMasterPort : public RequestPort
+class TokenRequestPort : public RequestPort
 {
   private:
 /* Manager to track tokens between this token port pair. */
 TokenManager *tokenManager;

   public:
-TokenMasterPort(const std::string& name, SimObject* owner,
+TokenRequestPort(const std::string& name, SimObject* owner,
 PortID id = InvalidPortID) :
 RequestPort(name, owner, id), tokenManager(nullptr)
 { }
@@ -87,21 +87,

[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33499 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

CHanged MapperMasterPort and MapperSlavePort

Change-Id: Ic03240faf7f3be5bc3dcc3fae55acf314cc81d18
---
M src/mem/addr_mapper.hh
1 file changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/mem/addr_mapper.hh b/src/mem/addr_mapper.hh
index 5e680a8..add3a63 100644
--- a/src/mem/addr_mapper.hh
+++ b/src/mem/addr_mapper.hh
@@ -98,12 +98,12 @@

 };

-class MapperMasterPort : public RequestPort
+class MapperRequestPort : public RequestPort
 {

   public:

-MapperMasterPort(const std::string& _name, AddrMapper& _mapper)
+MapperRequestPort(const std::string& _name, AddrMapper& _mapper)
 : RequestPort(_name, &_mapper), mapper(_mapper)
 { }

@@ -151,14 +151,14 @@
 };

 /** Instance of master port, facing the memory side */
-MapperMasterPort masterPort;
+MapperRequestPort masterPort;

-class MapperSlavePort : public ResponsePort
+class MapperResponsePort : public ResponsePort
 {

   public:

-MapperSlavePort(const std::string& _name, AddrMapper& _mapper)
+MapperResponsePort(const std::string& _name, AddrMapper& _mapper)
 : ResponsePort(_name, &_mapper), mapper(_mapper)
 { }

@@ -201,7 +201,7 @@
 };

 /** Instance of slave port, i.e. on the CPU side */
-MapperSlavePort slavePort;
+MapperResponsePort slavePort;

 void recvFunctional(PacketPtr pkt);


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33499
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic03240faf7f3be5bc3dcc3fae55acf314cc81d18
Gerrit-Change-Number: 33499
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33503 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed SerialLinkMasterPort and SerialLinkSlavePort

Change-Id: I143c65bbaf4a7a9395938f9d3aedebbeeeaa2e19
---
M src/mem/serial_link.cc
M src/mem/serial_link.hh
2 files changed, 42 insertions(+), 40 deletions(-)



diff --git a/src/mem/serial_link.cc b/src/mem/serial_link.cc
index d05328e..4b05336 100644
--- a/src/mem/serial_link.cc
+++ b/src/mem/serial_link.cc
@@ -51,9 +51,10 @@
 #include "debug/SerialLink.hh"
 #include "params/SerialLink.hh"

-SerialLink::SerialLinkSlavePort::SerialLinkSlavePort(const std::string&  
_name,

+SerialLink::SerialLinkResponsePort::
+SerialLinkResponsePort(const std::string& _name,
  SerialLink& _serial_link,
- SerialLinkMasterPort& _masterPort,
+ SerialLinkRequestPort&  
_masterPort,

  Cycles _delay, int _resp_limit,
  const std::vector&
  _ranges)
@@ -66,9 +67,9 @@
 {
 }

-SerialLink::SerialLinkMasterPort::SerialLinkMasterPort(const std::string&
+SerialLink::SerialLinkRequestPort::SerialLinkRequestPort(const std::string&
_name, SerialLink& _serial_link,
-   SerialLinkSlavePort& _slavePort,
+   SerialLinkResponsePort&  
_slavePort,

Cycles _delay, int _req_limit)
 : RequestPort(_name, &_serial_link), serial_link(_serial_link),
   slavePort(_slavePort), delay(_delay), reqQueueLimit(_req_limit),
@@ -112,19 +113,19 @@
 }

 bool
-SerialLink::SerialLinkSlavePort::respQueueFull() const
+SerialLink::SerialLinkResponsePort::respQueueFull() const
 {
 return outstandingResponses == respQueueLimit;
 }

 bool
-SerialLink::SerialLinkMasterPort::reqQueueFull() const
+SerialLink::SerialLinkRequestPort::reqQueueFull() const
 {
 return transmitList.size() == reqQueueLimit;
 }

 bool
-SerialLink::SerialLinkMasterPort::recvTimingResp(PacketPtr pkt)
+SerialLink::SerialLinkRequestPort::recvTimingResp(PacketPtr pkt)
 {
 // all checks are done when the request is accepted on the slave
 // side, so we are guaranteed to have space for the response
@@ -157,7 +158,7 @@
 }

 bool
-SerialLink::SerialLinkSlavePort::recvTimingReq(PacketPtr pkt)
+SerialLink::SerialLinkResponsePort::recvTimingReq(PacketPtr pkt)
 {
 DPRINTF(SerialLink, "recvTimingReq: %s addr 0x%x\n",
 pkt->cmdString(), pkt->getAddr());
@@ -224,7 +225,7 @@
 }

 void
-SerialLink::SerialLinkSlavePort::retryStalledReq()
+SerialLink::SerialLinkResponsePort::retryStalledReq()
 {
 if (retryReq) {
 DPRINTF(SerialLink, "Request waiting for retry, now retrying\n");
@@ -234,7 +235,7 @@
 }

 void
-SerialLink::SerialLinkMasterPort::schedTimingReq(PacketPtr pkt, Tick when)
+SerialLink::SerialLinkRequestPort::schedTimingReq(PacketPtr pkt, Tick when)
 {
 // If we're about to put this packet at the head of the queue, we
 // need to schedule an event to do the transmit.  Otherwise there
@@ -251,7 +252,7 @@


 void
-SerialLink::SerialLinkSlavePort::schedTimingResp(PacketPtr pkt, Tick when)
+SerialLink::SerialLinkResponsePort::schedTimingResp(PacketPtr pkt, Tick  
when)

 {
 // If we're about to put this packet at the head of the queue, we
 // need to schedule an event to do the transmit.  Otherwise there
@@ -265,7 +266,7 @@
 }

 void
-SerialLink::SerialLinkMasterPort::trySendTiming()
+SerialLink::SerialLinkRequestPort::trySendTiming()
 {
 assert(!transmitList.empty());

@@ -308,7 +309,7 @@
 }

 void
-SerialLink::SerialLinkSlavePort::trySendTiming()
+SerialLink::SerialLinkResponsePort::trySendTiming()
 {
 assert(!transmitList.empty());

@@ -356,25 +357,25 @@
 }

 void
-SerialLink::SerialLinkMasterPort::recvReqRetry()
+SerialLink::SerialLinkRequestPort::recvReqRetry()
 {
 trySendTiming();
 }

 void
-SerialLink::SerialLinkSlavePort::recvRespRetry()
+SerialLink::SerialLinkResponsePort::recvRespRetry()
 {
 trySendTiming();
 }

 Tick
-SerialLink::SerialLinkSlavePort::recvAtomic(PacketPtr pkt)
+SerialLink::SerialLinkResponsePort::recvAtomic(PacketPtr pkt)
 {
 return delay * serial_link.clockPeriod() + masterPort.sendAtomic(pkt);
 }

 void
-SerialLink::SerialLinkSlavePort::recvFunctional(PacketPtr pkt)
+SerialLink::SerialLinkResponsePort::recvFunctional(PacketPtr pkt)
 {
 pkt->pushLabel(name());

@@ -398,7 +399,7 @@
 }

 bool
-SerialLink::SerialLinkMasterPort::trySatisfyFunctional(PacketPtr pkt)
+SerialLink::SerialLinkRequestPort::trySatisfyFunctional(PacketPtr pkt)
 {
 bool found = false;
 auto i = transm

[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33500 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed BridgeMasterPort and BridgeSlavePort

Change-Id: I86dbddad48e981f0dac89a92ea8a8223917bb244
---
M src/mem/bridge.cc
M src/mem/bridge.hh
M src/systemc/tlm_bridge/gem5_to_tlm.hh
M src/systemc/tlm_bridge/tlm_to_gem5.hh
4 files changed, 40 insertions(+), 40 deletions(-)



diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 3cf61f5..d90c5dd 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -50,9 +50,9 @@
 #include "debug/Bridge.hh"
 #include "params/Bridge.hh"

-Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
+Bridge::BridgeResponsePort::BridgeResponsePort(const std::string& _name,
  Bridge& _bridge,
- BridgeMasterPort& _masterPort,
+ BridgeRequestPort& _masterPort,
  Cycles _delay, int _resp_limit,
  std::vector _ranges)
 : ResponsePort(_name, &_bridge), bridge(_bridge),  
masterPort(_masterPort),

@@ -62,9 +62,9 @@
 {
 }

-Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
+Bridge::BridgeRequestPort::BridgeRequestPort(const std::string& _name,
Bridge& _bridge,
-   BridgeSlavePort& _slavePort,
+   BridgeResponsePort& _slavePort,
Cycles _delay, int _req_limit)
 : RequestPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
   delay(_delay), reqQueueLimit(_req_limit),
@@ -105,19 +105,19 @@
 }

 bool
-Bridge::BridgeSlavePort::respQueueFull() const
+Bridge::BridgeResponsePort::respQueueFull() const
 {
 return outstandingResponses == respQueueLimit;
 }

 bool
-Bridge::BridgeMasterPort::reqQueueFull() const
+Bridge::BridgeRequestPort::reqQueueFull() const
 {
 return transmitList.size() == reqQueueLimit;
 }

 bool
-Bridge::BridgeMasterPort::recvTimingResp(PacketPtr pkt)
+Bridge::BridgeRequestPort::recvTimingResp(PacketPtr pkt)
 {
 // all checks are done when the request is accepted on the slave
 // side, so we are guaranteed to have space for the response
@@ -139,7 +139,7 @@
 }

 bool
-Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt)
+Bridge::BridgeResponsePort::recvTimingReq(PacketPtr pkt)
 {
 DPRINTF(Bridge, "recvTimingReq: %s addr 0x%x\n",
 pkt->cmdString(), pkt->getAddr());
@@ -199,7 +199,7 @@
 }

 void
-Bridge::BridgeSlavePort::retryStalledReq()
+Bridge::BridgeResponsePort::retryStalledReq()
 {
 if (retryReq) {
 DPRINTF(Bridge, "Request waiting for retry, now retrying\n");
@@ -209,7 +209,7 @@
 }

 void
-Bridge::BridgeMasterPort::schedTimingReq(PacketPtr pkt, Tick when)
+Bridge::BridgeRequestPort::schedTimingReq(PacketPtr pkt, Tick when)
 {
 // If we're about to put this packet at the head of the queue, we
 // need to schedule an event to do the transmit.  Otherwise there
@@ -226,7 +226,7 @@


 void
-Bridge::BridgeSlavePort::schedTimingResp(PacketPtr pkt, Tick when)
+Bridge::BridgeResponsePort::schedTimingResp(PacketPtr pkt, Tick when)
 {
 // If we're about to put this packet at the head of the queue, we
 // need to schedule an event to do the transmit.  Otherwise there
@@ -240,7 +240,7 @@
 }

 void
-Bridge::BridgeMasterPort::trySendTiming()
+Bridge::BridgeRequestPort::trySendTiming()
 {
 assert(!transmitList.empty());

@@ -278,7 +278,7 @@
 }

 void
-Bridge::BridgeSlavePort::trySendTiming()
+Bridge::BridgeResponsePort::trySendTiming()
 {
 assert(!transmitList.empty());

@@ -322,19 +322,19 @@
 }

 void
-Bridge::BridgeMasterPort::recvReqRetry()
+Bridge::BridgeRequestPort::recvReqRetry()
 {
 trySendTiming();
 }

 void
-Bridge::BridgeSlavePort::recvRespRetry()
+Bridge::BridgeResponsePort::recvRespRetry()
 {
 trySendTiming();
 }

 Tick
-Bridge::BridgeSlavePort::recvAtomic(PacketPtr pkt)
+Bridge::BridgeResponsePort::recvAtomic(PacketPtr pkt)
 {
 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
  "is responding");
@@ -343,7 +343,7 @@
 }

 void
-Bridge::BridgeSlavePort::recvFunctional(PacketPtr pkt)
+Bridge::BridgeResponsePort::recvFunctional(PacketPtr pkt)
 {
 pkt->pushLabel(name());

@@ -367,7 +367,7 @@
 }

 bool
-Bridge::BridgeMasterPort::trySatisfyFunctional(PacketPtr pkt)
+Bridge::BridgeRequestPort::trySatisfyFunctional(PacketPtr pkt)
 {
 bool found = false;
 auto i = transmitList.begin();
@@ -384,7 +384,7 @@
 }

 AddrRangeList
-Bridge::BridgeSlavePort::getAddrRanges() const
+Bridge::BridgeResponsePort::getAddrRanges() const
 {
 return ranges;
 }
diff --git a/src/mem/bridge.hh b/src/

[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33501 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed CoherentXBarPorts and NonCoherentXBarPorts

Change-Id: I73dce1093e4051e98d1406ef4f52ac3f9aad49e0
---
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
M src/mem/noncoherent_xbar.cc
M src/mem/noncoherent_xbar.hh
4 files changed, 19 insertions(+), 18 deletions(-)



diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index e64df9e..12c395e 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -68,7 +68,7 @@
 // are enumerated starting from zero
 for (int i = 0; i < p->port_master_connection_count; ++i) {
 std::string portName = csprintf("%s.master[%d]", name(), i);
-RequestPort* bp = new CoherentXBarMasterPort(portName, *this, i);
+RequestPort* bp = new CoherentXBarRequestPort(portName, *this, i);
 masterPorts.push_back(bp);
 reqLayers.push_back(new ReqLayer(*bp, *this,
  csprintf("reqLayer%d", i)));
@@ -81,7 +81,7 @@
 if (p->port_default_connection_count) {
 defaultPortID = masterPorts.size();
 std::string portName = name() + ".default";
-RequestPort* bp = new CoherentXBarMasterPort(portName, *this,
+RequestPort* bp = new CoherentXBarRequestPort(portName, *this,
 defaultPortID);
 masterPorts.push_back(bp);
 reqLayers.push_back(new ReqLayer(*bp, *this, csprintf("reqLayer%d",
@@ -94,7 +94,8 @@
 // create the slave ports, once again starting at zero
 for (int i = 0; i < p->port_slave_connection_count; ++i) {
 std::string portName = csprintf("%s.slave[%d]", name(), i);
-QueuedResponsePort* bp = new CoherentXBarSlavePort(portName,  
*this, i);

+QueuedResponsePort* bp =
+new CoherentXBarResponsePort(portName, *this, i);
 slavePorts.push_back(bp);
 respLayers.push_back(new RespLayer(*bp, *this,
csprintf("respLayer%d", i)));
diff --git a/src/mem/coherent_xbar.hh b/src/mem/coherent_xbar.hh
index 09d81ca..977d65d 100644
--- a/src/mem/coherent_xbar.hh
+++ b/src/mem/coherent_xbar.hh
@@ -82,7 +82,7 @@
  * be instantiated for each of the master ports connecting to the
  * crossbar.
  */
-class CoherentXBarSlavePort : public QueuedResponsePort
+class CoherentXBarResponsePort : public QueuedResponsePort
 {

   private:
@@ -95,7 +95,7 @@

   public:

-CoherentXBarSlavePort(const std::string &_name,
+CoherentXBarResponsePort(const std::string &_name,
  CoherentXBar &_xbar, PortID _id)
 : QueuedResponsePort(_name, &_xbar, queue, _id), xbar(_xbar),
   queue(_xbar, *this)
@@ -146,7 +146,7 @@
  * instantiated for each of the slave interfaces connecting to the
  * crossbar.
  */
-class CoherentXBarMasterPort : public RequestPort
+class CoherentXBarRequestPort : public RequestPort
 {
   private:
 /** A reference to the crossbar to which this port belongs. */
@@ -154,7 +154,7 @@

   public:

-CoherentXBarMasterPort(const std::string &_name,
+CoherentXBarRequestPort(const std::string &_name,
   CoherentXBar &_xbar, PortID _id)
 : RequestPort(_name, &_xbar, _id), xbar(_xbar)
 { }
diff --git a/src/mem/noncoherent_xbar.cc b/src/mem/noncoherent_xbar.cc
index 8ec668a..3d070d7 100644
--- a/src/mem/noncoherent_xbar.cc
+++ b/src/mem/noncoherent_xbar.cc
@@ -58,7 +58,7 @@
 // are enumerated starting from zero
 for (int i = 0; i < p->port_master_connection_count; ++i) {
 std::string portName = csprintf("%s.master[%d]", name(), i);
-RequestPort* bp = new NoncoherentXBarMasterPort(portName, *this,  
i);
+RequestPort* bp = new NoncoherentXBarRequestPort(portName, *this,  
i);

 masterPorts.push_back(bp);
 reqLayers.push_back(new ReqLayer(*bp, *this,
  csprintf("reqLayer%d", i)));
@@ -69,7 +69,7 @@
 if (p->port_default_connection_count) {
 defaultPortID = masterPorts.size();
 std::string portName = name() + ".default";
-RequestPort* bp = new NoncoherentXBarMasterPort(portName, *this,
+RequestPort* bp = new NoncoherentXBarRequestPort(portName, *this,
   defaultPortID);
 masterPorts.push_back(bp);
 reqLayers.push_back(new ReqLayer(*bp, *this, csprintf("reqLayer%d",
@@ -80,7 +80,7 @@
 for (int i = 0; i < p->port_slave_connection_count; ++i) {
 std::string portName = csprintf("%s.slave[%d]", name(), i);
 QueuedResponsePort* bp =
- new Nonco

[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33494 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed QueuedMasterPort and QueuedSlavePort

Change-Id: I7d84d0df3d0003a3447c7118abcbba43443b3b23
---
M src/dev/arm/smmu_v3_ports.cc
M src/dev/arm/smmu_v3_ports.hh
M src/dev/x86/intdev.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
M src/mem/mem_delay.cc
M src/mem/mem_delay.hh
M src/mem/noncoherent_xbar.cc
M src/mem/noncoherent_xbar.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/qport.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/snoop_filter.hh
M src/mem/token_port.cc
M src/mem/tport.cc
M src/mem/tport.hh
M src/mem/xbar.hh
23 files changed, 58 insertions(+), 55 deletions(-)



diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc
index 3f54250..e950f56 100644
--- a/src/dev/arm/smmu_v3_ports.cc
+++ b/src/dev/arm/smmu_v3_ports.cc
@@ -80,7 +80,7 @@
  SMMUv3SlaveInterface &_ifc,
  PortID _id)
 :
-QueuedSlavePort(_name, &_ifc, respQueue, _id),
+QueuedResponsePort(_name, &_ifc, respQueue, _id),
 ifc(_ifc),
 respQueue(_ifc, *this)
 {}
@@ -138,7 +138,7 @@

 SMMUATSMasterPort::SMMUATSMasterPort(const std::string &_name,
  SMMUv3SlaveInterface &_ifc) :
-QueuedMasterPort(_name, &_ifc, reqQueue, snoopRespQueue),
+QueuedRequestPort(_name, &_ifc, reqQueue, snoopRespQueue),
 ifc(_ifc),
 reqQueue(_ifc, *this),
 snoopRespQueue(_ifc, *this)
@@ -152,7 +152,7 @@

 SMMUATSSlavePort::SMMUATSSlavePort(const std::string &_name,
SMMUv3SlaveInterface &_ifc) :
-QueuedSlavePort(_name, &_ifc, respQueue),
+QueuedResponsePort(_name, &_ifc, respQueue),
 ifc(_ifc),
 respQueue(_ifc, *this)
 {}
diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh
index ee68bbb..a8bf84e 100644
--- a/src/dev/arm/smmu_v3_ports.hh
+++ b/src/dev/arm/smmu_v3_ports.hh
@@ -71,7 +71,7 @@
 virtual ~SMMUMasterTableWalkPort() {}
 };

-class SMMUSlavePort : public QueuedSlavePort
+class SMMUSlavePort : public QueuedResponsePort
 {
   protected:
 SMMUv3SlaveInterface &ifc;
@@ -106,7 +106,7 @@
 virtual ~SMMUControlPort() {}
 };

-class SMMUATSMasterPort : public QueuedMasterPort
+class SMMUATSMasterPort : public QueuedRequestPort
 {
   protected:
 SMMUv3SlaveInterface &ifc;
@@ -120,7 +120,7 @@
 virtual ~SMMUATSMasterPort() {}
 };

-class SMMUATSSlavePort : public QueuedSlavePort
+class SMMUATSSlavePort : public QueuedResponsePort
 {
   protected:
 SMMUv3SlaveInterface &ifc;
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index a681a2e..815406a 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -94,7 +94,7 @@
 }

 template 
-class IntMasterPort : public QueuedMasterPort
+class IntMasterPort : public QueuedRequestPort
 {
   private:
 ReqPacketQueue reqQueue;
@@ -115,7 +115,7 @@
   public:
 IntMasterPort(const std::string& _name, SimObject* _parent,
   Device* dev, Tick _latency) :
-QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
+QueuedRequestPort(_name, _parent, reqQueue, snoopRespQueue),
 reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
 device(dev), latency(_latency)
 {
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 0187703..71eab09 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -66,7 +66,7 @@
 BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
   BaseCache *_cache,
   const std::string &_label)
-: QueuedSlavePort(_name, _cache, queue),
+: QueuedResponsePort(_name, _cache, queue),
   queue(*_cache, *this, true, _label),
   blocked(false), mustSendRetry(false),
   sendRetryEvent([this]{ processSendRetry(); }, _name)
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index c129661..176a7e5 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -119,7 +119,7 @@
  * and the sendDeferredPacket of the timing port is modified to
  * consider both the transmit list and the requests from the MSHR.
  */
-class CacheMasterPort : public QueuedMasterPort
+class CacheMasterPort : public QueuedRequestPort
 {

   public:
@@ -139,7 +139,7 @@
 CacheMasterPort(const std::string &_name, BaseCache *_cache,
 ReqPacketQueue &_reqQueue,
 SnoopRespPacketQueue &_snoopRespQueue) :
-QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
+QueuedRequestPort

[gem5-dev] Change in gem5/gem5[develop]: dev: MasterID to UniqueID

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33509 )



Change subject: dev: MasterID to UniqueID
..

dev: MasterID to UniqueID

Change-Id: Ia56ad2b1d99f3ebb6d94b8da7dd306b61e4482a6
---
M src/dev/arm/amba.hh
M src/dev/arm/smmu_v3.hh
M src/dev/dma_device.hh
3 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/dev/arm/amba.hh b/src/dev/arm/amba.hh
index 4bfba34..f275c0f 100644
--- a/src/dev/arm/amba.hh
+++ b/src/dev/arm/amba.hh
@@ -43,7 +43,7 @@
 namespace AMBA
 {

-typedef MasterID OrderID;
+typedef UniqueID OrderID;

 static OrderID
 orderId(PacketPtr pkt)
diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh
index a1295a6..1b4280e 100644
--- a/src/dev/arm/smmu_v3.hh
+++ b/src/dev/arm/smmu_v3.hh
@@ -88,7 +88,7 @@
 friend class SMMUv3SlaveInterface;

 const System &system;
-const MasterID masterId;
+const UniqueID masterId;

 SMMURequestPortmasterPort;
 SMMUMasterTableWalkPort masterTableWalkPort;
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 56c8d4c..cca0f24 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -114,7 +114,7 @@
 System *const sys;

 /** Id for all requests */
-const MasterID masterId;
+const UniqueID masterId;

   protected:
 /** Use a deque as we never do any insertion or removal in the middle  
*/


--
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Gerrit-Change-Id: Ia56ad2b1d99f3ebb6d94b8da7dd306b61e4482a6
Gerrit-Change-Number: 33509
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33506 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed PioMasterPort and PioSlavePort

Change-Id: I8530e2271db14fe4b3f2bf0dfbc795e4fc2c135a
---
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
2 files changed, 15 insertions(+), 15 deletions(-)



diff --git a/src/mem/ruby/system/RubyPort.cc  
b/src/mem/ruby/system/RubyPort.cc

index 8c399b8..56c0d9b 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -76,7 +76,7 @@

 // create the master ports based on the number of connected ports
 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
-master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
+master_ports.push_back(new PioRequestPort(csprintf("%s.master%d",
 name(), i), this));
 }
 }
@@ -121,7 +121,7 @@
 return ClockedObject::getPort(if_name, idx);
 }

-RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
+RubyPort::PioRequestPort::PioRequestPort(const std::string &_name,
RubyPort *_port)
 : QueuedRequestPort(_name, _port, reqQueue, snoopRespQueue),
   reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
@@ -129,7 +129,7 @@
 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
 }

-RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
+RubyPort::PioResponsePort::PioResponsePort(const std::string &_name,
RubyPort *_port)
 : QueuedResponsePort(_name, _port, queue), queue(*_port, *this)
 {
@@ -156,7 +156,7 @@
 }

 bool
-RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
+RubyPort::PioRequestPort::recvTimingResp(PacketPtr pkt)
 {
 RubyPort *rp = static_cast(&owner);
 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
@@ -192,7 +192,7 @@
 }

 bool
-RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
+RubyPort::PioResponsePort::recvTimingReq(PacketPtr pkt)
 {
 RubyPort *ruby_port = static_cast(&owner);

@@ -213,7 +213,7 @@
 }

 Tick
-RubyPort::PioSlavePort::recvAtomic(PacketPtr pkt)
+RubyPort::PioResponsePort::recvAtomic(PacketPtr pkt)
 {
 RubyPort *ruby_port = static_cast(&owner);
 // Only atomic_noncaching mode supported!
@@ -584,7 +584,7 @@
 }

 AddrRangeList
-RubyPort::PioSlavePort::getAddrRanges() const
+RubyPort::PioResponsePort::getAddrRanges() const
 {
 // at the moment the assumption is that the master does not care
 AddrRangeList ranges;
@@ -631,7 +631,7 @@
 }

 void
-RubyPort::PioMasterPort::recvRangeChange()
+RubyPort::PioRequestPort::recvRangeChange()
 {
 RubyPort &r = static_cast(owner);
 r.gotAddrRanges--;
diff --git a/src/mem/ruby/system/RubyPort.hh  
b/src/mem/ruby/system/RubyPort.hh

index 40f148c..9e87c0c 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -102,27 +102,27 @@
 bool isPhysMemAddress(PacketPtr pkt) const;
 };

-class PioMasterPort : public QueuedRequestPort
+class PioRequestPort : public QueuedRequestPort
 {
   private:
 ReqPacketQueue reqQueue;
 SnoopRespPacketQueue snoopRespQueue;

   public:
-PioMasterPort(const std::string &_name, RubyPort *_port);
+PioRequestPort(const std::string &_name, RubyPort *_port);

   protected:
 bool recvTimingResp(PacketPtr pkt);
 void recvRangeChange();
 };

-class PioSlavePort : public QueuedResponsePort
+class PioResponsePort : public QueuedResponsePort
 {
   private:
 RespPacketQueue queue;

   public:
-PioSlavePort(const std::string &_name, RubyPort *_port);
+PioResponsePort(const std::string &_name, RubyPort *_port);

   protected:
 bool recvTimingReq(PacketPtr pkt);
@@ -205,15 +205,15 @@
 retryList.push_back(port);
 }

-PioMasterPort pioMasterPort;
-PioSlavePort pioSlavePort;
+PioRequestPort pioMasterPort;
+PioResponsePort pioSlavePort;
 MemRequestPort memMasterPort;
 MemResponsePort memSlavePort;
 unsigned int gotAddrRanges;

 /** Vector of M5 Ports attached to this Ruby port. */
 typedef std::vector::iterator CpuPortIter;
-std::vector master_ports;
+std::vector master_ports;

 //
 // Based on similar code in the M5 bus.  Stores pointers to those ports

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8530e2271db14fe4b3f2bf0dfbc795e4fc2c135a
Gerrit-Change-Number: 33506
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi 
Gerrit-MessageType: newchange
___
gem5-dev mailing

[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33505 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed MemMasterPort and MemSlavePort

Change-Id: I589906af48e44dc5a831350413d521a4dd7606f2
---
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/VIPERCoalescer.cc
5 files changed, 35 insertions(+), 33 deletions(-)



diff --git a/src/mem/ruby/system/GPUCoalescer.cc  
b/src/mem/ruby/system/GPUCoalescer.cc

index 80bc19a..b2a6801 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -669,7 +669,7 @@
 // back the requesting CU when we receive write
 // complete callbacks for all issued Ruby requests of this
 // instruction.
-RubyPort::MemSlavePort* mem_slave_port = ss->port;
+RubyPort::MemResponsePort* mem_slave_port = ss->port;

 GPUDynInstPtr gpuDynInst = nullptr;

@@ -783,7 +783,7 @@
 for (auto& pkt : mylist) {
 RubyPort::SenderState *ss =
 safe_cast(pkt->senderState);
-MemSlavePort *port = ss->port;
+MemResponsePort *port = ss->port;
 assert(port != NULL);

 pkt->senderState = ss->predecessor;
diff --git a/src/mem/ruby/system/GPUCoalescer.hh  
b/src/mem/ruby/system/GPUCoalescer.hh

index 0aee3ca..16323a7 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -135,7 +135,7 @@
 {}

 void
-addPendingReq(RubyPort::MemSlavePort* port, GPUDynInstPtr inst,
+addPendingReq(RubyPort::MemResponsePort* port, GPUDynInstPtr inst,
   bool usingRubyTester)
 {
 assert(port);
@@ -192,7 +192,7 @@
 // which implies multiple ports per instruction. However, we need
 // only 1 of the ports to call back the CU. Therefore, here we keep
 // track the port that sent the first packet of this instruction.
-RubyPort::MemSlavePort* originalPort;
+RubyPort::MemResponsePort* originalPort;
 // similar to the originalPort, this gpuDynInstPtr is set only for
 // the first packet of this instruction.
 GPUDynInstPtr gpuDynInstPtr;
diff --git a/src/mem/ruby/system/RubyPort.cc  
b/src/mem/ruby/system/RubyPort.cc

index 43259eb..8c399b8 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -68,7 +68,8 @@

 // create the slave ports based on the number of connected ports
 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
-slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d",  
name(),

+slave_ports.push_back
+(new MemResponsePort(csprintf("%s.slave%d", name(),
 i), this, p->ruby_system->getAccessBackingStore(),
 i, p->no_retry_on_stall));
 }
@@ -135,7 +136,7 @@
 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
 }

-RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
+RubyPort::MemRequestPort::MemRequestPort(const std::string &_name,
RubyPort *_port)
 : QueuedRequestPort(_name, _port, reqQueue, snoopRespQueue),
   reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
@@ -143,7 +144,8 @@
 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n",  
_name);

 }

-RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort  
*_port,

+RubyPort::
+MemResponsePort::MemResponsePort(const std::string &_name, RubyPort *_port,
  bool _access_backing_store, PortID id,
  bool _no_retry_on_stall)
 : QueuedResponsePort(_name, _port, queue, id), queue(*_port, *this),
@@ -165,7 +167,7 @@
 return true;
 }

-bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
+bool RubyPort::MemRequestPort::recvTimingResp(PacketPtr pkt)
 {
 // got a response from a device
 assert(pkt->isResponse());
@@ -173,7 +175,7 @@
 // First we must retrieve the request port from the sender State
 RubyPort::SenderState *senderState =
 safe_cast(pkt->popSenderState());
-MemSlavePort *port = senderState->port;
+MemResponsePort *port = senderState->port;
 assert(port != NULL);
 delete senderState;

@@ -231,7 +233,7 @@
 }

 bool
-RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
+RubyPort::MemResponsePort::recvTimingReq(PacketPtr pkt)
 {
 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
 pkt->getAddr(), id);
@@ -302,7 +304,7 @@
 }

 Tick
-RubyPort::MemSlavePort::recvAtomic(PacketPtr pkt)
+RubyPort::MemResponsePort::recvAtomic(PacketPtr pkt)
 {
 RubyPort *ruby_port = static_cast(&owner);
 // Only atomic_noncaching mode supported!
@@ -347,7 +349,7 @@
 }

 void
-RubyP

[gem5-dev] Change in gem5/gem5[develop]: misc: Master/Slave terminology

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33504 )



Change subject: misc: Master/Slave terminology
..

misc: Master/Slave terminology

Changed CacheMasterPort and CacheSlavePort

Change-Id: I64b7449139544dd995e6f6960f1927caecc1e817
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
2 files changed, 16 insertions(+), 16 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 71eab09..be9b699 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -63,7 +63,7 @@

 using namespace std;

-BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
+BaseCache::CacheResponsePort::CacheResponsePort(const std::string &_name,
   BaseCache *_cache,
   const std::string &_label)
 : QueuedResponsePort(_name, _cache, queue),
@@ -129,7 +129,7 @@
 }

 void
-BaseCache::CacheSlavePort::setBlocked()
+BaseCache::CacheResponsePort::setBlocked()
 {
 assert(!blocked);
 DPRINTF(CachePort, "Port is blocking new requests\n");
@@ -144,7 +144,7 @@
 }

 void
-BaseCache::CacheSlavePort::clearBlocked()
+BaseCache::CacheResponsePort::clearBlocked()
 {
 assert(blocked);
 DPRINTF(CachePort, "Port is accepting new requests\n");
@@ -156,7 +156,7 @@
 }

 void
-BaseCache::CacheSlavePort::processSendRetry()
+BaseCache::CacheResponsePort::processSendRetry()
 {
 DPRINTF(CachePort, "Port is sending retry\n");

@@ -2364,7 +2364,7 @@
 BaseCache::
 CpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache,
  const std::string &_label)
-: CacheSlavePort(_name, _cache, _label), cache(_cache)
+: CacheResponsePort(_name, _cache, _label), cache(_cache)
 {
 }

@@ -2451,7 +2451,7 @@
 BaseCache::MemSidePort::MemSidePort(const std::string &_name,
 BaseCache *_cache,
 const std::string &_label)
-: CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
+: CacheRequestPort(_name, _cache, _reqQueue, _snoopRespQueue),
   _reqQueue(*_cache, *this, _snoopRespQueue, _label),
   _snoopRespQueue(*_cache, *this, true, _label), cache(_cache)
 {
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 176a7e5..80797d5 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -111,7 +111,7 @@
   protected:

 /**
- * A cache master port is used for the memory-side port of the
+ * A cache request port is used for the memory-side port of the
  * cache, and in addition to the basic timing port that only sends
  * response packets through a transmit list, it also offers the
  * ability to schedule and send request packets (requests &
@@ -119,7 +119,7 @@
  * and the sendDeferredPacket of the timing port is modified to
  * consider both the transmit list and the requests from the MSHR.
  */
-class CacheMasterPort : public QueuedRequestPort
+class CacheRequestPort : public QueuedRequestPort
 {

   public:
@@ -136,7 +136,7 @@

   protected:

-CacheMasterPort(const std::string &_name, BaseCache *_cache,
+CacheRequestPort(const std::string &_name, BaseCache *_cache,
 ReqPacketQueue &_reqQueue,
 SnoopRespPacketQueue &_snoopRespQueue) :
 QueuedRequestPort(_name, _cache, _reqQueue, _snoopRespQueue)
@@ -202,10 +202,10 @@


 /**
- * The memory-side port extends the base cache master port with
+ * The memory-side port extends the base cache request port with
  * access functions for functional, atomic and timing snoops.
  */
-class MemSidePort : public CacheMasterPort
+class MemSidePort : public CacheRequestPort
 {
   private:

@@ -234,14 +234,14 @@
 };

 /**
- * A cache slave port is used for the CPU-side port of the cache,
+ * A cache response port is used for the CPU-side port of the cache,
  * and it is basically a simple timing port that uses a transmit
  * list for responses to the CPU (or connected master). In
  * addition, it has the functionality to block the port for
  * incoming requests. If blocked, the port will issue a retry once
  * unblocked.
  */
-class CacheSlavePort : public QueuedResponsePort
+class CacheResponsePort : public QueuedResponsePort
 {

   public:
@@ -256,7 +256,7 @@

   protected:

-CacheSlavePort(const std::string &_name, BaseCache *_cache,
+CacheResponsePort(const std::string &_name, BaseCache *_cache,
const std::string &_label);

 /** A normal packet queue used to store responses. */
@@ -275,10 +275,10 @@
 };

 /**
- * The CPU-side port extends the base cache slave port with access
+ * The CPU-side port extends the base cache response port wit

[gem5-dev] Change in gem5/gem5[develop]: systemc: MasterID to UniqueID

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33513 )



Change subject: systemc: MasterID to UniqueID
..

systemc: MasterID to UniqueID

Change-Id: I9b70f221bf93e19b03bc5d33b25496ac926112c0
---
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/tlm_bridge/tlm_to_gem5.hh
2 files changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc  
b/src/systemc/tlm_bridge/tlm_to_gem5.cc

index e6cb483..0a37762 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -67,7 +67,7 @@
 {

 PacketPtr
-payload2packet(MasterID masterId, tlm::tlm_generic_payload &trans)
+payload2packet(UniqueID masterId, tlm::tlm_generic_payload &trans)
 {
 MemCmd cmd;

diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.hh  
b/src/systemc/tlm_bridge/tlm_to_gem5.hh

index 99f75d1..0a8d0c5 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.hh
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.hh
@@ -171,7 +171,7 @@

 void before_end_of_elaboration() override;

-const MasterID masterId;
+const UniqueID masterId;
 };

 } // namespace sc_gem5

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9b70f221bf93e19b03bc5d33b25496ac926112c0
Gerrit-Change-Number: 33513
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: MasterID to UniqueID

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33508 )



Change subject: cpu: MasterID to UniqueID
..

cpu: MasterID to UniqueID

Change-Id: I68d9a896f1ed9892a10ae222341716fb1d8ad467
---
M src/cpu/base.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/o3/lsq.hh
M src/cpu/testers/directedtest/DirectedGenerator.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/testers/traffic_gen/base_gen.cc
M src/cpu/testers/traffic_gen/base_gen.hh
M src/cpu/testers/traffic_gen/dram_gen.cc
M src/cpu/testers/traffic_gen/dram_gen.hh
M src/cpu/testers/traffic_gen/dram_rot_gen.hh
M src/cpu/testers/traffic_gen/exit_gen.hh
M src/cpu/testers/traffic_gen/idle_gen.hh
M src/cpu/testers/traffic_gen/linear_gen.hh
M src/cpu/testers/traffic_gen/random_gen.hh
M src/cpu/testers/traffic_gen/trace_gen.hh
M src/cpu/trace/trace_cpu.hh
20 files changed, 43 insertions(+), 43 deletions(-)



diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 5c0c709..187e759 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -124,10 +124,10 @@
 const uint32_t _socketId;

 /** instruction side request id that must be placed in all requests */
-MasterID _instMasterId;
+UniqueID _instMasterId;

 /** data side request id that must be placed in all requests */
-MasterID _dataMasterId;
+UniqueID _dataMasterId;

 /** An intrenal representation of a task identifier within gem5. This  
is
  * used so the CPU can add which taskId (which is an internal  
representation

@@ -182,9 +182,9 @@
 uint32_t socketId() const { return _socketId; }

 /** Reads this CPU's unique data requestor ID */
-MasterID dataMasterId() const { return _dataMasterId; }
+UniqueID dataMasterId() const { return _dataMasterId; }
 /** Reads this CPU's unique instruction requestor ID */
-MasterID instMasterId() const { return _instMasterId; }
+UniqueID instMasterId() const { return _instMasterId; }

 /**
  * Get a port on this CPU. All CPUs have a data and
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b98cbaa..d53844c 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -441,7 +441,7 @@
 uint32_t socketId() const { return cpu->socketId(); }

 /** Read this CPU's data requestor ID */
-MasterID masterId() const { return cpu->dataMasterId(); }
+UniqueID masterId() const { return cpu->dataMasterId(); }

 /** Read this context's system-wide ID **/
 ContextID contextId() const { return thread->contextId(); }
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3c04064..0598e30 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -89,7 +89,7 @@
 using VecRegContainer = TheISA::VecRegContainer;

 /** id attached to all issued requests */
-MasterID masterId;
+UniqueID masterId;
   public:
 void init() override;

diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 9ef3b0c..b9892f4 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -456,7 +456,7 @@
  */
 void
 setVirt(Addr vaddr, unsigned size, Request::Flags flags_,
-MasterID mid, Addr pc)
+UniqueID mid, Addr pc)
 {
 request()->setVirt(vaddr, size, flags_, mid, pc);
 }
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh  
b/src/cpu/testers/directedtest/DirectedGenerator.hh

index 2d03372..994a276 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.hh
+++ b/src/cpu/testers/directedtest/DirectedGenerator.hh
@@ -49,7 +49,7 @@

   protected:
 int m_num_cpus;
-MasterID masterId;
+UniqueID masterId;
 RubyDirectedTester* m_directed_tester;
 };

diff --git  
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh  
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh

index 524a960..ebd6469 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
@@ -130,7 +130,7 @@

 const Cycles responseLimit;

-MasterID masterId;
+UniqueID masterId;

 void completeRequest(PacketPtr pkt);

diff --git a/src/cpu/testers/memtest/memtest.hh  
b/src/cpu/testers/memtest/memtest.hh

index 86b27a4..a0dd748 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -127,7 +127,7 @@
 const unsigned percentUncacheable;

 /** Request id for all generated traffic */
-MasterID masterId;
+UniqueID masterId;

 unsigned int id;

diff --git a/src/cpu/testers/rubytest/RubyTester.hh  
b/src/cpu/testers/rubytest/RubyTester.hh

index e63729a..2a31ae5 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: MasterID to UniqueID

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33510 )



Change subject: gpu-compute: MasterID to UniqueID
..

gpu-compute: MasterID to UniqueID

Change-Id: I2acc5741dff576d33cb10eb6e624cd3167b3a350
---
M src/gpu-compute/compute_unit.hh
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/gpu-compute/compute_unit.hh  
b/src/gpu-compute/compute_unit.hh

index f8947f1..6d03769 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -458,13 +458,13 @@
 void processFetchReturn(PacketPtr pkt);
 void updatePageDivergenceDist(Addr addr);

-MasterID masterId() { return _masterId; }
+UniqueID masterId() { return _masterId; }

 bool isDone() const;
 bool isVectorAluIdle(uint32_t simdId) const;

   protected:
-MasterID _masterId;
+UniqueID _masterId;

 LdsState &lds;


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2acc5741dff576d33cb10eb6e624cd3167b3a350
Gerrit-Change-Number: 33510
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: MasterID to UniqueID

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33512 )



Change subject: sim: MasterID to UniqueID
..

sim: MasterID to UniqueID

Change-Id: I6fafa29509bf8d83d71d5c26d2c988d3e65fe327
---
M src/sim/probe/mem.hh
M src/sim/system.cc
M src/sim/system.hh
3 files changed, 23 insertions(+), 23 deletions(-)



diff --git a/src/sim/probe/mem.hh b/src/sim/probe/mem.hh
index fed7bcf..e8200c4 100644
--- a/src/sim/probe/mem.hh
+++ b/src/sim/probe/mem.hh
@@ -56,7 +56,7 @@
 uint32_t size;
 Request::FlagsType flags;
 Addr pc;
-MasterID master;
+UniqueID master;

 explicit PacketInfo(const PacketPtr& pkt) :
 cmd(pkt->cmd),
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 8185f13..69fc4d7 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -247,7 +247,7 @@
 warn_once("Cache line size is neither 16, 32, 64 nor 128  
bytes.\n");


 // Get the generic system master IDs
-MasterID tmp_id M5_VAR_USED;
+UniqueID tmp_id M5_VAR_USED;
 tmp_id = getMasterId(this, "writebacks");
 assert(tmp_id == Request::wbMasterId);
 tmp_id = getMasterId(this, "functional");
@@ -420,7 +420,7 @@
 }

 void
-System::addDeviceMemory(MasterID masterId, AbstractMemory *deviceMemory)
+System::addDeviceMemory(UniqueID masterId, AbstractMemory *deviceMemory)
 {
 if (!deviceMemMap.count(masterId)) {
 deviceMemMap.insert(std::make_pair(masterId, deviceMemory));
@@ -430,17 +430,17 @@
 bool
 System::isDeviceMemAddr(PacketPtr pkt) const
 {
-const MasterID& mid = pkt->masterId();
+const UniqueID& mid = pkt->masterId();

 return (deviceMemMap.count(mid) &&
 deviceMemMap.at(mid)->getAddrRange().contains(pkt->getAddr()));
 }

 AbstractMemory *
-System::getDeviceMemory(MasterID mid) const
+System::getDeviceMemory(UniqueID mid) const
 {
 panic_if(!deviceMemMap.count(mid),
- "No device memory found for MasterID %d\n", mid);
+ "No device memory found for UniqueID %d\n", mid);
 return deviceMemMap.at(mid);
 }

@@ -553,10 +553,10 @@
 }
 }

-MasterID
+UniqueID
 System::lookupMasterId(const SimObject* obj) const
 {
-MasterID id = Request::invldMasterId;
+UniqueID id = Request::invldMasterId;

 // number of occurrences of the SimObject pointer
 // in the master list.
@@ -570,13 +570,13 @@
 }

 fatal_if(obj_number > 1,
-"Cannot lookup MasterID by SimObject pointer: "
+"Cannot lookup UniqueID by SimObject pointer: "
 "More than one master is sharing the same SimObject\n");

 return id;
 }

-MasterID
+UniqueID
 System::lookupMasterId(const std::string& master_name) const
 {
 std::string name = stripSystemName(master_name);
@@ -590,20 +590,20 @@
 return Request::invldMasterId;
 }

-MasterID
+UniqueID
 System::getGlobalMasterId(const std::string& master_name)
 {
 return _getMasterId(nullptr, master_name);
 }

-MasterID
+UniqueID
 System::getMasterId(const SimObject* master, std::string submaster)
 {
 auto master_name = leafMasterName(master, submaster);
 return _getMasterId(master, master_name);
 }

-MasterID
+UniqueID
 System::_getMasterId(const SimObject* master, const std::string&  
master_name)

 {
 std::string name = stripSystemName(master_name);
@@ -624,8 +624,8 @@
 "You must do so in init().\n");
 }

-// Generate a new MasterID incrementally
-MasterID master_id = masters.size();
+// Generate a new UniqueID incrementally
+UniqueID master_id = masters.size();

 // Append the new Master metadata to the group of system Masters.
 masters.emplace_back(master, name, master_id);
@@ -646,7 +646,7 @@
 }

 std::string
-System::getMasterName(MasterID master_id)
+System::getMasterName(UniqueID master_id)
 {
 if (master_id >= masters.size())
 fatal("Invalid master_id passed to getMasterName()\n");
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 8e2c472..5ab5144 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -99,7 +99,7 @@
 SystemPort _systemPort;

 // Map of memory address ranges for devices with their own backing  
stores

-std::unordered_map deviceMemMap;
+std::unordered_map deviceMemMap;

   public:

@@ -361,19 +361,19 @@
  * be considered a non-PIO memory address if the masterId of the packet
  * and range match something in the device memory map.
  */
-void addDeviceMemory(MasterID masterID, AbstractMemory *deviceMemory);
+void addDeviceMemory(UniqueID masterID, AbstractMemory *deviceMemory);

 /**
  * Similar to isMemAddr but for devices. Checks if a physical address
  * of the packet match an address range of a device corresponding to  
the

- * MasterId of the request.
+ * UniqueId of the request.
  */
 bool isDeviceMemAddr(PacketPtr pkt) const;

 /**
  * Return a pointer to the device mem

[gem5-dev] Change in gem5/gem5[develop]: arch: MasterID to UniqueID

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33507 )



Change subject: arch: MasterID to UniqueID
..

arch: MasterID to UniqueID

Change-Id: I14d4d4f09687fa8b883af243d7c4e7b15587527a
---
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/riscv/pagetable_walker.hh
M src/arch/x86/pagetable_walker.hh
8 files changed, 10 insertions(+), 10 deletions(-)



diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py  
b/src/arch/arm/fastmodel/GIC/FastModelGIC.py

index 0980cc4..205a073 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -443,7 +443,7 @@
 output_attributes = Param.String("ExtendedID[62:55]=MPAM_PMG, "
 "ExtendedID[54:39]=MPAM_PARTID, ExtendedID[38]=MPAM_NS",
 "User-defined transform to be applied to bus attributes like "
-"MasterID, ExtendedID or UserFlags. Currently, only works for "
+"UniqueID, ExtendedID or UserFlags. Currently, only works for "
 "MPAM Attributes encoding into bus attributes.")
 has_DirtyVLPIOnLoad = Param.Bool(False, "GICR_VPENDBASER.Dirty  
reflects "

 "transient loading state when valid=1")
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index 0ac7abe..2dfd3de 100644
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -60,7 +60,7 @@
 DmaPort port;

 /** Request id for requests generated by this MMU */
-MasterID masterId;
+UniqueID masterId;

   public:
 /** This translation class is used to trigger the data fetch once a  
timing

diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 1c89c22..3cbd301 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -97,7 +97,7 @@
 }

 void
-TableWalker::setMMU(Stage2MMU *m, MasterID master_id)
+TableWalker::setMMU(Stage2MMU *m, UniqueID master_id)
 {
 stage2Mmu = m;
 port = &m->getDMAPort();
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 6f04149..1597a65 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -829,8 +829,8 @@
 /** Port shared by the two table walkers. */
 DmaPort* port;

-/** Master id assigned by the MMU. */
-MasterID masterId;
+/** Unique id assigned by the MMU. */
+UniqueID masterId;

 /** Indicates whether this table walker is part of the stage 2 mmu */
 const bool isStage2;
@@ -912,7 +912,7 @@

 void setTlb(TLB *_tlb) { tlb = _tlb; }
 TLB* getTlb() { return tlb; }
-void setMMU(Stage2MMU *m, MasterID master_id);
+void setMMU(Stage2MMU *m, UniqueID master_id);
 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
   uint8_t texcb, bool s);
 void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 1d43a0d..0817b9b 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -107,7 +107,7 @@
 }

 void
-TLB::setMMU(Stage2MMU *m, MasterID master_id)
+TLB::setMMU(Stage2MMU *m, UniqueID master_id)
 {
 stage2Mmu = m;
 tableWalker->setMMU(m, master_id);
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 004ce0b..8bb3c9a 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -224,7 +224,7 @@

 TableWalker *getTableWalker() { return tableWalker; }

-void setMMU(Stage2MMU *m, MasterID master_id);
+void setMMU(Stage2MMU *m, UniqueID master_id);

 int getsize() const { return size; }

diff --git a/src/arch/riscv/pagetable_walker.hh  
b/src/arch/riscv/pagetable_walker.hh

index d9ab569..ccf7d1f 100644
--- a/src/arch/riscv/pagetable_walker.hh
+++ b/src/arch/riscv/pagetable_walker.hh
@@ -166,7 +166,7 @@
 // The TLB we're supposed to load.
 TLB * tlb;
 System * sys;
-MasterID masterId;
+UniqueID masterId;

 // The number of outstanding walks that can be squashed per cycle.
 unsigned numSquashable;
diff --git a/src/arch/x86/pagetable_walker.hh  
b/src/arch/x86/pagetable_walker.hh

index 55bb098..96ce0e2 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -168,7 +168,7 @@
 // The TLB we're supposed to load.
 TLB * tlb;
 System * sys;
-MasterID masterId;
+UniqueID masterId;

 // The number of outstanding walks that can be squashed per cycle.
 unsigned numSquashable;

--
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[gem5-dev] Change in gem5/gem5[develop]: mem: MasterID to UniqueID

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33511 )



Change subject: mem: MasterID to UniqueID
..

mem: MasterID to UniqueID

Change-Id: I1282ede2f818c0b1d99c5ef90efd83f2f5dbd286
---
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/tags/base.cc
M src/mem/dram_ctrl.hh
M src/mem/external_master.hh
M src/mem/mem_master.hh
M src/mem/packet.hh
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
M src/mem/qos/policy.hh
M src/mem/qos/policy_fixed_prio.cc
M src/mem/qos/policy_fixed_prio.hh
M src/mem/qos/policy_pf.cc
M src/mem/qos/policy_pf.hh
M src/mem/qos/q_policy.cc
M src/mem/qos/q_policy.hh
M src/mem/request.hh
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
22 files changed, 75 insertions(+), 75 deletions(-)



diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 7009db7..d080591 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -94,7 +94,7 @@
 /** The program counter that generated this address. */
 Addr pc;
 /** The requestor ID that generated this address. */
-MasterID masterId;
+UniqueID masterId;
 /** Validity bit for the PC of this address. */
 bool validPC;
 /** Whether this address targets the secure memory space. */
@@ -152,7 +152,7 @@
  * Gets the requestor ID that generated this address
  * @return the requestor ID that generated this address
  */
-MasterID getMasterId() const
+UniqueID getMasterId() const
 {
 return masterId;
 }
@@ -281,7 +281,7 @@
 const bool onInst;

 /** Request id for prefetches */
-const MasterID masterId;
+const UniqueID masterId;

 const Addr pageBytes;

diff --git a/src/mem/cache/prefetch/queued.cc  
b/src/mem/cache/prefetch/queued.cc

index c2ae090..15ac013 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -51,7 +51,7 @@

 void
 Queued::DeferredPacket::createPkt(Addr paddr, unsigned blk_size,
-MasterID mid, bool  
tag_prefetch,
+UniqueID mid, bool  
tag_prefetch,

 Tick t) {
 /* Create a prefetch memory request */
 RequestPtr req = std::make_shared(paddr, blk_size, 0, mid);
diff --git a/src/mem/cache/prefetch/queued.hh  
b/src/mem/cache/prefetch/queued.hh

index 5af9093..95974c1 100644
--- a/src/mem/cache/prefetch/queued.hh
+++ b/src/mem/cache/prefetch/queued.hh
@@ -106,7 +106,7 @@
  *tagged
  * @param t time when the prefetch becomes ready
  */
-void createPkt(Addr paddr, unsigned blk_size, MasterID mid,
+void createPkt(Addr paddr, unsigned blk_size, UniqueID mid,
bool tag_prefetch, Tick t);

 /**
diff --git a/src/mem/cache/prefetch/stride.cc  
b/src/mem/cache/prefetch/stride.cc

index 36773c6..9f8ac8b 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -124,7 +124,7 @@
 Addr pf_addr = pfi.getAddr();
 Addr pc = pfi.getPC();
 bool is_secure = pfi.isSecure();
-MasterID master_id = useMasterId ? pfi.getMasterId() : 0;
+UniqueID master_id = useMasterId ? pfi.getMasterId() : 0;

 // Get corresponding pc table
 PCTable* pcTable = findTable(master_id);
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index faad7be..89742a3 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -105,7 +105,7 @@
 // to insert the new one

 // Deal with what we are bringing in
-MasterID master_id = pkt->req->masterId();
+UniqueID master_id = pkt->req->masterId();
 assert(master_id < system->maxMasters());
 stats.occupancies[master_id]++;

diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index a8433c8..656849e 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -617,8 +617,8 @@
 /** This comes from the outside world */
 const PacketPtr pkt;

-/** MasterID associated with the packet */
-const MasterID _masterId;
+/** UniqueID associated with the packet */
+const UniqueID _masterId;

 const bool read;

@@ -674,10 +674,10 @@
 inline uint8_t qosValue() const { return _qosValue; }

 /**
- * Get the packet MasterID
+ * Get the packet UniqueID
  * (interface compatibility with Packet)
  */
-inline MasterID masterId() const { return _masterId; }
+inline UniqueID masterId() const { return _masterId; }

 /**
  * Get the packet size
diff --git a/src/mem/exter

[gem5-dev] Change in gem5/gem5[develop]: misc: MasterInfo to RequestorInfo

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33515 )



Change subject: misc: MasterInfo to RequestorInfo
..

misc: MasterInfo to RequestorInfo

Change-Id: Ia0e9ea1f686bf360c04d34d8828962d12c001a10
---
M src/mem/mem_master.hh
M src/sim/system.hh
2 files changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/mem/mem_master.hh b/src/mem/mem_master.hh
index 2393ce4..6a1d9ad 100644
--- a/src/mem/mem_master.hh
+++ b/src/mem/mem_master.hh
@@ -37,7 +37,7 @@

 /**
  * @file
- * MasterInfo declaration.
+ * RequestorInfo declaration.
  */

 #ifndef __MEM_MEM_MASTER_HH__
@@ -47,11 +47,11 @@
 #include "sim/sim_object.hh"

 /**
- * The MasterInfo class contains data about a specific master.
+ * The RequestorInfo class contains data about a specific master.
  */
-struct MasterInfo
+struct RequestorInfo
 {
-MasterInfo(const SimObject* _obj,
+RequestorInfo(const SimObject* _obj,
std::string master_name,
UniqueID master_id)
   : obj(_obj), masterName(master_name), masterId(master_id)
diff --git a/src/sim/system.hh b/src/sim/system.hh
index b6f7583..0a3ca22 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -427,7 +427,7 @@
  * It's used to uniquely id any master in the system by name for things
  * like cache statistics.
  */
-std::vector masters;
+std::vector masters;

 ThermalModel * thermalModel;


--
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[gem5-dev] Change in gem5/gem5[develop]: sim: MasterID to UniqueID

2020-08-26 Thread Eden Avivi (Gerrit) via gem5-dev

Eden Avivi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33514 )



Change subject: sim: MasterID to UniqueID
..

sim: MasterID to UniqueID

Change-Id: I5096af531d0c774e183fb04428d672add75c4046
---
M src/sim/system.hh
1 file changed, 9 insertions(+), 9 deletions(-)



diff --git a/src/sim/system.hh b/src/sim/system.hh
index 5ab5144..b6f7583 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -482,31 +482,31 @@
  * @param masterName full name of the master
  * @return the master's ID.
  */
-MasterID getGlobalMasterId(const std::string& master_name);
+UniqueID getGlobalMasterId(const std::string& master_name);

 /**
  * Get the name of an object for a given request id.
  */
-std::string getMasterName(MasterID master_id);
+std::string getMasterName(UniqueID master_id);

 /**
- * Looks up the MasterID for a given SimObject
- * returns an invalid MasterID (invldMasterId) if not found.
+ * Looks up the UniqueID for a given SimObject
+ * returns an invalid UniqueID (invldMasterId) if not found.
  */
-MasterID lookupMasterId(const SimObject* obj) const;
+UniqueID lookupMasterId(const SimObject* obj) const;

 /**
- * Looks up the MasterID for a given object name string
+ * Looks up the UniqueID for a given object name string
  * returns an invalid MasterID (invldMasterId) if not found.
  */
-MasterID lookupMasterId(const std::string& name) const;
+UniqueID lookupMasterId(const std::string& name) const;

 /** Get the number of masters registered in the system */
-MasterID maxMasters() { return masters.size(); }
+UniqueID maxMasters() { return masters.size(); }

   protected:
 /** helper function for getMasterId */
-MasterID _getMasterId(const SimObject* master,
+UniqueID _getMasterId(const SimObject* master,
   const std::string& master_name);

 /**

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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Replaced master/slave variables,comments

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33516 )



Change subject: arch-x86: Replaced master/slave variables,comments
..

arch-x86: Replaced master/slave variables,comments

src/arch/x86/X86LocalApic.py

Change-Id: I4298fe7059a8860fcb25d2a296e7c74409d821d8
---
M src/arch/x86/X86LocalApic.py
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
3 files changed, 14 insertions(+), 7 deletions(-)



diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index 442a5e1..39004d2 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -48,8 +48,15 @@
 type = 'X86LocalApic'
 cxx_class = 'X86ISA::Interrupts'
 cxx_header = 'arch/x86/interrupts.hh'
-int_master = RequestPort("Port for sending interrupt messages")
-int_slave = ResponsePort("Port for receiving interrupt messages")
+
+int_requestor = RequestPort("Port for sending interrupt messages")
+int_master= DeprecatedParam(int_requestor,
+'`int_master` is now called `int_requestor`')
+
+int_responder = ResponsePort("Port for receiving interrupt messages")
+int_slave = DeprecatedParam(int_responder,
+'`int_slave` is now called `int_responder`')
+
 int_latency = Param.Latency('1ns', \
 "Latency for an interrupt to propagate through this device.")
 pio = ResponsePort("Programmed I/O port")
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 2be0746..b25e8a7 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -603,8 +603,8 @@
   pendingStartup(false), startupVector(0),
   startedUp(false), pendingUnmaskableInt(false),
   pendingIPIs(0),
-  intSlavePort(name() + ".int_slave", this, this),
-  intMasterPort(name() + ".int_master", this, this, p->int_latency),
+  intSlavePort(name() + ".int_responder", this, this),
+  intMasterPort(name() + ".int_requestor", this, this, p->int_latency),
   pioPort(this), pioDelay(p->pio_latency)
 {
 memset(regs, 0, sizeof(regs));
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index c1b2565..1a4904f 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -228,9 +228,9 @@
 Port &getPort(const std::string &if_name,
   PortID idx=InvalidPortID) override
 {
-if (if_name == "int_master") {
-return intMasterPort;
-} else if (if_name == "int_slave") {
+if (if_name == "int_requestor") {
+return intRequestPort;
+} else if (if_name == "int_responder") {
 return intSlavePort;
 } else if (if_name == "pio") {
 return pioPort;

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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Update master/slave variables

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33520 )



Change subject: dev-arm: Update master/slave variables
..

dev-arm: Update master/slave variables

Change-Id: I2fa67b81f138b0b6691edc17d93f0585746ab343
---
M src/dev/arm/RealView.py
M src/dev/arm/UFSHostDevice.py
2 files changed, 11 insertions(+), 11 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 440292b..d157942 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -94,8 +94,8 @@
 abstract = True
 cxx_header = "dev/arm/amba_device.hh"
 pio_addr = Param.Addr("Address for AMBA responder interface")
-pio_latency = Param.Latency("10ns",
-"Time between action and write/read result by AMBA DMA Device")
+pio_latency = Param.Latency("10ns", "Time between action and  
write/read"

+"result by AMBA DMA Device")
 interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
 amba_id = Param.UInt32("ID of AMBA device for kernel detection")

@@ -577,16 +577,16 @@
 def _attach_memory(self, mem, bus, mem_ports=None):
 if hasattr(mem, "port"):
 if mem_ports is None:
-mem.port = bus.master
+mem.port = bus.mem_side
 else:
 mem_ports.append(mem.port)

 def _attach_device(self, device, bus, dma_ports=None):
 if hasattr(device, "pio"):
-device.pio = bus.master
+device.pio = bus.mem_side
 if hasattr(device, "dma"):
 if dma_ports is None:
-device.dma = bus.slave
+device.dma = bus.cpu_side
 else:
 dma_ports.append(device.dma)

@@ -1093,15 +1093,15 @@
 """
 Instantiate a single SMMU and attach a group of client devices to  
it.

 The devices' dma port is wired to the SMMU and the SMMU's dma port
-(master) is attached to the bus. In order to make it work, the list
+(requestor) is attached to the bus. In order to make it work, the  
list
 of clients shouldn't contain any device part of the  
_off_chip_devices

 or _on_chip_devices.
 This method should be called only once.

 Parameters:
 devices (list): List of devices which will be using the SMMU
-bus (Bus): The bus downstream of the SMMU. Its slave port will
-   receive memory requests from the SMMU, and its  
master
+bus (Bus): The bus downstream of the SMMU. Its response port  
will
+   receive memory requests from the SMMU, and its  
request
port will forward accesses to the memory mapped  
devices

 """
 if hasattr(self, 'smmu'):
@@ -1109,8 +1109,8 @@

 self.smmu = SMMUv3(reg_map=AddrRange(0x2b40, size=0x0002))

-self.smmu.master = bus.slave
-self.smmu.control = bus.master
+self.smmu.mem_side = bus.cpu_side
+self.smmu.control = bus.mem_side

 dma_ports = []
 for dev in devices:
diff --git a/src/dev/arm/UFSHostDevice.py b/src/dev/arm/UFSHostDevice.py
index a444a9a..879503a 100644
--- a/src/dev/arm/UFSHostDevice.py
+++ b/src/dev/arm/UFSHostDevice.py
@@ -42,7 +42,7 @@
 class UFSHostDevice(DmaDevice):
 type = 'UFSHostDevice'
 cxx_header = "dev/arm/ufs_device.hh"
-pio_addr = Param.Addr("Address for SCSI configuration slave interface")
+pio_addr = Param.Addr("Address for SCSI configuration responder  
interface")
 pio_latency = Param.Latency("10ns", "Time between action and  
write/read \

result by AMBA DMA Device")
 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")

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[gem5-dev] Change in gem5/gem5[develop]: arch: Update master/slave variables

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33519 )



Change subject: arch: Update master/slave variables
..

arch: Update master/slave variables

Change-Id: Ib2ddf64ff250b1c78ed2d950850058048ddfdc9d
---
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
2 files changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index b25e8a7..7767c80 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -288,12 +288,12 @@
 void
 X86ISA::Interrupts::init()
 {
-panic_if(!intMasterPort.isConnected(),
+panic_if(!intRequestPort.isConnected(),
 "Int port not connected to anything!");
 panic_if(!pioPort.isConnected(),
 "Pio port of %s not connected to anything!", name());

-intSlavePort.sendRangeChange();
+intResponsePort.sendRangeChange();
 pioPort.sendRangeChange();
 }

@@ -541,7 +541,7 @@
 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
 for (auto id: apics) {
 PacketPtr pkt = buildIntTriggerPacket(id, message);
-intMasterPort.sendMessage(pkt, sys->isTimingMode(),
+intRequestPort.sendMessage(pkt, sys->isTimingMode(),
 [this](PacketPtr pkt) { completeIPI(pkt); });
 }
 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
@@ -603,8 +603,8 @@
   pendingStartup(false), startupVector(0),
   startedUp(false), pendingUnmaskableInt(false),
   pendingIPIs(0),
-  intSlavePort(name() + ".int_responder", this, this),
-  intMasterPort(name() + ".int_requestor", this, this, p->int_latency),
+  intResponsePort(name() + ".int_responder", this, this),
+  intRequestPort(name() + ".int_requestor", this, this,  
p->int_latency),

   pioPort(this), pioDelay(p->pio_latency)
 {
 memset(regs, 0, sizeof(regs));
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 1a4904f..8712bbc 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -174,8 +174,8 @@
 int initialApicId;

 // Ports for interrupts.
-IntSlavePort intSlavePort;
-IntMasterPort intMasterPort;
+IntSlavePort intResponsePort;
+IntMasterPort intRequestPort;

 // Port for memory mapped register accesses.
 PioPort pioPort;
@@ -231,7 +231,7 @@
 if (if_name == "int_requestor") {
 return intRequestPort;
 } else if (if_name == "int_responder") {
-return intSlavePort;
+return intResponsePort;
 } else if (if_name == "pio") {
 return pioPort;
 }

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[gem5-dev] Change in gem5/gem5[develop]: cpu: Replaced master/slave variables and comments

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33517 )



Change subject: cpu: Replaced master/slave variables and comments
..

cpu: Replaced master/slave variables and comments

Change-Id: I99bca2ae43b39a8f8243b2a4af0a2eb6e941a2af
---
M src/cpu/o3/commit_impl.hh
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/testers/traffic_gen/traffic_gen.hh
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
6 files changed, 21 insertions(+), 21 deletions(-)



diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index de79206..a549bf1 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -733,7 +733,7 @@
 {
 // Verify that we still have an interrupt to handle
 if (!cpu->checkInterrupts(0)) {
-DPRINTF(Commit, "Pending interrupt is cleared by master before "
+DPRINTF(Commit, "Pending interrupt is cleared by requestor before "
 "it got handled. Restart fetching from the orig path.\n");
 toIEW->commitInfo[0].clearInterrupt = true;
 interrupt = NoFault;
diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py  
b/src/cpu/testers/traffic_gen/BaseTrafficGen.py

index ff50a19..f56d7c9 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -44,7 +44,7 @@
 # generated (Random, Linear, Trace etc)
 class StreamGenType(ScopedEnum): vals = [ 'none', 'fixed', 'random' ]

-# The traffic generator is a master module that generates stimuli for
+# The traffic generator is a requestor module that generates stimuli for
 # the memory system, based on a collection of simple behaviours that
 # are either probabilistic or based on traces. It can be used stand
 # alone for creating test cases for interconnect and memory
@@ -57,7 +57,7 @@
 cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"

 # Port used for sending requests and receiving responses
-port = RequestPort("Master port")
+port = RequestPort("This port sends requests and receives responses")

 # System used to determine the mode of the memory system
 system = Param.System(Parent.any, "System this generator is part of")
@@ -110,9 +110,9 @@
 def connectCachedPorts(self, bus):
 if hasattr(self, '_cached_ports') and (len(self._cached_ports) >  
0):

 for p in self._cached_ports:
-exec('self.%s = bus.slave' % p)
+exec('self.%s = bus.cpu_side' % p)
 else:
-self.port = bus.slave
+self.port = bus.cpu_side

 def connectAllPorts(self, cached_bus, uncached_bus = None):
 self.connectCachedPorts(cached_bus)
diff --git a/src/cpu/testers/traffic_gen/base.hh  
b/src/cpu/testers/traffic_gen/base.hh

index 17b1aa1..2466206 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -53,7 +53,7 @@
 struct BaseTrafficGenParams;

 /**
- * The traffic generator is a master module that generates stimuli for
+ * The traffic generator is a memside module that generates stimuli for
  * the memory system, based on a collection of simple generator
  * behaviours that are either probabilistic or based on traces. It can
  * be used stand alone for creating test cases for interconnect and
@@ -123,7 +123,7 @@
 const int maxOutstandingReqs;


-/** Master port specialisation for the traffic generator */
+/** Request port specialisation for the traffic generator */
 class TrafficGenPort : public RequestPort
 {
   public:
@@ -157,7 +157,7 @@
  */
 void update();

-/** The instance of master port used by the traffic generator. */
+/** The instance of request port used by the traffic generator. */
 TrafficGenPort port;

 /** Packet waiting to be sent. */
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh  
b/src/cpu/testers/traffic_gen/traffic_gen.hh

index 3f1c2ab..5dab256 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.hh
+++ b/src/cpu/testers/traffic_gen/traffic_gen.hh
@@ -45,7 +45,7 @@
 struct TrafficGenParams;

 /**
- * The traffic generator is a master module that generates stimuli for
+ * The traffic generator is a memside module that generates stimuli for
  * the memory system, based on a collection of simple behaviours that
  * are either probabilistic or based on traces. It can be used stand
  * alone for creating test cases for interconnect and memory
@@ -53,7 +53,7 @@
  * components that are not yet modelled in detail, e.g. a video engine
  * or baseband subsystem in an SoC.
  *
- * The traffic generator has a single master port that is used to send
+ * The traffic generator has a single request port that is used to send
  * requests, independent of the specific behaviour. The behaviour of
  * the traffic generator is specified in a configuration file, and this
  * f

[gem5-dev] Change in gem5/gem5[develop]: dev-arm,dev: Replaced master/slave variables + comments --x86

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33518 )



Change subject: dev-arm,dev: Replaced master/slave variables + comments  
--x86

..

dev-arm,dev: Replaced master/slave variables + comments --x86

Change-Id: I975498ab67879e22afb59b6159d019021254f571
---
M src/dev/arm/RealView.py
M src/dev/serial/terminal.cc
M src/dev/storage/ide_ctrl.cc
M src/dev/storage/ide_ctrl.hh
M src/dev/x86/I82094AA.py
M src/dev/x86/SouthBridge.py
M src/dev/x86/i82094aa.cc
7 files changed, 25 insertions(+), 19 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 684567f..440292b 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -93,8 +93,9 @@
 type = 'AmbaDmaDevice'
 abstract = True
 cxx_header = "dev/arm/amba_device.hh"
-pio_addr = Param.Addr("Address for AMBA slave interface")
-pio_latency = Param.Latency("10ns", "Time between action and  
write/read result by AMBA DMA Device")

+pio_addr = Param.Addr("Address for AMBA responder interface")
+pio_latency = Param.Latency("10ns",
+"Time between action and write/read result by AMBA DMA Device")
 interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
 amba_id = Param.UInt32("ID of AMBA device for kernel detection")

diff --git a/src/dev/serial/terminal.cc b/src/dev/serial/terminal.cc
index 7cfc6d7..8b420da 100644
--- a/src/dev/serial/terminal.cc
+++ b/src/dev/serial/terminal.cc
@@ -204,7 +204,7 @@
 pollQueue.schedule(dataEvent);

 stringstream stream;
-ccprintf(stream, " m5 slave terminal: Terminal %d ", number);
+ccprintf(stream, " m5 terminal: Terminal %d ", number);

 // we need an actual carriage return followed by a newline for the
 // terminal
diff --git a/src/dev/storage/ide_ctrl.cc b/src/dev/storage/ide_ctrl.cc
index 632144c..47cdd10 100644
--- a/src/dev/storage/ide_ctrl.cc
+++ b/src/dev/storage/ide_ctrl.cc
@@ -77,7 +77,7 @@
 string newName, Addr _cmdSize, Addr _ctrlSize) :
 _name(newName),
 cmdAddr(0), cmdSize(_cmdSize), ctrlAddr(0), ctrlSize(_ctrlSize),
-master(NULL), slave(NULL), selected(NULL)
+device0(NULL), device1(NULL), selected(NULL)
 {
 bmiRegs.reset();
 bmiRegs.status.dmaCap0 = 1;
@@ -105,16 +105,16 @@
 continue;
 switch (i) {
   case 0:
-primary.master = params()->disks[0];
+primary.device0 = params()->disks[0];
 break;
   case 1:
-primary.slave = params()->disks[1];
+primary.device1 = params()->disks[1];
 break;
   case 2:
-secondary.master = params()->disks[2];
+secondary.device0 = params()->disks[2];
 break;
   case 3:
-secondary.slave = params()->disks[3];
+secondary.device1 = params()->disks[3];
 break;
   default:
 panic("IDE controllers support a maximum "
@@ -156,9 +156,9 @@
 IdeController::setDmaComplete(IdeDisk *disk)
 {
 Channel *channel;
-if (disk == primary.master || disk == primary.slave) {
+if (disk == primary.device0 || disk == primary.device1) {
 channel = &primary;
-} else if (disk == secondary.master || disk == secondary.slave) {
+} else if (disk == secondary.device0 || disk == secondary.device1) {
 channel = &secondary;
 } else {
 panic("Unable to find disk based on pointer %#x\n", disk);
diff --git a/src/dev/storage/ide_ctrl.hh b/src/dev/storage/ide_ctrl.hh
index 44e8c5b..5410985 100644
--- a/src/dev/storage/ide_ctrl.hh
+++ b/src/dev/storage/ide_ctrl.hh
@@ -89,8 +89,13 @@
 uint32_t bmidtp;
 } bmiRegs;

-/** IDE disks connected to this controller */
-IdeDisk *master, *slave;
+/** IDE disks connected to this controller
+ * For more details about device0 and device1 see:
+ * https://en.wikipedia.org/wiki/Parallel_ATA
+ * #Multiple_devices_on_a_cable
+ *
+*/
+IdeDisk *device0, *device1;

 /** Currently selected disk */
 IdeDisk *selected;
@@ -98,10 +103,10 @@
 bool selectBit;

 void
-select(bool selSlave)
+select(bool selDisk)
 {
-selectBit = selSlave;
-selected = selectBit ? slave : master;
+selectBit = selDisk;
+selected = selectBit ? device1 : device0;
 }

 void accessCommand(Addr offset, int size, uint8_t *data, bool  
read);

diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py
index 2cb210a..ce1f394 100644
--- a/src/dev/x86/I82094AA.py
+++ b/src/dev/x86/I82094AA.py
@@ -34,7 +34,7 @@
 cxx_class = 'X86ISA::I82094AA'
 cxx_header = "dev/x86/i82094aa.hh"
 apic_id = Param.Int(1, 'APIC id for this IO APIC')
-int_master = RequestPort("Port for se

[gem5-dev] Change in gem5/gem5[develop]: sim: Update master/slave variables/comments

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33524 )



Change subject: sim: Update master/slave variables/comments
..

sim: Update master/slave variables/comments

Change-Id: I53c93e049e26ef24f3640b332d7c66bd8a2a248d
---
M src/sim/cxx_config.hh
M src/sim/cxx_manager.cc
M src/sim/cxx_manager.hh
M src/sim/probe/mem.hh
M src/sim/system.cc
5 files changed, 51 insertions(+), 49 deletions(-)



diff --git a/src/sim/cxx_config.hh b/src/sim/cxx_config.hh
index 9f8a07d..9a45e76 100644
--- a/src/sim/cxx_config.hh
+++ b/src/sim/cxx_config.hh
@@ -95,12 +95,12 @@
 /* Is this a vector or singleton parameters/SimObject */
 const bool isVector;

-/** Is this a master or slave port */
-const bool isMaster;
+/** Is this a request or response port */
+const bool isRequestor;

 PortDesc(const std::string &name_,
-bool isVector_, bool isMaster_) :
-name(name_), isVector(isVector_), isMaster(isMaster_)
+bool isVector_, bool isRequestor_) :
+name(name_), isVector(isVector_), isRequestor(isRequestor_)
 { }
 };

diff --git a/src/sim/cxx_manager.cc b/src/sim/cxx_manager.cc
index 71ee10b..5511d5f 100644
--- a/src/sim/cxx_manager.cc
+++ b/src/sim/cxx_manager.cc
@@ -444,39 +444,39 @@

 void
 CxxConfigManager::bindPort(
-SimObject *master_object, const std::string &master_port_name,
-PortID master_port_index,
-SimObject *slave_object, const std::string &slave_port_name,
-PortID slave_port_index)
+SimObject *master_object, const std::string &request_port_name,
+PortID request_port_index,
+SimObject *response_object, const std::string &response_port_name,
+PortID response_port_index)
 {
-/* FIXME, check slave_port_index against connection_count
+/* FIXME, check response_port_index against connection_count
  *  defined for port, need getPortConnectionCount and a
  *  getCxxConfigDirectoryEntry for each object. */

 /* It would be nice to be able to catch the errors from these calls. */
-Port &master_port = master_object->getPort(
-master_port_name, master_port_index);
-Port &slave_port = slave_object->getPort(
-slave_port_name, slave_port_index);
+Port &request_port = master_object->getPort(
+request_port_name, request_port_index);
+Port &response_port = response_object->getPort(
+response_port_name, response_port_index);

-if (master_port.isConnected()) {
+if (request_port.isConnected()) {
 throw Exception(master_object->name(), csprintf(
-"Master port: %s[%d] is already connected\n", master_port_name,
-master_port_index));
+"Request port: %s[%d] is already connected\n",  
request_port_name,

+request_port_index));
 }

-if (slave_port.isConnected()) {
-throw Exception(slave_object->name(), csprintf(
-"Slave port: %s[%d] is already connected\n", slave_port_name,
-slave_port_index));
+if (response_port.isConnected()) {
+throw Exception(response_object->name(), csprintf(
+"Response port: %s[%d] is already connected\n",  
response_port_name,

+response_port_index));
 }

 DPRINTF(CxxConfig, "Binding port %s.%s[%d]"
 " to %s:%s[%d]\n",
-master_object->name(), master_port_name, master_port_index,
-slave_object->name(), slave_port_name, slave_port_index);
+master_object->name(), request_port_name, request_port_index,
+response_object->name(), response_port_name, response_port_index);

-master_port.bind(slave_port);
+request_port.bind(response_port);
 }

 void
@@ -484,32 +484,34 @@
 const CxxConfigDirectoryEntry::PortDesc &port,
 const std::vector &peers)
 {
-unsigned int master_port_index = 0;
+unsigned int request_port_index = 0;

 for (auto peer_i = peers.begin(); peer_i != peers.end();
 ++peer_i)
 {
 const std::string &peer = *peer_i;
-std::string slave_object_name;
-std::string slave_port_name;
-unsigned int slave_port_index;
+std::string response_object_name;
+std::string response_port_name;
+unsigned int response_port_index;

-parsePort(peer, slave_object_name, slave_port_name,
-slave_port_index);
+parsePort(peer, response_object_name, response_port_name,
+response_port_index);

-std::string slave_instance_name = rename(slave_object_name);
+std::string response_instance_name = rename(response_object_name);

-if (objectsByName.find(slave_instance_name) ==  
objectsByName.end()) {

+if (objectsByName.find(response_instance_name)
+== objectsByName.end()) {
 throw Exception(object->name(), csprintf(
-"Can't find

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Update master/slave variables

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33523 )



Change subject: mem-ruby: Update master/slave variables
..

mem-ruby: Update master/slave variables

master -> mem_side, slave -> cpu_side
update comments

Change-Id: I21ace53f697c4e12d1d7e8d5cbd6fa68017a7f74
---
M src/mem/ruby/network/MessageBuffer.py
M src/mem/ruby/network/Network.py
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/system/DMASequencer.cc
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/RubySystem.hh
M src/mem/ruby/system/Sequencer.py
10 files changed, 106 insertions(+), 92 deletions(-)



diff --git a/src/mem/ruby/network/MessageBuffer.py  
b/src/mem/ruby/network/MessageBuffer.py

index c796960..712af5f 100644
--- a/src/mem/ruby/network/MessageBuffer.py
+++ b/src/mem/ruby/network/MessageBuffer.py
@@ -40,5 +40,7 @@
random delays if RubySystem \
randomization flag is True)")

-master = RequestPort("Master port to MessageBuffer receiver")
-slave = ResponsePort("Slave port from MessageBuffer sender")
+out_port = RequestPort("Request port to MessageBuffer receiver")
+master = DeprecatedParam(out_port, '`master` is now called `out_port`')
+in_port = ResponsePort("Response port from MessageBuffer sender")
+slave = DeprecatedParam(in_port, '`slave` is now called `in_port`')
\ No newline at end of file
diff --git a/src/mem/ruby/network/Network.py  
b/src/mem/ruby/network/Network.py

index 5acad60..cd5625a 100644
--- a/src/mem/ruby/network/Network.py
+++ b/src/mem/ruby/network/Network.py
@@ -49,5 +49,7 @@
 ext_links = VectorParam.BasicExtLink("Links to external nodes")
 int_links = VectorParam.BasicIntLink("Links between internal nodes")

-slave = VectorSlavePort("CPU slave port")
-master = VectorMasterPort("CPU master port")
+in_port = VectorSlavePort("CPU slave port")
+slave = DeprecatedParam(in_port, '`slave` is now called `in_port`')
+out_port = VectorMasterPort("CPU master port")
+master = DeprecatedParam(out_port, '`master` is now called `out_port`')
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh  
b/src/mem/ruby/slicc_interface/AbstractController.hh

index daa52da..1d7e5a7 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -237,7 +237,7 @@
 void recvReqRetry();
 };

-/* Master port to the memory controller. */
+/* Request port to the memory controller. */
 MemoryPort memoryPort;

 // State that is stored in packets sent to the memory controller.
diff --git a/src/mem/ruby/system/DMASequencer.cc  
b/src/mem/ruby/system/DMASequencer.cc

index bad49c9..80cbc4c 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -57,7 +57,7 @@
 RubyPort::init();
 m_data_block_mask = mask(RubySystem::getBlockSizeBits());

-for (const auto &s_port : slave_ports)
+for (const auto &s_port : cpu_side_ports)
 s_port->sendRangeChange();
 }

diff --git a/src/mem/ruby/system/GPUCoalescer.cc  
b/src/mem/ruby/system/GPUCoalescer.cc

index 80bc19a..ce1f149 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -669,7 +669,7 @@
 // back the requesting CU when we receive write
 // complete callbacks for all issued Ruby requests of this
 // instruction.
-RubyPort::MemSlavePort* mem_slave_port = ss->port;
+RubyPort::MemSlavePort* mem_response_port = ss->port;

 GPUDynInstPtr gpuDynInst = nullptr;

@@ -686,7 +686,8 @@
 }

 PendingWriteInst& inst = pendingWriteInsts[seqNum];
-inst.addPendingReq(mem_slave_port, gpuDynInst,  
m_usingRubyTester);

+inst.addPendingReq(mem_response_port, gpuDynInst,
+   m_usingRubyTester);
 }

 return true;
diff --git a/src/mem/ruby/system/RubyPort.cc  
b/src/mem/ruby/system/RubyPort.cc

index 4510e3a..fa13cf4 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -55,27 +55,28 @@
 : ClockedObject(p), m_ruby_system(p->ruby_system),  
m_version(p->version),

   m_controller(NULL), m_mandatory_q_ptr(NULL),
   m_usingRubyTester(p->using_ruby_tester), system(p->system),
-  pioMasterPort(csprintf("%s.pio-master-port", name()), this),
-  pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
-  memMasterPort(csprintf("%s.mem-master-port", name()), this),
-  memSlavePort(csprintf("%s-mem-slave-port", name()), this,
+  pioRequestPort(csprintf("%s.pio-request-port", name()), this),
+  pioResponsePort(csprintf("%

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Update master/slave variables -smmu

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33521 )



Change subject: dev-arm: Update master/slave variables -smmu
..

dev-arm: Update master/slave variables -smmu

Change-Id: I9fcb9374e5de4daa2212f8d9a441010878d015bf
---
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3.hh
M src/dev/arm/smmu_v3_proc.cc
M src/dev/arm/smmu_v3_slaveifc.cc
M src/dev/arm/smmu_v3_slaveifc.hh
M src/dev/arm/smmu_v3_transl.cc
6 files changed, 49 insertions(+), 47 deletions(-)



diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index f9d99da..d3d8a53 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -54,9 +54,9 @@
 SMMUv3::SMMUv3(SMMUv3Params *params) :
 ClockedObject(params),
 system(*params->system),
-masterId(params->system->getMasterId(this)),
-masterPort(name() + ".master", *this),
-masterTableWalkPort(name() + ".master_walker", *this),
+_id(params->system->getMasterId(this)),
+requestPort(name() + ".requestor", *this),
+requestTableWalkPort(name() + ".requestor_walker", *this),
 controlPort(name() + ".control", *this, params->reg_map),
 tlb(params->tlb_entries, params->tlb_assoc, params->tlb_policy),
 configCache(params->cfg_entries, params->cfg_assoc,  
params->cfg_policy),

@@ -74,14 +74,14 @@
 walkCacheNonfinalEnable(params->wc_nonfinal_enable),
 walkCacheS1Levels(params->wc_s1_levels),
 walkCacheS2Levels(params->wc_s2_levels),
-masterPortWidth(params->master_port_width),
+requestPortWidth(params->request_port_width),
 tlbSem(params->tlb_slots),
 ifcSmmuSem(1),
 smmuIfcSem(1),
 configSem(params->cfg_slots),
 ipaSem(params->ipa_slots),
 walkSem(params->walk_slots),
-masterPortSem(1),
+requestPortSem(1),
 transSem(params->xlate_slots),
 ptwSem(params->ptw_slots),
 cycleSem(1),
@@ -91,7 +91,7 @@
 configLat(params->cfg_lat),
 ipaLat(params->ipa_lat),
 walkLat(params->walk_lat),
-slaveInterfaces(params->slave_interfaces),
+respInterfaces(params->responder_interfaces),
 commandExecutor(name() + ".cmd_exec", *this),
 regsMap(params->reg_map),
 processCommandsEvent(this)
@@ -153,7 +153,7 @@
 DPRINTF(SMMUv3, "[t] master retr addr=%#x size=%#x\n",
 a.pkt->getAddr(), a.pkt->getSize());

-if (!masterPort.sendTimingReq(a.pkt))
+if (!requestPort.sendTimingReq(a.pkt))
 break;

 packetsToRetry.pop();
@@ -249,7 +249,7 @@
 }
 M5_FALLTHROUGH;
 case ACTION_SEND_REQ_FINAL:
-delay += masterPort.sendAtomic(action.pkt);
+delay += requestPort.sendAtomic(action.pkt);
 pkt = action.pkt;
 break;

@@ -310,7 +310,8 @@
 DPRINTF(SMMUv3, "[t] master req  addr=%#x size=%#x\n",
 action.pkt->getAddr(), action.pkt->getSize());

-if (packetsToRetry.empty() &&  
masterPort.sendTimingReq(action.pkt)) {

+if (packetsToRetry.empty() &&
+requestPort.sendTimingReq(action.pkt)) {
 scheduleSlaveRetries();
 } else {
 DPRINTF(SMMUv3, "[t] master req  needs retry, qlen=%d\n",
@@ -717,7 +718,7 @@
 SMMUv3::init()
 {
 // make sure both sides are connected and have the same block size
-if (!masterPort.isConnected())
+if (!requestPort.isConnected())
 fatal("Master port is not connected.\n");

 // If the second master port is connected for the table walks, enable
@@ -816,9 +817,9 @@
 SMMUv3::getPort(const std::string &name, PortID id)
 {
 if (name == "master") {
-return masterPort;
-} else if (name == "master_walker") {
-return masterTableWalkPort;
+return requestPort;
+} else if (name == "requestor_walker") {
+return requestTableWalkPort;
 } else if (name == "control") {
 return controlPort;
 } else {
diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh
index 8f35cdf..76a8c8f 100644
--- a/src/dev/arm/smmu_v3.hh
+++ b/src/dev/arm/smmu_v3.hh
@@ -90,7 +90,7 @@
 const System &system;
 const MasterID masterId;

-SMMUMasterPortmasterPort;
+SMMUMasterPortrequestPort;
 SMMUMasterTableWalkPort masterTableWalkPort;
 SMMUControlPort   controlPort;

@@ -108,7 +108,7 @@
 const bool walkCacheNonfinalEnable;
 const unsigned walkCacheS1Levels;
 const unsigned walkCacheS2Levels;
-const unsigned masterPortWidth; // in bytes
+const unsigned requestPortWidth; // in bytes

 SMMUSemaphore tlbSem;
 SMMUSemaphore ifcSmmuSem;
@@ -116,7 +116,7 @@
 SMMUSemaphore configSem;
 SMMUSemaphore ipaSem;
 SMMUSemaphore walkSem;
-SMMUSemaphore masterPortSem;
+SMMUSemaphore requestPortSem;

 SMMUSemaphore transSem; // max N transactions in SMMU
 SMMUSemaphore ptwSem;

[gem5-dev] Change in gem5/gem5[develop]: systemc: Update master/slave variables

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33525 )



Change subject: systemc: Update master/slave variables
..

systemc: Update master/slave variables

Change-Id: Ibcfeeeb134354dec9c9c5598248721cd58d3af01
---
M src/systemc/tests/tlm/multi_sockets/MultiSocketSimpleSwitchAT.h
M src/systemc/tlm_bridge/TlmBridge.py
2 files changed, 3 insertions(+), 3 deletions(-)



diff --git  
a/src/systemc/tests/tlm/multi_sockets/MultiSocketSimpleSwitchAT.h  
b/src/systemc/tests/tlm/multi_sockets/MultiSocketSimpleSwitchAT.h

index 3e03db3..f43218f 100644
--- a/src/systemc/tests/tlm/multi_sockets/MultiSocketSimpleSwitchAT.h
+++ b/src/systemc/tests/tlm/multi_sockets/MultiSocketSimpleSwitchAT.h
@@ -34,7 +34,7 @@
 This class is a simple crossbar switch through which an arbitrary number  
of initiators

 may communicate in parallel as long as they do not talk to the same target.

-If two masters address the same target at the same point of time,
+If two requestors address the same target at the same point of time,
 the choice who will be allowed to communicate
 is done non-deterministically (based on the SystemC process exectution  
order).


diff --git a/src/systemc/tlm_bridge/TlmBridge.py  
b/src/systemc/tlm_bridge/TlmBridge.py

index 1851464..0a2aaa7 100644
--- a/src/systemc/tlm_bridge/TlmBridge.py
+++ b/src/systemc/tlm_bridge/TlmBridge.py
@@ -37,7 +37,7 @@

 system = Param.System(Parent.any, "system")

-gem5 = ResponsePort('gem5 slave port')
+gem5 = ResponsePort('gem5 response port')
 addr_ranges = VectorParam.AddrRange([],
 'Addresses served by this port\'s TLM side')

@@ -49,7 +49,7 @@

 system = Param.System(Parent.any, "system")

-gem5 = RequestPort('gem5 master port')
+gem5 = RequestPort('gem5 request port')


 class Gem5ToTlmBridge32(Gem5ToTlmBridgeBase):

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[gem5-dev] Change in gem5/gem5[develop]: dev: Update instances of masterId

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33531 )



Change subject: dev: Update instances of masterId
..

dev: Update instances of masterId

Change-Id: Iad83557e2b459c45a8c1e1c78148fd32c37ed651
---
M src/dev/dma_device.cc
M src/dev/dma_device.hh
2 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 03882e3..97e0eff 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -52,7 +52,7 @@
 DmaPort::DmaPort(ClockedObject *dev, System *s,
  uint32_t sid, uint32_t ssid)
 : RequestPort(dev->name() + ".dma", dev),
-  device(dev), sys(s), masterId(s->getMasterId(dev)),
+  device(dev), sys(s), _id(s->getMasterId(dev)),
   sendEvent([this]{ sendDma(); }, dev->name()),
   pendingCount(0), inRetry(false),
   defaultSid(sid),
@@ -166,7 +166,7 @@
  !gen.done(); gen.next()) {

 req = std::make_shared(
-gen.addr(), gen.size(), flag, masterId);
+gen.addr(), gen.size(), flag, _id);

 req->setStreamId(sid);
 req->setSubStreamId(ssid);
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 56c8d4c..c590a77 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -114,7 +114,7 @@
 System *const sys;

 /** Id for all requests */
-const MasterID masterId;
+const MasterID _id;

   protected:
 /** Use a deque as we never do any insertion or removal in the middle  
*/


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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Update instances of masterId

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33526 )



Change subject: arch-arm: Update instances of masterId
..

arch-arm: Update instances of masterId

smmu files

Change-Id: I0c1116ee954bd536b9beb7b832ce0e11ebc7eb77
---
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
6 files changed, 17 insertions(+), 17 deletions(-)



diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index 745bb0f..1378cf9 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -49,13 +49,13 @@
 Stage2MMU::Stage2MMU(const Params *p)
 : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
   port(_stage1Tlb->getTableWalker(), p->sys),
-  masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()))
+  _id(p->sys->getMasterId(_stage1Tlb->getTableWalker()))
 {
 // we use the stage-one table walker as the parent of the port,
 // and to get our master id, this is done to keep things
 // symmetrical with other ISAs in terms of naming and stats
-stage1Tlb()->setMMU(this, masterId);
-stage2Tlb()->setMMU(this, masterId);
+stage1Tlb()->setMMU(this, _id);
+stage2Tlb()->setMMU(this, _id);
 }

 Fault
@@ -66,7 +66,7 @@

 // translate to physical address using the second stage MMU
 auto req = std::make_shared();
-req->setVirt(descAddr, numBytes, flags | Request::PT_WALK, masterId,  
0);

+req->setVirt(descAddr, numBytes, flags | Request::PT_WALK, _id, 0);
 if (isFunctional) {
 fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read);
 } else {
@@ -102,7 +102,7 @@
 {
 // translate to physical address using the second stage MMU
 translation->setVirt(
-descAddr, numBytes, flags | Request::PT_WALK, masterId);
+descAddr, numBytes, flags | Request::PT_WALK, _id);
 translation->translateTiming(tc);
 }

diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index 0ac7abe..ef6e7cb 100644
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -60,7 +60,7 @@
 DmaPort port;

 /** Request id for requests generated by this MMU */
-MasterID masterId;
+MasterID _id;

   public:
 /** This translation class is used to trigger the data fetch once a  
timing

@@ -88,10 +88,10 @@
 finish(const Fault &fault, const RequestPtr &req, ThreadContext  
*tc,

BaseTLB::Mode mode);

-void setVirt(Addr vaddr, int size, Request::Flags flags, int  
masterId)

+void setVirt(Addr vaddr, int size, Request::Flags flags, int _id)
 {
 numBytes = size;
-req->setVirt(vaddr, size, flags, masterId, 0);
+req->setVirt(vaddr, size, flags, _id, 0);
 }

 void translateTiming(ThreadContext *tc)
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 1c89c22..e9502f8 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -55,7 +55,7 @@

 TableWalker::TableWalker(const Params *p)
 : ClockedObject(p),
-  stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId),
+  stage2Mmu(NULL), port(NULL), _id(Request::invldMasterId),
   isStage2(p->is_stage2), tlb(NULL),
   currState(NULL), pending(false),
   numSquashable(p->num_squash_per_cycle),
@@ -97,11 +97,11 @@
 }

 void
-TableWalker::setMMU(Stage2MMU *m, MasterID master_id)
+TableWalker::setMMU(Stage2MMU *m, MasterID unique_id)
 {
 stage2Mmu = m;
 port = &m->getDMAPort();
-masterId = master_id;
+_id = unique_id;
 }

 void
@@ -2122,7 +2122,7 @@
 (this->*doDescriptor)();
 } else {
 RequestPtr req = std::make_shared(
-descAddr, numBytes, flags, masterId);
+descAddr, numBytes, flags, _id);

 req->taskId(ContextSwitchTaskId::DMA);
 PacketPtr  pkt = new Packet(req, MemCmd::ReadReq);
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 6f04149..1d2b3f1 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -830,7 +830,7 @@
 DmaPort* port;

 /** Master id assigned by the MMU. */
-MasterID masterId;
+MasterID _id;

 /** Indicates whether this table walker is part of the stage 2 mmu */
 const bool isStage2;
@@ -912,7 +912,7 @@

 void setTlb(TLB *_tlb) { tlb = _tlb; }
 TLB* getTlb() { return tlb; }
-void setMMU(Stage2MMU *m, MasterID master_id);
+void setMMU(Stage2MMU *m, MasterID unique_id);
 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
   uint8_t texcb, bool s);
 void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 1d43a0d..f253dd9 100644
--- a/src/ar

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Update instances of masterId

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33527 )



Change subject: arch-riscv: Update instances of masterId
..

arch-riscv: Update instances of masterId

Change-Id: I0f90e0ddb231dd5c592fc3821d0cf3771857c6ac
---
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/pagetable_walker.hh
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/pagetable_walker.hh
4 files changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/arch/riscv/pagetable_walker.cc  
b/src/arch/riscv/pagetable_walker.cc

index 786cb81..39d3ed2 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -396,7 +396,7 @@
 else {
 //If we didn't return, we're setting up another read.
 RequestPtr request = std::make_shared(
-nextRead, oldRead->getSize(), flags, walker->masterId);
+nextRead, oldRead->getSize(), flags, walker->_id);
 read = new Packet(request, MemCmd::ReadReq);
 read->allocate();

@@ -435,7 +435,7 @@

 Request::Flags flags = Request::PHYSICAL;
 RequestPtr request = std::make_shared(
-topAddr, sizeof(PTESv39), flags, walker->masterId);
+topAddr, sizeof(PTESv39), flags, walker->_id);

 read = new Packet(request, MemCmd::ReadReq);
 read->allocate();
diff --git a/src/arch/riscv/pagetable_walker.hh  
b/src/arch/riscv/pagetable_walker.hh

index d9ab569..9b564e2 100644
--- a/src/arch/riscv/pagetable_walker.hh
+++ b/src/arch/riscv/pagetable_walker.hh
@@ -166,7 +166,7 @@
 // The TLB we're supposed to load.
 TLB * tlb;
 System * sys;
-MasterID masterId;
+MasterID _id;

 // The number of outstanding walks that can be squashed per cycle.
 unsigned numSquashable;
@@ -202,7 +202,7 @@
 Walker(const Params *params) :
 ClockedObject(params), port(name() + ".port", this),
 funcState(this, NULL, NULL, true), tlb(NULL),  
sys(params->system),

-masterId(sys->getMasterId(this)),
+_id(sys->getMasterId(this)),
 numSquashable(params->num_squash_per_cycle),
 startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
 {
diff --git a/src/arch/x86/pagetable_walker.cc  
b/src/arch/x86/pagetable_walker.cc

index b540be3..940a96f 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -519,7 +519,7 @@
 Request::Flags flags = oldRead->req->getFlags();
 flags.set(Request::UNCACHEABLE, uncacheable);
 RequestPtr request = std::make_shared(
-nextRead, oldRead->getSize(), flags, walker->masterId);
+nextRead, oldRead->getSize(), flags, walker->_id);
 read = new Packet(request, MemCmd::ReadReq);
 read->allocate();
 // If we need to write, adjust the read packet to write the  
modified

@@ -588,7 +588,7 @@
 flags.set(Request::UNCACHEABLE);

 RequestPtr request = std::make_shared(
-topAddr, dataSize, flags, walker->masterId);
+topAddr, dataSize, flags, walker->_id);

 read = new Packet(request, MemCmd::ReadReq);
 read->allocate();
diff --git a/src/arch/x86/pagetable_walker.hh  
b/src/arch/x86/pagetable_walker.hh

index 55bb098..237950c 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -168,7 +168,7 @@
 // The TLB we're supposed to load.
 TLB * tlb;
 System * sys;
-MasterID masterId;
+MasterID _id;

 // The number of outstanding walks that can be squashed per cycle.
 unsigned numSquashable;
@@ -204,7 +204,7 @@
 Walker(const Params *params) :
 ClockedObject(params), port(name() + ".port", this),
 funcState(this, NULL, NULL, true), tlb(NULL),  
sys(params->system),

-masterId(sys->getMasterId(this)),
+_id(sys->getMasterId(this)),
 numSquashable(params->num_squash_per_cycle),
 startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
 {

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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Update instances of masterId

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33529 )



Change subject: dev-arm: Update instances of masterId
..

dev-arm: Update instances of masterId

Change-Id: I360068d315ca9b87b7e3489c4e1c8f250d808cc3
---
M src/dev/arm/gic_v3_its.cc
M src/dev/arm/gic_v3_its.hh
2 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/dev/arm/gic_v3_its.cc b/src/dev/arm/gic_v3_its.cc
index 442008f..3fdd42b 100644
--- a/src/dev/arm/gic_v3_its.cc
+++ b/src/dev/arm/gic_v3_its.cc
@@ -89,7 +89,7 @@
 a.type = ItsActionType::SEND_REQ;

 RequestPtr req = std::make_shared(
-addr, size, 0, its.masterId);
+addr, size, 0, its._id);

 req->taskId(ContextSwitchTaskId::DMA);

@@ -113,7 +113,7 @@
 a.type = ItsActionType::SEND_REQ;

 RequestPtr req = std::make_shared(
-addr, size, 0, its.masterId);
+addr, size, 0, its._id);

 req->taskId(ContextSwitchTaskId::DMA);

@@ -779,7 +779,7 @@
gitsCbaser(0), gitsCreadr(0),
gitsCwriter(0), gitsIidr(0),
tableBases(NUM_BASER_REGS, 0),
-   masterId(params->system->getMasterId(this)),
+   _id(params->system->getMasterId(this)),
gic(nullptr),
commandEvent([this] { checkCommandQueue(); }, name()),
pendingCommands(false),
diff --git a/src/dev/arm/gic_v3_its.hh b/src/dev/arm/gic_v3_its.hh
index 54beb3e..853722f 100644
--- a/src/dev/arm/gic_v3_its.hh
+++ b/src/dev/arm/gic_v3_its.hh
@@ -319,7 +319,7 @@

   private:
 std::queue packetsToRetry;
-uint32_t masterId;
+uint32_t _id;
 Gicv3 *gic;
 EventFunctionWrapper commandEvent;


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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Update instances of masterId

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33532 )



Change subject: gpu-compute: Update instances of masterId
..

gpu-compute: Update instances of masterId

Change-Id: If37fdf0103a95f397b204d82ec1db9d671e9e716
---
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
2 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index 9a41233..ad68edd 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -94,7 +94,7 @@
 countPages(p->countPages),
 req_tick_latency(p->mem_req_latency * p->clk_domain->clockPeriod()),
 resp_tick_latency(p->mem_resp_latency * p->clk_domain->clockPeriod()),
-_masterId(p->system->getMasterId(this, "ComputeUnit")),
+_id(p->system->getMasterId(this, "ComputeUnit")),
 lds(*p->localDataStore), gmTokenPort(name() + ".gmTokenPort", this),
 _cacheLineSize(p->system->cacheLineSize()),
 _numBarrierSlots(p->num_barrier_slots),
diff --git a/src/gpu-compute/compute_unit.hh  
b/src/gpu-compute/compute_unit.hh

index 211dd53..b47a6e0 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -458,13 +458,13 @@
 void processFetchReturn(PacketPtr pkt);
 void updatePageDivergenceDist(Addr addr);

-MasterID masterId() { return _masterId; }
+MasterID masterId() { return _id; }

 bool isDone() const;
 bool isVectorAluIdle(uint32_t simdId) const;

   protected:
-MasterID _masterId;
+MasterID _id;

 LdsState &lds;


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[gem5-dev] Change in gem5/gem5[develop]: cpu: Update instances of masterId

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33528 )



Change subject: cpu: Update instances of masterId
..

cpu: Update instances of masterId

Change-Id: Ied470bb9a08cb7676a2fce20d9c5349c2af8ade0
---
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/testers/directedtest/DirectedGenerator.cc
M src/cpu/testers/directedtest/DirectedGenerator.hh
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/testers/traffic_gen/base_gen.cc
M src/cpu/testers/traffic_gen/base_gen.hh
M src/cpu/testers/traffic_gen/dram_gen.cc
M src/cpu/testers/traffic_gen/dram_gen.hh
M src/cpu/testers/traffic_gen/dram_rot_gen.hh
M src/cpu/testers/traffic_gen/exit_gen.hh
M src/cpu/testers/traffic_gen/idle_gen.hh
M src/cpu/testers/traffic_gen/linear_gen.hh
M src/cpu/testers/traffic_gen/random_gen.hh
M src/cpu/testers/traffic_gen/trace_gen.hh
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
27 files changed, 69 insertions(+), 69 deletions(-)



diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index b016938..7fc18dd 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -58,7 +58,7 @@
 void
 CheckerCPU::init()
 {
-masterId = systemPtr->getMasterId(this);
+_id = systemPtr->getMasterId(this);
 }

 CheckerCPU::CheckerCPU(Params *p)
@@ -154,13 +154,13 @@
 auto it_end = byte_enable.cbegin() + (size - size_left);
 if (isAnyActiveElement(it_start, it_end)) {
 mem_req = std::make_shared(frag_addr, frag_size,
-flags, masterId, thread->pcState().instAddr(),
+flags, _id, thread->pcState().instAddr(),
 tc->contextId());
 mem_req->setByteEnable(std::vector(it_start, it_end));
 }
 } else {
 mem_req = std::make_shared(frag_addr, frag_size,
-flags, masterId, thread->pcState().instAddr(),
+flags, _id, thread->pcState().instAddr(),
 tc->contextId());
 }

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3c04064..209dcfa 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -89,7 +89,7 @@
 using VecRegContainer = TheISA::VecRegContainer;

 /** id attached to all issued requests */
-MasterID masterId;
+MasterID _id;
   public:
 void init() override;

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 0656035..2b6058f 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -238,11 +238,11 @@
 if (!curMacroStaticInst) {
 // set up memory request for instruction fetch
 auto mem_req = std::make_shared(
-fetch_PC, sizeof(MachInst), 0, masterId, fetch_PC,
+fetch_PC, sizeof(MachInst), 0, _id, fetch_PC,
 thread->contextId());

 mem_req->setVirt(fetch_PC, sizeof(MachInst),
- Request::INST_FETCH, masterId,
+ Request::INST_FETCH, _id,
  thread->instAddr());

 fault = itb->translateFunctional(
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc  
b/src/cpu/testers/directedtest/DirectedGenerator.cc

index 2d76b86..3502783 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.cc
+++ b/src/cpu/testers/directedtest/DirectedGenerator.cc
@@ -33,7 +33,7 @@

 DirectedGenerator::DirectedGenerator(const Params *p)
 : SimObject(p),
-  masterId(p->system->getMasterId(this))
+  _id(p->system->getMasterId(this))
 {
 m_num_cpus = p->num_cpus;
 m_directed_tester = NULL;
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh  
b/src/cpu/testers/directedtest/DirectedGenerator.hh

index 2d03372..0f17ce1 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.hh
+++ b/src/cpu/testers/directedtest/DirectedGenerator.hh
@@ -49,7 +49,7 @@

   protected:
 int m_num_cpus;
-MasterID masterId;
+MasterID _id;
 RubyDirectedTester* m_directed_tester;
 };

diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc  
b/src/cpu/testers/directedtest/InvalidateGenerator.cc

index 5640163..9956e88 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -60,7 +60,7 @@
 Packet::Command cmd;

 // For simplicity, requests ar

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Update instances of masterId - smmu

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33530 )



Change subject: dev-arm: Update instances of masterId - smmu
..

dev-arm: Update instances of masterId - smmu

smmu files

Change-Id: If766fcc7b6a06420215e814e9a94bfd33b704a0c
---
M src/dev/arm/SMMUv3.py
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3.hh
M src/dev/arm/smmu_v3_ports.hh
M src/dev/arm/smmu_v3_proc.cc
M src/dev/arm/smmu_v3_slaveifc.cc
M src/dev/arm/smmu_v3_slaveifc.hh
M src/dev/arm/smmu_v3_transl.cc
8 files changed, 111 insertions(+), 103 deletions(-)



diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 0b9ab21..ff13139 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -43,9 +43,16 @@
 type = 'SMMUv3SlaveInterface'
 cxx_header = 'dev/arm/smmu_v3_slaveifc.hh'

-slave = ResponsePort('Device port')
-ats_master = RequestPort('ATS master port')
-ats_slave  = ResponsePort('ATS slave port')
+responder = ResponsePort('Device port')
+slave = DeprecatedParam(responder, '`slave` is now called  
`responder`')

+ats_mem_side = RequestPort('ATS mem_side port,'
+'sends requests and receives responses')
+ats_master   = DeprecatedParam(ats_mem_side,
+'`ats_master` is now called  
`ats_mem_side`')

+ats_cpu_side  = ResponsePort('ATS cpu_side port,'
+'sends responses and receives requests')
+ats_slave = DeprecatedParam(ats_cpu_side,
+'`ats_slave` is now called `ats_cpu_side`')

 port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')
 wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)')
@@ -74,18 +81,19 @@
 type = 'SMMUv3'
 cxx_header = 'dev/arm/smmu_v3.hh'

-master = RequestPort('Master port')
-master_walker = RequestPort(
-'Master port for SMMU initiated HWTW requests (optional)')
+requestor = RequestPort('Request port')
+requestor_walker = RequestPort(
+'Request port for SMMU initiated HWTW requests (optional)')
 control = ResponsePort(
 'Control port for accessing memory-mapped registers')
 sample_period = Param.Clock('10us', 'Stats sample period')
 reg_map = Param.AddrRange('Address range for control registers')
 system = Param.System(Parent.any, "System this device is part of")

-slave_interfaces = VectorParam.SMMUv3SlaveInterface([], "Slave  
interfaces")

+responder_interfaces = VectorParam.SMMUv3SlaveInterface([],
+"Responder interfaces")

-# SLAVE INTERFACE<->SMMU link parameters
+# RESPONDER INTERFACE<->SMMU link parameters
 ifc_smmu_lat = Param.Cycles(8, 'IFC to SMMU communication latency')
 smmu_ifc_lat = Param.Cycles(8, 'SMMU to IFC communication latency')

@@ -93,8 +101,8 @@
 xlate_slots = Param.Unsigned(64, 'SMMU translation slots')
 ptw_slots = Param.Unsigned(16, 'SMMU page table walk slots')

-master_port_width = Param.Unsigned(16,
-'Master port width in bytes (= 1 beat)')
+request_port_width = Param.Unsigned(16,
+'Request port width in bytes (= 1 beat)')

 tlb_entries = Param.Unsigned(2048, 'TLB size (entries)')
 tlb_assoc = Param.Unsigned(4, 'TLB associativity (0=full)')
@@ -185,23 +193,23 @@

 def connect(self, device):
 """
-Helper method used to connect the SMMU. The master could
+Helper method used to connect the SMMU. The requestor could
 be either a dma port (if the SMMU is attached directly to a
-dma device), or to a master port (this is the case where the SMMU
+dma device), or to a request port (this is the case where the SMMU
 is attached to a bridge).
 """

-slave_interface = SMMUv3SlaveInterface()
+responder_interface = SMMUv3SlaveInterface()

-if hasattr(device, "master"):
-slave_interface.slave = device.master
+if hasattr(device, "requestor"):
+responder_interface.responder = device.requestor
 elif hasattr(device, "dma"):
-slave_interface.slave = device.dma
+responder_interface.responder = device.dma
 else:
 print("Unable to attach SMMUv3\n")
 sys.exit(1)

-self.slave_interfaces.append(slave_interface)
+self.responder_interfaces.append(responder_interface)

 # Storing a reference to the smmu to be used when generating
 # the binding in the device DTB.
diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index d3d8a53..2822cb9 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -119,14 +119,14 @@
 // store an unallowed values or if the are configuration conflicts.
 warn("SMMUv3 IDx register values unchecked\n");

-for (auto ifc : slaveInterfaces

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Update instances of masterId

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33533 )



Change subject: mem-cache: Update instances of masterId
..

mem-cache: Update instances of masterId

Change-Id: Ia7fb3472d6013ea2c8b993434c82cdda3501c966
---
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/tags/base.cc
5 files changed, 15 insertions(+), 15 deletions(-)



diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index d4223aa..9306dc4 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -57,7 +57,7 @@

 Base::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr, bool miss)
   : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
-masterId(pkt->req->masterId()), validPC(pkt->req->hasPC()),
+_id(pkt->req->masterId()), validPC(pkt->req->hasPC()),
 secure(pkt->isSecure()), size(pkt->req->getSize()),  
write(pkt->isWrite()),

 paddress(pkt->req->getPaddr()), cacheMiss(miss)
 {
@@ -72,7 +72,7 @@
 }

 Base::PrefetchInfo::PrefetchInfo(PrefetchInfo const &pfi, Addr addr)
-  : address(addr), pc(pfi.pc), masterId(pfi.masterId),  
validPC(pfi.validPC),

+  : address(addr), pc(pfi.pc), _id(pfi._id), validPC(pfi.validPC),
 secure(pfi.secure), size(pfi.size), write(pfi.write),
 paddress(pfi.paddress), cacheMiss(pfi.cacheMiss), data(nullptr)
 {
@@ -92,7 +92,7 @@
 : ClockedObject(p), listeners(), cache(nullptr),  
blkSize(p->block_size),

   lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
   onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
-  masterId(p->sys->getMasterId(this)),  
pageBytes(p->sys->getPageBytes()),

+  _id(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()),
   prefetchOnAccess(p->prefetch_on_access),
   useVirtualAddresses(p->use_virtual_addresses), issuedPrefetches(0),
   usefulPrefetches(0), tlb(nullptr)
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 7009db7..5bf4ed8 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -94,7 +94,7 @@
 /** The program counter that generated this address. */
 Addr pc;
 /** The requestor ID that generated this address. */
-MasterID masterId;
+MasterID _id;
 /** Validity bit for the PC of this address. */
 bool validPC;
 /** Whether this address targets the secure memory space. */
@@ -154,7 +154,7 @@
  */
 MasterID getMasterId() const
 {
-return masterId;
+return _id;
 }

 /**
@@ -281,7 +281,7 @@
 const bool onInst;

 /** Request id for prefetches */
-const MasterID masterId;
+const MasterID _id;

 const Addr pageBytes;

diff --git a/src/mem/cache/prefetch/queued.cc  
b/src/mem/cache/prefetch/queued.cc

index c2ae090..681fd7c 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -291,7 +291,7 @@
 } else {
 Tick pf_time = curTick() + clockPeriod() * latency;
 it->createPkt(it->translationRequest->getPaddr(), blkSize,
-masterId, tagPrefetch, pf_time);
+_id, tagPrefetch, pf_time);
 addToQueue(pfq, *it);
 }
 } else {
@@ -342,7 +342,7 @@
 PacketPtr pkt)
 {
 RequestPtr translation_req = std::make_shared(
-addr, blkSize, pkt->req->getFlags(), masterId, pfi.getPC(),
+addr, blkSize, pkt->req->getFlags(), _id, pfi.getPC(),
 pkt->req->contextId());
 translation_req->setFlags(Request::PREFETCH);
 return translation_req;
@@ -431,7 +431,7 @@
 DeferredPacket dpp(this, new_pfi, 0, priority);
 if (has_target_pa) {
 Tick pf_time = curTick() + clockPeriod() * latency;
-dpp.createPkt(target_paddr, blkSize, masterId, tagPrefetch,  
pf_time);

+dpp.createPkt(target_paddr, blkSize, _id, tagPrefetch, pf_time);
 DPRINTF(HWPrefetch, "Prefetch queued. "
 "addr:%#x priority: %3d tick:%lld.\n",
 new_pfi.getAddr(), priority, pf_time);
diff --git a/src/mem/cache/prefetch/stride.cc  
b/src/mem/cache/prefetch/stride.cc

index 36773c6..e6544db 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -124,10 +124,10 @@
 Addr pf_addr = pfi.getAddr();
 Addr pc = pfi.getPC();
 bool is_secure = pfi.isSecure();
-MasterID master_id = useMasterId ? pfi.getMasterId() : 0;
+MasterID unique_id = useMasterId ? pfi.getMasterId() : 0;

 // Get corresponding pc table
-PCTable* pcTable = findTable(master_id);
+PCTable* pcTable = findTable(unique_id);

 // Search for entry in the pc table
 StrideEnt

[gem5-dev] Change in gem5/gem5[develop]: mem: Update instances of masterId

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33534 )



Change subject: mem: Update instances of masterId
..

mem: Update instances of masterId

Change-Id: If2b70dd98a57cf879349df467fd65c64dcec55b9
---
M src/mem/dram_ctrl.hh
M src/mem/external_master.cc
M src/mem/external_master.hh
M src/mem/qos/q_policy.cc
4 files changed, 9 insertions(+), 9 deletions(-)



diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 78a50fd..778d9fa 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -618,7 +618,7 @@
 const PacketPtr pkt;

 /** MasterID associated with the packet */
-const MasterID _masterId;
+const MasterID _requestorId;

 const bool read;

@@ -677,7 +677,7 @@
  * Get the packet MasterID
  * (interface compatibility with Packet)
  */
-inline MasterID masterId() const { return _masterId; }
+inline MasterID masterId() const { return _requestorId; }

 /**
  * Get the packet size
@@ -708,7 +708,7 @@
uint32_t _row, uint16_t bank_id, Addr _addr,
unsigned int _size, Bank& bank_ref, Rank& rank_ref)
 : entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
-  _masterId(pkt->masterId()),
+  _requestorId(pkt->masterId()),
   read(is_read), rank(_rank), bank(_bank), row(_row),
   bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
   bankRef(bank_ref), rankRef(rank_ref),  
_qosValue(_pkt->qosValue())

diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc
index 1a1ec40..9cee9e7 100644
--- a/src/mem/external_master.cc
+++ b/src/mem/external_master.cc
@@ -53,7 +53,7 @@
 portName(params->name + ".port"),
 portType(params->port_type),
 portData(params->port_data),
-masterId(params->system->getMasterId(this))
+_id(params->system->getMasterId(this))
 {}

 Port &
diff --git a/src/mem/external_master.hh b/src/mem/external_master.hh
index fb289a6..1099489 100644
--- a/src/mem/external_master.hh
+++ b/src/mem/external_master.hh
@@ -128,7 +128,7 @@

 void init() override;

-const MasterID masterId;
+const MasterID _id;
 };


diff --git a/src/mem/qos/q_policy.cc b/src/mem/qos/q_policy.cc
index e8235dc..21fe88f 100644
--- a/src/mem/qos/q_policy.cc
+++ b/src/mem/qos/q_policy.cc
@@ -119,10 +119,10 @@
 DPRINTF(QOS, "QoSQPolicy::lrg evaluating alternative "
  "unique id %d\n", uniqueId);

-if (track.find(masterId) != track.end()) {
-ret = track[masterId];
-DPRINTF(QOS, "QoSQPolicy::lrg master id "
- "%d selected for service\n", masterId);
+if (track.find(uniqueId) != track.end()) {
+ret = track[uniqueId];
+DPRINTF(QOS, "QoSQPolicy::lrg unique id "
+ "%d selected for service\n", uniqueId);

 return ret;
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33534
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If2b70dd98a57cf879349df467fd65c64dcec55b9
Gerrit-Change-Number: 33534
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Update master/slave and masterId --system.cc

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33538 )



Change subject: sim: Update master/slave and masterId --system.cc
..

sim: Update master/slave and masterId --system.cc

system.cc

Change-Id: I25468cbd4bb201d4c74791610d0a0e07562da707
---
M src/sim/system.cc
M src/sim/system.hh
2 files changed, 67 insertions(+), 64 deletions(-)



diff --git a/src/sim/system.cc b/src/sim/system.cc
index ac4ebed..a711ce7 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -246,7 +246,7 @@
   _cacheLineSize == 64 || _cacheLineSize == 128))
 warn_once("Cache line size is neither 16, 32, 64 nor 128  
bytes.\n");


-// Get the generic system master IDs
+// Get the generic system unique IDs
 MasterID tmp_id M5_VAR_USED;
 tmp_id = getMasterId(this, "writebacks");
 assert(tmp_id == Request::wbUniqueId);
@@ -420,28 +420,28 @@
 }

 void
-System::addDeviceMemory(MasterID masterId, AbstractMemory *deviceMemory)
+System::addDeviceMemory(MasterID unique_id, AbstractMemory *deviceMemory)
 {
-if (!deviceMemMap.count(masterId)) {
-deviceMemMap.insert(std::make_pair(masterId, deviceMemory));
+if (!deviceMemMap.count(unique_id)) {
+deviceMemMap.insert(std::make_pair(unique_id, deviceMemory));
 }
 }

 bool
 System::isDeviceMemAddr(PacketPtr pkt) const
 {
-const MasterID& mid = pkt->masterId();
+const MasterID& id = pkt->masterId();

-return (deviceMemMap.count(mid) &&
-deviceMemMap.at(mid)->getAddrRange().contains(pkt->getAddr()));
+return (deviceMemMap.count(id) &&
+deviceMemMap.at(id)->getAddrRange().contains(pkt->getAddr()));
 }

 AbstractMemory *
-System::getDeviceMemory(MasterID mid) const
+System::getDeviceMemory(MasterID id) const
 {
-panic_if(!deviceMemMap.count(mid),
- "No device memory found for MasterID %d\n", mid);
-return deviceMemMap.at(mid);
+panic_if(!deviceMemMap.count(id),
+ "No device memory found for MasterID %d\n", id);
+return deviceMemMap.at(id);
 }

 void
@@ -544,12 +544,12 @@
 }

 std::string
-System::stripSystemName(const std::string& master_name) const
+System::stripSystemName(const std::string& requestor_name) const
 {
-if (startswith(master_name, name())) {
-return master_name.substr(name().size());
+if (startswith(requestor_name, name())) {
+return requestor_name.substr(name().size());
 } else {
-return master_name;
+return requestor_name;
 }
 }

@@ -559,7 +559,7 @@
 MasterID id = Request::invldUniqueId;

 // number of occurrences of the SimObject pointer
-// in the master list.
+// in the requestor list.
 auto obj_number = 0;

 for (int i = 0; i < requestors.size(); i++) {
@@ -571,15 +571,15 @@

 fatal_if(obj_number > 1,
 "Cannot lookup MasterID by SimObject pointer: "
-"More than one master is sharing the same SimObject\n");
+"More than one requestor is sharing the same SimObject\n");

 return id;
 }

 MasterID
-System::lookupMasterId(const std::string& master_name) const
+System::lookupMasterId(const std::string& requestor_name) const
 {
-std::string name = stripSystemName(master_name);
+std::string name = stripSystemName(requestor_name);

 for (int i = 0; i < requestors.size(); i++) {
 if (requestors[i].req_name == name) {
@@ -591,22 +591,23 @@
 }

 MasterID
-System::getGlobalMasterId(const std::string& _name)
+System::getGlobalMasterId(const std::string& requestor_name)
 {
-return _getMasterId(nullptr, _name);
+return _getMasterId(nullptr, requestor_name);
 }

 MasterID
 System::getMasterId(const SimObject* requestor, std::string subrequestor)
 {
-auto name = leafMasterName(requestor, subrequestor);
-return _getMasterId(requestor, name);
+auto requestor_name = leafMasterName(requestor, subrequestor);
+return _getMasterId(requestor, requestor_name);
 }

 MasterID
-System::_getMasterId(const SimObject* requestor, const std::string& _name)
+System::_getMasterId(const SimObject* requestor,
+ const std::string& requestor_name)
 {
-std::string name = stripSystemName(_name);
+std::string name = stripSystemName(requestor_name);

 // CPUs in switch_cpus ask for ids again after switching
 for (int i = 0; i < requestors.size(); i++) {
@@ -620,27 +621,28 @@
 // they will be too small

 if (Stats::enabled()) {
-fatal("Can't request a masterId after regStats(). "
+fatal("Can't request a uniqueId after regStats(). "
 "You must do so in init().\n");
 }

 // Generate a new MasterID incrementally
-MasterID _id = requestors.size();
+MasterID unique_id = requestors.size();

 // Append the new Master metadata to the group of system Masters.
-requestors.emplace_back(requestor, name, _id);
+requestors

[gem5-dev] Change in gem5/gem5[develop]: mem: Update masterId and master/slave variables in MemCtrl obj

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33535 )



Change subject: mem: Update masterId and master/slave variables in MemCtrl  
obj

..

mem: Update masterId and master/slave variables in MemCtrl obj

Change-Id: If57b3a5c8dab3d96d7297d48d3466f3f2aa436f9
---
M src/mem/mem_master.hh
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
3 files changed, 98 insertions(+), 98 deletions(-)



diff --git a/src/mem/mem_master.hh b/src/mem/mem_master.hh
index 468cd11..64c73d7 100644
--- a/src/mem/mem_master.hh
+++ b/src/mem/mem_master.hh
@@ -47,24 +47,24 @@
 #include "sim/sim_object.hh"

 /**
- * The MasterInfo class contains data about a specific master.
+ * The MasterInfo class contains data about a specific requestor.
  */
 struct MasterInfo
 {
 MasterInfo(const SimObject* _obj,
-   std::string master_name,
-   MasterID master_id)
-  : obj(_obj), masterName(master_name), masterId(master_id)
+   std::string requestor_name,
+   MasterID unique_id)
+  : obj(_obj), req_name(requestor_name), _id(unique_id)
 {}

-/** SimObject related to the Master */
+/** SimObject related to the Requestor */
 const SimObject* obj;

-/** Master Name */
-std::string masterName;
+/** Requestor Name */
+std::string req_name;

-/** Master ID */
-MasterID masterId;
+/** Unique id */
+MasterID _id;
 };

 #endif // __MEM_MEM_MASTER_HH__
diff --git a/src/mem/qos/mem_ctrl.cc b/src/mem/qos/mem_ctrl.cc
index e8d1ce0..a38de58 100644
--- a/src/mem/qos/mem_ctrl.cc
+++ b/src/mem/qos/mem_ctrl.cc
@@ -83,18 +83,18 @@
 }

 void
-MemCtrl::logRequest(BusState dir, MasterID m_id, uint8_t qos,
+MemCtrl::logRequest(BusState dir, MasterID id, uint8_t qos,
 Addr addr, uint64_t entries)
 {
 // If needed, initialize all counters and statistics
-// for this master
-addMaster(m_id);
+// for this requestor
+addMaster(id);

 DPRINTF(QOS,
 "QoSMemCtrl::logRequest REQUESTOR %s [id %d] address %d"
 " prio %d this requestor q packets %d"
 " - queue size %d - requested entries %d\n",
-masters[m_id], m_id, addr, qos, packetPriorities[m_id][qos],
+requestors[id], id, addr, qos, packetPriorities[id][qos],
 (dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos],
 entries);

@@ -106,28 +106,28 @@
 totalWriteQueueSize += entries;
 }

-packetPriorities[m_id][qos] += entries;
+packetPriorities[id][qos] += entries;
 for (auto j = 0; j < entries; ++j) {
-requestTimes[m_id][addr].push_back(curTick());
+requestTimes[id][addr].push_back(curTick());
 }

 // Record statistics
-stats.avgPriority[m_id].sample(qos);
+stats.avgPriority[id].sample(qos);

 // Compute avg priority distance

-for (uint8_t i = 0; i < packetPriorities[m_id].size(); ++i) {
+for (uint8_t i = 0; i < packetPriorities[id].size(); ++i) {
 uint8_t distance =
-(abs(int(qos) - int(i))) * packetPriorities[m_id][i];
+(abs(int(qos) - int(i))) * packetPriorities[id][i];

 if (distance > 0) {
-stats.avgPriorityDistance[m_id].sample(distance);
+stats.avgPriorityDistance[id].sample(distance);
 DPRINTF(QOS,
 "QoSMemCtrl::logRequest REQUESTOR %s [id %d]"
 " registering priority distance %d for priority %d"
 " (packets %d)\n",
-masters[m_id], m_id, distance, i,
-packetPriorities[m_id][i]);
+requestors[id], id, distance, i,
+packetPriorities[id][i]);
 }
 }

@@ -140,17 +140,17 @@
 }

 void
-MemCtrl::logResponse(BusState dir, MasterID m_id, uint8_t qos,
+MemCtrl::logResponse(BusState dir, MasterID id, uint8_t qos,
  Addr addr, uint64_t entries, double delay)
 {
-panic_if(!hasMaster(m_id),
-"Logging response with invalid master\n");
+panic_if(!hasMaster(id),
+"Logging response with invalid requestor\n");

 DPRINTF(QOS,
 "QoSMemCtrl::logResponse REQUESTOR %s [id %d] address %d prio"
 " %d this requestor q packets %d"
 " - queue size %d - requested entries %d\n",
-masters[m_id], m_id, addr, qos, packetPriorities[m_id][qos],
+requestors[id], id, addr, qos, packetPriorities[id][qos],
 (dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos],
 entries);

@@ -162,17 +162,17 @@
 totalWriteQueueSize -= entries;
 }

-panic_if(packetPriorities[m_id][qos] == 0,
- "QoSMemCtrl::logResponse master %s negative packets for  
priority"

- " %d", masters[m_id], qos);
+panic_if(packetPriorities[id][qos] == 0,
+

[gem5-dev] Change in gem5/gem5[develop]: systemc: Update instances of masterId

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33539 )



Change subject: systemc: Update instances of masterId
..

systemc: Update instances of masterId

Change-Id: Id6ba9557b4208299ce3023f929e4d26bc3855af0
---
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/tlm_bridge/tlm_to_gem5.hh
2 files changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc  
b/src/systemc/tlm_bridge/tlm_to_gem5.cc

index e6cb483..45ceb79 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -67,7 +67,7 @@
 {

 PacketPtr
-payload2packet(MasterID masterId, tlm::tlm_generic_payload &trans)
+payload2packet(MasterID _id, tlm::tlm_generic_payload &trans)
 {
 MemCmd cmd;

@@ -87,7 +87,7 @@

 Request::Flags flags;
 auto req = std::make_shared(
-trans.get_address(), trans.get_data_length(), flags, masterId);
+trans.get_address(), trans.get_data_length(), flags, _id);

 /*
  * Allocate a new Packet. The packet will be deleted when it returns  
from

@@ -156,7 +156,7 @@
 extension->setPipeThrough();
 pkt = extension->getPacket();
 } else {
-pkt = payload2packet(masterId, trans);
+pkt = payload2packet(_id, trans);
 }

 auto tlmSenderState = new TlmSenderState(trans);
@@ -274,7 +274,7 @@
 extension->setPipeThrough();
 pkt = extension->getPacket();
 } else {
-pkt = payload2packet(masterId, trans);
+pkt = payload2packet(_id, trans);
 }

 MemBackdoorPtr backdoor = nullptr;
@@ -311,7 +311,7 @@
 extension->setPipeThrough();
 bmp.sendFunctional(extension->getPacket());
 } else {
-auto pkt = payload2packet(masterId, trans);
+auto pkt = payload2packet(_id, trans);
 if (pkt) {
 bmp.sendFunctional(pkt);
 destroyPacket(pkt);
@@ -337,7 +337,7 @@
 extension->setPipeThrough();
 pkt = extension->getPacket();
 } else {
-pkt = payload2packet(masterId, trans);
+pkt = payload2packet(_id, trans);
 pkt->req->setFlags(Request::NO_ACCESS);
 }

@@ -470,7 +470,7 @@
 bmp(std::string(name()) + "master", *this), socket("tlm_socket"),
 wrapper(socket, std::string(name()) + ".tlm", InvalidPortID),
 system(params->system),
-masterId(params->system->getGlobalMasterId(
+_id(params->system->getGlobalMasterId(
 std::string("[systemc].") + name()))
 {
 }
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.hh  
b/src/systemc/tlm_bridge/tlm_to_gem5.hh

index e2e7540..b060da8 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.hh
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.hh
@@ -171,7 +171,7 @@

 void before_end_of_elaboration() override;

-const MasterID masterId;
+const MasterID _id;
 };

 } // namespace sc_gem5

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Id6ba9557b4208299ce3023f929e4d26bc3855af0
Gerrit-Change-Number: 33539
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Update master/slave and masterId in request.hh

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33536 )



Change subject: mem: Update master/slave and masterId in request.hh
..

mem: Update master/slave and masterId in request.hh

Change-Id: I4af248c241078a9cb6e22a9258c39856119a2622
---
M src/arch/arm/isa.cc
M src/arch/arm/table_walker.cc
M src/arch/arm/tracers/tarmac_parser.cc
M src/dev/x86/intdev.hh
M src/mem/cache/base.cc
M src/mem/cache/cache.cc
M src/mem/cache/cache_blk.hh
M src/mem/port.cc
M src/mem/port_proxy.cc
M src/mem/qos/policy_pf.cc
M src/mem/request.hh
M src/mem/ruby/system/CacheRecorder.cc
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/RubySystem.cc
M src/mem/translating_port_proxy.cc
M src/sim/system.cc
M src/sim/system.hh
18 files changed, 85 insertions(+), 83 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6ef9fe3..b1ae705 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2339,7 +2339,7 @@
 warn_once("Doing AT (address translation) in functional mode! Fix  
Me!\n");


 auto req = std::make_shared(
-val, 0, flags,  Request::funcMasterId,
+val, 0, flags,  Request::funcUniqueId,
 tc->pcState().pc(), tc->contextId());

 Fault fault = getDTBPtr(tc)->translateFunctional(
@@ -2390,7 +2390,7 @@
 warn_once("Doing AT (address translation) in functional mode! Fix  
Me!\n");


 auto req = std::make_shared(
-val, 0, flags,  Request::funcMasterId,
+val, 0, flags,  Request::funcUniqueId,
 tc->pcState().pc(), tc->contextId());

 Fault fault = getDTBPtr(tc)->translateFunctional(
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index e9502f8..e7893bc 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -55,7 +55,7 @@

 TableWalker::TableWalker(const Params *p)
 : ClockedObject(p),
-  stage2Mmu(NULL), port(NULL), _id(Request::invldMasterId),
+  stage2Mmu(NULL), port(NULL), _id(Request::invldUniqueId),
   isStage2(p->is_stage2), tlb(NULL),
   currState(NULL), pending(false),
   numSquashable(p->num_squash_per_cycle),
diff --git a/src/arch/arm/tracers/tarmac_parser.cc  
b/src/arch/arm/tracers/tarmac_parser.cc

index 9ed5bf4..4c1ce07 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -1287,7 +1287,7 @@
 ArmISA::TLB* dtb = static_cast(thread->getDTBPtr());

 req->setVirt(addr, size, flags, thread->pcState().instAddr(),
- Request::funcMasterId);
+ Request::funcUniqueId);

 // Translate to physical address
 Fault fault = dtb->translateAtomic(req, thread, BaseTLB::Read);
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index a681a2e..9bf5fad 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -86,7 +86,7 @@
 buildIntPacket(Addr addr, T payload)
 {
 RequestPtr req = std::make_shared(
-addr, sizeof(T), Request::UNCACHEABLE, Request::intMasterId);
+addr, sizeof(T), Request::UNCACHEABLE, Request::intUniqueId);
 PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
 pkt->allocate();
 pkt->setRaw(payload);
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 0187703..f92f87b 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1488,10 +1488,10 @@
   "Writeback from read-only cache");
 assert(blk && blk->isValid() && (blk->isDirty() || writebackClean));

-stats.writebacks[Request::wbMasterId]++;
+stats.writebacks[Request::wbUniqueId]++;

 RequestPtr req = std::make_shared(
-regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId);
+regenerateBlkAddr(blk), blkSize, 0, Request::wbUniqueId);

 if (blk->isSecure())
 req->setFlags(Request::SECURE);
@@ -1533,7 +1533,7 @@
 BaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
 {
 RequestPtr req = std::make_shared(
-regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId);
+regenerateBlkAddr(blk), blkSize, 0, Request::wbUniqueId);

 if (blk->isSecure()) {
 req->setFlags(Request::SECURE);
@@ -1606,7 +1606,7 @@
 assert(blk.isValid());

 RequestPtr request = std::make_shared(
-regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId);
+regenerateBlkAddr(&blk), blkSize, 0, Request::funcUniqueId);

 request->taskId(blk.task_id);
 if (blk.isSecure()) {
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 6fb6f11..58fc31a 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -912,7 +912,7 @@

 // Creating a zero sized write, a message to the snoop filter
 RequestPtr req = std::make_shared(
-regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId);
+regenerateBlkAddr(blk), blkSize, 0, Reque

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: comments

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33542 )



Change subject: arch-arm: comments
..

arch-arm: comments

Change-Id: I97f96b4bb69de317cc3e652689dd47f6fcda85a1
---
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.hh
3 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index 1378cf9..6dbb881 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -52,7 +52,7 @@
   _id(p->sys->getMasterId(_stage1Tlb->getTableWalker()))
 {
 // we use the stage-one table walker as the parent of the port,
-// and to get our master id, this is done to keep things
+// and to get our unique id, this is done to keep things
 // symmetrical with other ISAs in terms of naming and stats
 stage1Tlb()->setMMU(this, _id);
 stage2Tlb()->setMMU(this, _id);
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 1d2b3f1..c18268a 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -829,7 +829,7 @@
 /** Port shared by the two table walkers. */
 DmaPort* port;

-/** Master id assigned by the MMU. */
+/** Unique id assigned by the MMU. */
 MasterID _id;

 /** Indicates whether this table walker is part of the stage 2 mmu */
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index ae87676..55be97e 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -399,7 +399,7 @@
  * reference. For ARM this method will always return a valid port
  * pointer.
  *
- * @return A pointer to the walker master port
+ * @return A pointer to the walker request port
  */
 Port *getTableWalkerPort() override;


--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Update instances of masterId

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33537 )



Change subject: mem-ruby: Update instances of masterId
..

mem-ruby: Update instances of masterId

Change-Id: I670affa150934e86385d3aa1e0a9f15b8d25243b
---
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
2 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc  
b/src/mem/ruby/slicc_interface/AbstractController.cc

index dd3a9e7..7efab75 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -50,7 +50,7 @@
 AbstractController::AbstractController(const Params *p)
 : ClockedObject(p), Consumer(this), m_version(p->version),
   m_clusterID(p->cluster_id),
-  m_masterId(p->system->getMasterId(this)), m_is_blocking(false),
+  m_id(p->system->getMasterId(this)), m_is_blocking(false),
   m_number_of_TBEs(p->number_of_TBEs),
   m_transitions_per_cycle(p->transitions_per_cycle),
   m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
@@ -219,7 +219,7 @@
 }

 RequestPtr req
-= std::make_shared(mem_msg->m_addr, req_size, 0,  
m_masterId);

+= std::make_shared(mem_msg->m_addr, req_size, 0, m_id);
 PacketPtr pkt;
 if (mem_msg->getType() == MemoryRequestType_MEMORY_WB) {
 pkt = Packet::createWrite(req);
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh  
b/src/mem/ruby/slicc_interface/AbstractController.hh

index 1d7e5a7..b90de85 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -147,7 +147,7 @@

   public:
 MachineID getMachineID() const { return m_machineID; }
-MasterID getMasterId() const { return m_masterId; }
+MasterID getMasterId() const { return m_id; }

 Stats::Histogram& getDelayHist() { return m_delayHistogram; }
 Stats::Histogram& getDelayVCHist(uint32_t index)
@@ -186,7 +186,7 @@
 const NodeID m_clusterID;

 // MasterID used by some components of gem5.
-const MasterID m_masterId;
+const MasterID m_id;

 Network *m_net_ptr;
 bool m_is_blocking;

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[gem5-dev] Change in gem5/gem5[develop]: dev: Update master/slave variables dist_iface

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33540 )



Change subject: dev: Update master/slave variables dist_iface
..

dev: Update master/slave variables dist_iface

Change-Id: Ie555328f5a016a482ab973e0db97e19993f55af9
---
M src/dev/net/dist_iface.cc
M src/dev/net/dist_iface.hh
M src/dev/net/tcp_iface.cc
3 files changed, 42 insertions(+), 42 deletions(-)



diff --git a/src/dev/net/dist_iface.cc b/src/dev/net/dist_iface.cc
index cc408e0..7974242 100644
--- a/src/dev/net/dist_iface.cc
+++ b/src/dev/net/dist_iface.cc
@@ -60,7 +60,7 @@
 DistIface::SyncEvent *DistIface::syncEvent = nullptr;
 unsigned DistIface::distIfaceNum = 0;
 unsigned DistIface::recvThreadsNum = 0;
-DistIface *DistIface::master = nullptr;
+DistIface *DistIface::primary = nullptr;
 bool DistIface::isSwitch = false;

 void
@@ -142,7 +142,7 @@
 needExit = ReqType::pending;
 if (needStopSync != ReqType::none)
 needStopSync = ReqType::pending;
-DistIface::master->sendCmd(header);
+DistIface::primary->sendCmd(header);
 // now wait until all receiver threads complete the synchronisation
 auto lf = [this]{ return waitNum == 0; };
 cv.wait(sync_lock, lf);
@@ -191,7 +191,7 @@
 } else {
 header.needStopSync = ReqType::none;
 }
-DistIface::master->sendCmd(header);
+DistIface::primary->sendCmd(header);
 return true;
 }

@@ -410,7 +410,7 @@
 start();
 } else {
 // Wake up thread contexts on non-switch nodes.
-for (auto *tc: master->sys->threads) {
+for (auto *tc: primary->sys->threads) {
 if (tc->status() == ThreadContext::Suspended)
 tc->activate();
 else
@@ -503,10 +503,10 @@
 "send_tick:%llu send_delay:%llu link_delay:%llu  
recv_tick:%llu\n",

 send_tick, send_delay, linkDelay, recv_tick);
 // Every packet must be sent and arrive in the same quantum
-assert(send_tick > master->syncEvent->when() -
-   master->syncEvent->repeat);
+assert(send_tick > primary->syncEvent->when() -
+   primary->syncEvent->repeat);
 // No packet may be scheduled for receive in the arrival quantum
-assert(send_tick + send_delay + linkDelay > master->syncEvent->when());
+assert(send_tick + send_delay + linkDelay >  
primary->syncEvent->when());


 // Now we are about to schedule a recvDone event for the new data  
packet.
 // We use the same recvDone object for all incoming data packets.  
Packet

@@ -611,8 +611,8 @@
 rank(dist_rank), size(dist_size)
 {
 DPRINTF(DistEthernet, "DistIface() ctor rank:%d\n",dist_rank);
-isMaster = false;
-if (master == nullptr) {
+isPrimary = false;
+if (primary == nullptr) {
 assert(sync == nullptr);
 assert(syncEvent == nullptr);
 isSwitch = is_switch;
@@ -621,8 +621,8 @@
 else
 sync = new SyncNode();
 syncEvent = new SyncEvent();
-master = this;
-isMaster = true;
+primary = this;
+isPrimary = true;
 }
 distIfaceId = distIfaceNum;
 distIfaceNum++;
@@ -639,8 +639,8 @@
 assert(sync);
 delete sync;
 }
-if (this == master)
-master = nullptr;
+if (this == primary)
+primary = nullptr;
 }

 void
@@ -728,7 +728,7 @@
 {
 DPRINTF(DistEthernet,"DistIFace::drain() called\n");
 // This can be called multiple times in the same drain cycle.
-if (this == master)
+if (this == primary)
 syncEvent->draining(true);
 return DrainState::Drained;
 }
@@ -736,7 +736,7 @@
 void
 DistIface::drainResume() {
 DPRINTF(DistEthernet,"DistIFace::drainResume() called\n");
-if (this == master)
+if (this == primary)
 syncEvent->draining(false);
 recvScheduler.resumeRecvTicks();
 }
@@ -755,7 +755,7 @@
 SERIALIZE_SCALAR(dist_iface_id_orig);

 recvScheduler.serializeSection(cp, "recvScheduler");
-if (this == master) {
+if (this == primary) {
 sync->serializeSection(cp, "Sync");
 }
 }
@@ -774,7 +774,7 @@
  dist_iface_id_orig);

 recvScheduler.unserializeSection(cp, "recvScheduler");
-if (this == master) {
+if (this == primary) {
 sync->unserializeSection(cp, "Sync");
 }
 }
@@ -801,8 +801,8 @@

 // Initialize the seed for random generator to avoid the same sequence
 // in all gem5 peer processes
-assert(master != nullptr);
-if (this == master)
+assert(primary != nullptr);
+if (this == primary)
 random_mt.init(5489 * (rank+1) + 257);
 }

@@ -811,7 +811,7 @@
 {
 DPRINTF(DistEthernet, "DistIface::startup() started\n");
 // Schedule synchronization unless we are not a switch in pseudo_op  
mode.

-if (this == master && (!syncStartOnPseudoOp || isSwitch))
+if (this == primary && (!syncStart

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: update print statements + master/slave variables

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33547 )



Change subject: gpu-compute: update print statements + master/slave  
variables

..

gpu-compute: update print statements + master/slave variables

Change-Id: I6fb925294d5fd2c670d15c0d895a43ef6c371ae3
---
M src/gpu-compute/X86GPUTLB.py
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
4 files changed, 24 insertions(+), 20 deletions(-)



diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py
index bd22bee..ab48a52 100644
--- a/src/gpu-compute/X86GPUTLB.py
+++ b/src/gpu-compute/X86GPUTLB.py
@@ -58,8 +58,10 @@
 missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
 missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
 maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
-slave = VectorSlavePort("Port on side closer to CPU/CU")
-master = VectorMasterPort("Port on side closer to memory")
+cpu_side = VectorSlavePort("Port on side closer to CPU/CU")
+slave= DeprecatedParam(cpu_side, '`slave` is now called  
`cpu_side`')

+mem_side = VectorMasterPort("Port on side closer to memory")
+master   = DeprecatedParam(mem_side, '`master` is now called  
`mem_side`')

 allocationPolicy = Param.Bool(True, "Allocate on an access")
 accessDistance = Param.Bool(False, "print accessDistance stats")

@@ -69,6 +71,8 @@
 cxx_header = 'gpu-compute/tlb_coalescer.hh'
 probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
 coalescingWindow = Param.Int(1, "Permit coalescing across that many  
ticks")

-slave = VectorSlavePort("Port on side closer to CPU/CU")
-master = VectorMasterPort("Port on side closer to memory")
+cpu_side = VectorSlavePort("Port on side closer to CPU/CU")
+slave= DeprecatedParam(cpu_side, '`slave` is now called  
`cpu_side`')

+mem_side = VectorMasterPort("Port on side closer to memory")
+master   DeprecatedParam(mem_side, '`master` is now called `mem_side`')
 disableCoalescing = Param.Bool(False,"Dispable Coalescing")
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index a37618d..4e67ecd 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -112,14 +112,14 @@
 missLatency1 = p->missLatency1;
 missLatency2 = p->missLatency2;

-// create the slave ports based on the number of connected ports
-for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
+// create the response ports based on the number of connected ports
+for (size_t i = 0; i < p->port_cpu_side_connection_count; ++i) {
 cpuSidePort.push_back(new CpuSidePort(csprintf("%s-port%d",
   name(), i), this, i));
 }

-// create the master ports based on the number of connected ports
-for (size_t i = 0; i < p->port_master_connection_count; ++i) {
+// create the request ports based on the number of connected ports
+for (size_t i = 0; i < p->port_mem_side_connection_count; ++i) {
 memSidePort.push_back(new MemSidePort(csprintf("%s-port%d",
   name(), i), this, i));
 }
@@ -135,13 +135,13 @@
 Port &
 GpuTLB::getPort(const std::string &if_name, PortID idx)
 {
-if (if_name == "slave") {
+if (if_name == "cpu_side") {
 if (idx >= static_cast(cpuSidePort.size())) {
 panic("TLBCoalescer::getPort: unknown index %d\n", idx);
 }

 return *cpuSidePort[idx];
-} else if (if_name == "master") {
+} else if (if_name == "mem_side") {
 if (idx >= static_cast(memSidePort.size())) {
 panic("TLBCoalescer::getPort: unknown index %d\n", idx);
 }
@@ -1323,7 +1323,7 @@
 AddrRangeList
 GpuTLB::CpuSidePort::getAddrRanges() const
 {
-// currently not checked by the master
+// currently not checked by the requestor
 AddrRangeList ranges;

 return ranges;
diff --git a/src/gpu-compute/tlb_coalescer.cc  
b/src/gpu-compute/tlb_coalescer.cc

index b591232..eccd328 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -51,14 +51,14 @@
"Cleanup issuedTranslationsTable hashmap",
false, Event::Maximum_Pri)
 {
-// create the slave ports based on the number of connected ports
-for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
+// create the response ports based on the number of connected ports
+for (size_t i = 0; i < p->port_cpu_side_connection_count; ++i) {
 cpuSidePort.push_back(new CpuSidePort(csprintf("%s-port%d",  
name(), i),

   this, i));
 }

-// create the

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Update variables master/slave

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33541 )



Change subject: mem-cache: Update variables master/slave
..

mem-cache: Update variables master/slave

Change-Id: I42942bd0880c8892b536d44865c1dd807f2aa030
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache_blk.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/sector_blk.cc
M src/mem/cache/tags/sector_blk.hh
11 files changed, 78 insertions(+), 77 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index f92f87b..ab2d02b 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -114,7 +114,7 @@
 // buffer before committing to an MSHR

 // forward snoops is overridden in init() once we can query
-// whether the connected master is actually snooping or not
+// whether the connected requestor is actually snooping or not

 tempBlock = new TempCacheBlk(blkSize);

@@ -1868,98 +1868,98 @@

 Stats::Group::regStats();
 System *system = cache.system;
-const auto max_masters = system->maxMasters();
+const auto max_requestors = system->maxMasters();

 hits
-.init(max_masters)
+.init(max_requestors)
 .flags(total | nozero | nonan)
 ;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 hits.subname(i, system->getMasterName(i));
 }

 // Miss statistics
 misses
-.init(max_masters)
+.init(max_requestors)
 .flags(total | nozero | nonan)
 ;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 misses.subname(i, system->getMasterName(i));
 }

 // Miss latency statistics
 missLatency
-.init(max_masters)
+.init(max_requestors)
 .flags(total | nozero | nonan)
 ;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 missLatency.subname(i, system->getMasterName(i));
 }

 // access formulas
 accesses.flags(total | nozero | nonan);
 accesses = hits + misses;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 accesses.subname(i, system->getMasterName(i));
 }

 // miss rate formulas
 missRate.flags(total | nozero | nonan);
 missRate = misses / accesses;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 missRate.subname(i, system->getMasterName(i));
 }

 // miss latency formulas
 avgMissLatency.flags(total | nozero | nonan);
 avgMissLatency = missLatency / misses;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 avgMissLatency.subname(i, system->getMasterName(i));
 }

 // MSHR statistics
 // MSHR hit statistics
 mshr_hits
-.init(max_masters)
+.init(max_requestors)
 .flags(total | nozero | nonan)
 ;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 mshr_hits.subname(i, system->getMasterName(i));
 }

 // MSHR miss statistics
 mshr_misses
-.init(max_masters)
+.init(max_requestors)
 .flags(total | nozero | nonan)
 ;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 mshr_misses.subname(i, system->getMasterName(i));
 }

 // MSHR miss latency statistics
 mshr_miss_latency
-.init(max_masters)
+.init(max_requestors)
 .flags(total | nozero | nonan)
 ;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 mshr_miss_latency.subname(i, system->getMasterName(i));
 }

 // MSHR uncacheable statistics
 mshr_uncacheable
-.init(max_masters)
+.init(max_requestors)
 .flags(total | nozero | nonan)
 ;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 mshr_uncacheable.subname(i, system->getMasterName(i));
 }

 // MSHR miss latency statistics
 mshr_uncacheable_lat
-.init(max_masters)
+.init(max_requestors)
 .flags(total | nozero | nonan)
 ;
-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 mshr_uncacheable_lat.subname(i, system->getMasterName(i));
 }

@@ -1967,21 +1967,21 @@
 mshrMissRate.flags(total | nozero | nonan);
 mshrMissRate = mshr_misses / accesses;

-for (int i = 0; i < max_masters; i++) {
+for (int i = 0; i < max_requestors; i++) {
 mshrMissRate.su

[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: comments

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33545 )



Change subject: learning-gem5: comments
..

learning-gem5: comments

Change-Id: Ic97e6b010ec9ca8106a317b8b817e0a5ffe7dbae
---
M src/learning_gem5/part2/simple_cache.hh
1 file changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/learning_gem5/part2/simple_cache.hh  
b/src/learning_gem5/part2/simple_cache.hh

index 4e57c87..9273eaf 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -101,14 +101,14 @@

   protected:
 /**
- * Receive an atomic request packet from the master port.
+ * Receive an atomic request packet from the request port.
  * No need to implement in this simple cache.
  */
 Tick recvAtomic(PacketPtr pkt) override
 { panic("recvAtomic unimpl."); }

 /**
- * Receive a functional request packet from the master port.
+ * Receive a functional request packet from the request port.
  * Performs a "debug" access updating/reading the data in place.
  *
  * @param packet the requestor sent.
@@ -116,7 +116,7 @@
 void recvFunctional(PacketPtr pkt) override;

 /**
- * Receive a timing request from the master port.
+ * Receive a timing request from the request port.
  *
  * @param the packet that the requestor sent
  * @return whether this object can consume to packet. If false, we
@@ -126,7 +126,7 @@
 bool recvTimingReq(PacketPtr pkt) override;

 /**
- * Called by the master port if sendTimingResp was called on this
+ * Called by the request port if sendTimingResp was called on this
  * slave port (causing recvTimingResp to be called on the master
  * port) and was unsuccesful.
  */
@@ -171,7 +171,7 @@

 /**
  * Called by the slave port if sendTimingReq was called on this
- * master port (causing recvTimingReq to be called on the slave
+ * request port (causing recvTimingReq to be called on the slave
  * port) and was unsuccesful.
  */
 void recvReqRetry() override;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic97e6b010ec9ca8106a317b8b817e0a5ffe7dbae
Gerrit-Change-Number: 33545
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev: update print statements ide disk

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33546 )



Change subject: dev: update print statements ide disk
..

dev: update print statements ide disk

ide_disk

Change-Id: Ib2b10b04c241d59f27fc10b85db0e2cbf514c96a
---
M src/dev/storage/ide_disk.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/dev/storage/ide_disk.hh b/src/dev/storage/ide_disk.hh
index 8a90d1c..9f42941 100644
--- a/src/dev/storage/ide_disk.hh
+++ b/src/dev/storage/ide_disk.hh
@@ -245,7 +245,7 @@
 uint32_t curPrdAddr;
 /** PRD entry */
 PrdTableEntry curPrd;
-/** Device ID (master=0/slave=1) */
+/** Device ID (device0=0/device1=1) */
 int devID;
 /** Interrupt pending */
 bool intrPending;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib2b10b04c241d59f27fc10b85db0e2cbf514c96a
Gerrit-Change-Number: 33546
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev: Update master/slave comments + variables -x86

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33543 )



Change subject: dev: Update master/slave comments + variables -x86
..

dev: Update master/slave comments + variables -x86

Change-Id: I1f924b3787fa7a0d5f5980f94163b8aa7afee862
---
M src/dev/x86/Pc.py
M src/dev/x86/SouthBridge.py
M src/dev/x86/i82094aa.cc
M src/dev/x86/i82094aa.hh
M src/dev/x86/i8259.cc
M src/dev/x86/i8259.hh
6 files changed, 40 insertions(+), 38 deletions(-)



diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 4a732e6..089df50 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -75,12 +75,12 @@

 def attachIO(self, bus, dma_ports = []):
 self.south_bridge.attachIO(bus, dma_ports)
-self.i_dont_exist1.pio = bus.master
-self.i_dont_exist2.pio = bus.master
-self.behind_pci.pio = bus.master
-self.com_1.pio = bus.master
-self.fake_com_2.pio = bus.master
-self.fake_com_3.pio = bus.master
-self.fake_com_4.pio = bus.master
-self.fake_floppy.pio = bus.master
+self.i_dont_exist1.pio = bus.mem_side
+self.i_dont_exist2.pio = bus.mem_side
+self.behind_pci.pio = bus.mem_side
+self.com_1.pio = bus.mem_side
+self.fake_com_2.pio = bus.mem_side
+self.fake_com_3.pio = bus.mem_side
+self.fake_com_4.pio = bus.mem_side
+self.fake_floppy.pio = bus.mem_side
 self.pci_host.pio = bus.default
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 7fd16cc..9a10df8 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -97,15 +97,15 @@
 self.speaker.i8254 = self.pit
 self.io_apic.external_int_pic = self.pic1
 # Connect to the bus
-self.cmos.pio = bus.master
-self.dma1.pio = bus.master
-self.ide.pio = bus.master
+self.cmos.pio = bus.mem_side
+self.dma1.pio = bus.mem_side
+self.ide.pio = bus.mem_side
 if dma_ports.count(self.ide.dma) == 0:
-self.ide.dma = bus.slave
-self.keyboard.pio = bus.master
-self.pic1.pio = bus.master
-self.pic2.pio = bus.master
-self.pit.pio = bus.master
-self.speaker.pio = bus.master
-self.io_apic.pio = bus.master
-self.io_apic.int_requestor = bus.slave
+self.ide.dma = bus.cpu_side
+self.keyboard.pio = bus.mem_side
+self.pic1.pio = bus.mem_side
+self.pic2.pio = bus.mem_side
+self.pit.pio = bus.mem_side
+self.speaker.pio = bus.mem_side
+self.io_apic.pio = bus.mem_side
+self.io_apic.int_requestor = bus.cpu_side
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
index 50b6e47..c7817dc 100644
--- a/src/dev/x86/i82094aa.cc
+++ b/src/dev/x86/i82094aa.cc
@@ -42,7 +42,7 @@
 X86ISA::I82094AA::I82094AA(Params *p)
 : BasicPioDevice(p, 20), extIntPic(p->external_int_pic),
   lowestPriorityOffset(0),
-  intMasterPort(name() + ".int_requestor", this, this, p->int_latency)
+  intRequestPort(name() + ".int_request", this, this, p->int_latency)
 {
 // This assumes there's only one I/O APIC in the system and since the  
apic
 // id is stored in a 8-bit field with 0xff meaning broadcast, the id  
must

@@ -71,16 +71,16 @@
 // the piodevice init() function.
 BasicPioDevice::init();

-// If the master port isn't connected, we can't send interrupts  
anywhere.

-panic_if(!intMasterPort.isConnected(),
+// If the request port isn't connected, we can't send interrupts  
anywhere.

+panic_if(!intRequestPort.isConnected(),
 "Int port not connected to anything!");
 }

 Port &
 X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
 {
-if (if_name == "int_requestor")
-return intMasterPort;
+if (if_name == "int_request")
+return intRequestPort;
 if (if_name == "inputs")
 return *inputs.at(idx);
 else
@@ -242,7 +242,7 @@
 }
 for (auto id: apics) {
 PacketPtr pkt = buildIntTriggerPacket(id, message);
-intMasterPort.sendMessage(pkt, sys->isTimingMode());
+intRequestPort.sendMessage(pkt, sys->isTimingMode());
 }
 }
 }
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index 2c81e27..dd23011 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -82,7 +82,7 @@

 std::vector *> inputs;

-IntMasterPort intMasterPort;
+IntMasterPort intRequestPort;

   public:
 typedef I82094AAParams Params;
diff --git a/src/dev/x86/i8259.cc b/src/dev/x86/i8259.cc
index 1e081d7..5b763f8 100644
--- a/src/dev/x86/i8259.cc
+++ b/src/dev/x86/i8259.cc
@@ -38,7 +38,7 @@
 X86ISA::I8259::I8259(Params * p)
 : BasicPioDevice(p, 2),
   latency(p->pio_latency),
-  mode(p->mode), slave(p->slave),
+  mode(p->mode), respo

[gem5-dev] Change in gem5/gem5[develop]: arch: Replaced master/slave variables

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33550 )



Change subject: arch: Replaced master/slave variables
..

arch: Replaced master/slave variables

Change-Id: I5c9d0cd19709a7e5034625c2dd42ace3a35b787a
---
M src/arch/generic/BaseTLB.py
1 file changed, 4 insertions(+), 2 deletions(-)



diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index cca7da6..56e8027 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -33,5 +33,7 @@
 abstract = True
 cxx_header = "arch/generic/tlb.hh"
 # Ports to connect with other TLB levels
-slave  = VectorSlavePort("Port closer to the CPU side")
-master = RequestPort("Port closer to memory side")
+cpu_side  = VectorSlavePort("Port closer to the CPU side")
+slave = DeprecatedParam(cpu_side, '`slave` is now called  
`cpu_side`')

+mem_side = RequestPort("Port closer to memory side")
+master   = DeprecatedParam(mem_side, '`master` is now called  
`mem_side`')


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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: master/slave variables and comments

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33544 )



Change subject: gpu-compute: master/slave variables and comments
..

gpu-compute: master/slave variables and comments

Change-Id: I5cefe7e407f048a4c38bd604b843179dcc73555f
---
M src/gpu-compute/compute_unit.cc
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index ad68edd..9a55df9 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -171,7 +171,7 @@

 memPort.resize(wfSize());

-// Setup tokens for slave ports. The number of tokens in memSlaveTokens
+// Setup tokens for response ports. The number of tokens in  
memSlaveTokens

 // is the total token count for the entire vector port (i.e., this CU).
 memPortTokens = new TokenManager(p->max_cu_tokens);

@@ -1521,7 +1521,7 @@
 }

 // First we must convert the response cmd back to a request cmd so that
-// the request can be sent through the cu's master port
+// the request can be sent through the cu's request port
 PacketPtr new_pkt = new Packet(pkt->req, requestCmd);
 new_pkt->dataStatic(pkt->getPtr());
 delete pkt->senderState;
@@ -1744,7 +1744,7 @@
 if (success) {
 // pkt is reused in fetch(), don't delete it here.  However, we  
must

 // reset the command to be a request so that it can be sent through
-// the cu's master port
+// the cu's request port
 assert(pkt->cmd == MemCmd::ReadResp);
 pkt->cmd = MemCmd::ReadReq;


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[gem5-dev] Change in gem5/gem5[develop]: arch: Replaced master/slave variables isa_parser

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33551 )



Change subject: arch: Replaced master/slave variables isa_parser
..

arch: Replaced master/slave variables isa_parser

Change-Id: I1a4ea653cdf05aed01cb57daad6ca95a96ab1f03
---
M src/arch/isa_parser.py
1 file changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 8eb90ef..7d8bffd 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1294,7 +1294,7 @@
 class SubOperandList(OperandList):
 '''Find all the operands in the given code block.  Returns an operand
 descriptor list (instance of class OperandList).'''
-def __init__(self, parser, code, master_list):
+def __init__(self, parser, code, requestor_list):
 self.items = []
 self.bases = {}
 # delete strings and comments so we don't match on operands inside
@@ -1315,17 +1315,17 @@
 if op_base in parser.elemToVector:
 elem_op = op_base
 op_base = parser.elemToVector[elem_op]
-# find this op in the master list
-op_desc = master_list.find_base(op_base)
+# find this op in the requestor list
+op_desc = requestor_list.find_base(op_base)
 if not op_desc:
-error('Found operand %s which is not in the master list!'
+error('Found operand %s which is not in the requestor  
list!'

   % op_base)
 else:
 # See if we've already found this operand
 op_desc = self.find_base(op_base)
 if not op_desc:
 # if not, add a reference to it to this sub list
-self.append(master_list.bases[op_base])
+self.append(requestor_list.bases[op_base])

 # start next search after end of current match
 next_pos = match.end()

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[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: update print statements + variables

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33548 )



Change subject: learning-gem5: update print statements + variables
..

learning-gem5: update print statements + variables

Change-Id: I0ab90dfb9c06de2a0431e99b505585ef3a2ac256
---
M src/learning_gem5/part2/simple_cache.hh
1 file changed, 7 insertions(+), 7 deletions(-)



diff --git a/src/learning_gem5/part2/simple_cache.hh  
b/src/learning_gem5/part2/simple_cache.hh

index 9273eaf..6f0426b 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -86,7 +86,7 @@

 /**
  * Get a list of the non-overlapping address ranges the owner is
- * responsible for. All slave ports must override this function
+ * responsible for. All response ports must override this function
  * and return a populated list with at least one item.
  *
  * @return a list of ranges responded to
@@ -127,8 +127,8 @@

 /**
  * Called by the request port if sendTimingResp was called on this
- * slave port (causing recvTimingResp to be called on the master
- * port) and was unsuccesful.
+ * response port (causing recvTimingResp to be called on the  
request

+ * port) and was unsuccessful.
  */
 void recvRespRetry() override;
 };
@@ -165,19 +165,19 @@

   protected:
 /**
- * Receive a timing response from the slave port.
+ * Receive a timing response from the response port.
  */
 bool recvTimingResp(PacketPtr pkt) override;

 /**
- * Called by the slave port if sendTimingReq was called on this
- * request port (causing recvTimingReq to be called on the slave
+ * Called by the response port if sendTimingReq was called on this
+ * request port (causing recvTimingReq to be called on the response
  * port) and was unsuccesful.
  */
 void recvReqRetry() override;

 /**
- * Called to receive an address range change from the peer slave
+ * Called to receive an address range change from the peer response
  * port. The default implementation ignores the change and does
  * nothing. Override this function in a derived class if the owner
  * needs to be aware of the address ranges, e.g. in an

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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: replace master/slave variable names

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33554 )



Change subject: fastmodel: replace master/slave variable names
..

fastmodel: replace master/slave variable names

Change-Id: I380b7dcc1a2bdba7b9e3962155a07e405a4b9555
---
M src/arch/arm/fastmodel/FastModel.py
1 file changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/fastmodel/FastModel.py  
b/src/arch/arm/fastmodel/FastModel.py

index 5be451a..a8fdb04 100644
--- a/src/arch/arm/fastmodel/FastModel.py
+++ b/src/arch/arm/fastmodel/FastModel.py
@@ -35,11 +35,11 @@
 def AMBA_INITIATOR_ROLE(width):
 return 'AMBA INITIATOR %d' % width

-def SC_MASTER_PORT_ROLE(port_type):
-return 'SC MASTER PORT for %s' % port_type
+def SC_REQUEST_PORT_ROLE(port_type):
+return 'SC REQUEST PORT for %s' % port_type

-def SC_SLAVE_PORT_ROLE(port_type):
-return 'SC SLAVE PORT for %s' % port_type
+def SC_RESPONSE_PORT_ROLE(port_type):
+return 'SC RESPONSE PORT for %s' % port_type

 class AmbaTargetSocket(Port):
 def __init__(self, width, desc):
@@ -77,16 +77,16 @@

 class ScMasterPort(Port):
 def __init__(self, desc, port_type):
-my_role = SC_MASTER_PORT_ROLE(port_type)
-peer_role = SC_SLAVE_PORT_ROLE(port_type)
+my_role = SC_REQUEST_PORT_ROLE(port_type)
+peer_role = SC_RESPONSE_PORT_ROLE(port_type)
 Port.compat(my_role, peer_role)

 super(ScMasterPort, self).__init__(my_role, desc)

 class ScSlavePort(Port):
 def __init__(self, desc, port_type):
-my_role = SC_SLAVE_PORT_ROLE(port_type)
-peer_role = SC_MASTER_PORT_ROLE(port_type)
+my_role = SC_RESPONSE_PORT_ROLE(port_type)
+peer_role = SC_REQUEST_PORT_ROLE(port_type)
 Port.compat(my_role, peer_role)

 super(ScSlavePort, self).__init__(my_role, desc)

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[gem5-dev] Change in gem5/gem5[develop]: dev: replace master/slave in variables, params -mips

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33552 )



Change subject: dev: replace master/slave in variables, params -mips
..

dev: replace master/slave in variables, params -mips

Change-Id: I666f6d8feae88282510bf31232fd84fea13f055b
---
M src/dev/mips/Malta.py
M src/dev/sparc/T1000.py
2 files changed, 19 insertions(+), 19 deletions(-)



diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py
index baed7e8..6b9e85d 100755
--- a/src/dev/mips/Malta.py
+++ b/src/dev/mips/Malta.py
@@ -59,6 +59,6 @@
 # earlier, since the bus object itself is typically defined at the
 # System level.
 def attachIO(self, bus):
-self.cchip.pio = bus.master
-self.io.pio = bus.master
-self.uart.pio = bus.master
+self.cchip.pio = bus.mem_side
+self.io.pio = bus.mem_side
+self.uart.pio = bus.mem_side
diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index dee2207..2b1bd16 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -112,8 +112,8 @@
 iob = Iob()
 # Attach I/O devices that are on chip
 def attachOnChipIO(self, bus):
-self.iob.pio = bus.master
-self.htod.pio = bus.master
+self.iob.pio = bus.mem_side
+self.htod.pio = bus.mem_side


 # Attach I/O devices to specified bus object.  Can't do this
@@ -122,17 +122,17 @@
 def attachIO(self, bus):
 self.hvuart.device = self.hterm
 self.puart0.device = self.pterm
-self.fake_clk.pio = bus.master
-self.fake_membnks.pio = bus.master
-self.fake_l2_1.pio = bus.master
-self.fake_l2_2.pio = bus.master
-self.fake_l2_3.pio = bus.master
-self.fake_l2_4.pio = bus.master
-self.fake_l2esr_1.pio = bus.master
-self.fake_l2esr_2.pio = bus.master
-self.fake_l2esr_3.pio = bus.master
-self.fake_l2esr_4.pio = bus.master
-self.fake_ssi.pio = bus.master
-self.fake_jbi.pio = bus.master
-self.puart0.pio = bus.master
-self.hvuart.pio = bus.master
+self.fake_clk.pio = bus.mem_side
+self.fake_membnks.pio = bus.mem_side
+self.fake_l2_1.pio = bus.mem_side
+self.fake_l2_2.pio = bus.mem_side
+self.fake_l2_3.pio = bus.mem_side
+self.fake_l2_4.pio = bus.mem_side
+self.fake_l2esr_1.pio = bus.mem_side
+self.fake_l2esr_2.pio = bus.mem_side
+self.fake_l2esr_3.pio = bus.mem_side
+self.fake_l2esr_4.pio = bus.mem_side
+self.fake_ssi.pio = bus.mem_side
+self.fake_jbi.pio = bus.mem_side
+self.puart0.pio = bus.mem_side
+self.hvuart.pio = bus.mem_side

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[gem5-dev] Change in gem5/gem5[develop]: python: replaced master/slave

2020-08-26 Thread Shivani Parekh (Gerrit) via gem5-dev

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33553 )



Change subject: python: replaced master/slave
..

python: replaced master/slave

Change-Id: I4df2557c71e38cc4e3a485b0e590e85eb45de8b6
---
M src/python/m5/SimObject.py
M src/python/m5/util/dot_writer.py
2 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 7c4c809..425c53f 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -186,11 +186,11 @@

 for port in simobj._ports.values():
 is_vector = isinstance(port, m5.params.VectorPort)
-is_master = port.role == 'MASTER'
+is_requestor = port.role == 'REQUESTOR'

 code('ports["%s"] = new PortDesc("%s", %s, %s);' %
 (port.name, port.name, cxx_bool(is_vector),
-cxx_bool(is_master)))
+cxx_bool(is_requestor)))

 code.dedent()
 code('}')
diff --git a/src/python/m5/util/dot_writer.py  
b/src/python/m5/util/dot_writer.py

index c66108d..8b757e8 100644
--- a/src/python/m5/util/dot_writer.py
+++ b/src/python/m5/util/dot_writer.py
@@ -42,7 +42,7 @@
 # view. The output generated by do_dot() is a DOT-based figure (as a
 # pdf and an editable svg file) and its source dot code. Nodes are
 # components, and edges represent the memory hierarchy: the edges are
-# directed, from a master to slave. Initially all nodes are
+# directed, from a requestor to responder. Initially all nodes are
 # generated, and then all edges are added. do_dot should be called
 # with the top-most SimObject (namely root but not necessarily), the
 # output folder and the output dot source filename. From the given

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[gem5-dev] Change in gem5/gem5[develop]: systemc: Send response to TLM side if a packet does not need response

2020-08-26 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32735 )


Change subject: systemc: Send response to TLM side if a packet does not  
need response

..

systemc: Send response to TLM side if a packet does not need response

A completed TLM transaction includes request and response parts.
Currently, if a gem5 packet does not need a reponse, the bridge would not
send BEGIN_RESP to its upstream. It causes stuck on TLM side.

To fix this problem, the bridge should send BEGIN_RESP by itself in this
case.

Change-Id: I318dec21bc3f291693715c0d70bc624addf05076
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32735
Reviewed-by: Gabe Black 
Tested-by: kokoro 
Maintainer: Gabe Black 
---
M src/systemc/tlm_bridge/tlm_to_gem5.cc
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass

Objections:
  Matthias Jung: I would prefer this is not merged as is



diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc  
b/src/systemc/tlm_bridge/tlm_to_gem5.cc

index e6cb483..2bfbcc4 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -162,8 +162,15 @@
 auto tlmSenderState = new TlmSenderState(trans);
 pkt->pushSenderState(tlmSenderState);

+// If the packet doesn't need a response, we should send BEGIN_RESP by
+// ourselves.
+bool needsResponse = pkt->needsResponse();
 if (bmp.sendTimingReq(pkt)) { // port is free -> send END_REQ  
immediately

 sendEndReq(trans);
+if (!needsResponse) {
+auto delay = sc_core::SC_ZERO_TIME;
+sendBeginResp(trans, delay);
+}
 trans.release();
 } else { // port is blocked -> wait for retry before sending END_REQ
 waitForRetry = true;
@@ -429,12 +436,19 @@
 sc_assert(pendingRequest != nullptr);
 sc_assert(pendingPacket != nullptr);

+// If the packet doesn't need a response, we should send BEGIN_RESP by
+// ourselves.
+bool needsResponse = pendingPacket->needsResponse();
 if (bmp.sendTimingReq(pendingPacket)) {
 waitForRetry = false;
 pendingPacket = nullptr;

 auto &trans = *pendingRequest;
 sendEndReq(trans);
+if (!needsResponse) {
+auto delay = sc_core::SC_ZERO_TIME;
+sendBeginResp(trans, delay);
+}
 trans.release();

 pendingRequest = nullptr;

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Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Christian Menard 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matthias Jung 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jui-min Lee 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Allow pre-commit hook to parse unicode/nonASCII characters

2020-08-26 Thread Lakin Smith (Gerrit) via gem5-dev

Lakin Smith has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33556 )



Change subject: util: Allow pre-commit hook to parse unicode/nonASCII  
characters

..

util: Allow pre-commit hook to parse unicode/nonASCII characters

Set the default encoding in python to utf-8, this should be
removed when moving to Python3.

See:
https://stackoverflow.com/questions/3828723/why-should-we-not-use-sys-setdefaultencodingutf-8-in-a-py-script

Change-Id: I76ff6e573b9718d3023177bbd50b37a6ee3bc514
---
M util/style/verifiers.py
1 file changed, 5 insertions(+), 0 deletions(-)



diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index 85f31ce..b639b5e 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -46,6 +46,11 @@
 import os
 import re
 import sys
+# Allow pre-commit hook to parse unicode/non-ASCII characters
+# by setting the python encoding to utf-8.
+# This should be removed when moving to Python3
+reload(sys)
+sys.setdefaultencoding('utf-8')

 from six import add_metaclass


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Gerrit-PatchSet: 1
Gerrit-Owner: Lakin Smith 
Gerrit-MessageType: newchange
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