Re: [time-nuts] Using CPLD/FPGA or similar for frequency
In my mind, at least, this is still the same subject… Does anyone have any results to share re the SiLabs Si53xx ‘Jitter Attenuating Clock Multipliers’? Is this a helpful way to supply a 1GHz counter with a ‘0.1ps rms phase jitter’ clock? Alan ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
On Wed, 17 Jun 2015 09:32:23 +1200 Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: Do you mean the technique that Panek et al. [1] are using? Not quite he used an impulse to excite a saw filter rather than switching off the dc current feed to an inductor or the equivalent. Is there any fundamental difference there? IIRC he got that down to 0.5ps RMS now. And yes, the major source of error is the oscillator, according to [2]. Ripamonti et al. showed in [3] that using an LC tank instead of an SAW filter will result in something in the order of 2-10ps RMS (after temperature compensation). So this system is in the same region as an well designed time-to-amplitude converter based system. The curve fitting algorithm they used is somewhat deficient as is the switching method employed one can do much better provided one has sufficient time or computing resources available. Can you give a description what you would do differently? And yes, the two authors look like fresh graduate students who were told by their professor to see whether they can reproduce Paneks results without using a SAW filter. My crude testing using a somewhat simplified diode switched current source powered by the signal itself achieved a fitting noise of around 5ps with a 14 bit ADC. A better driver and higher resolution ADC with a lower noise input amplifier than the input amplifier of the oscilloscope I used should improve the results somewhat as would a better model for the damped sine signal. Hmm.. but the diode switched current source would need a quite steep input pulse, wouldn't it? So some kind of pulse shaping would be needed for a general circuit. I also played with the idea to use a overtone crystal oscillator instead of an LC tank, as this would probably give a higher temperature stability. Attila Kinali -- I must not become metastable. Metastability is the mind-killer. Metastability is the little-death that brings total obliteration. I will face my metastability. I will permit it to pass over me and through me. And when it has gone past I will turn the inner eye to see its path. Where the metastability has gone there will be nothing. Only I will remain. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
I used the output of a CMOS frequency divider to drive a capacitor coupled passive dual diode and resistor plus a parallel tank circuit comprising a 1uH powdered iron core (amidon #6) inductor and a 100pF silvered mica capacitor. The ADC used a 100MHz clock which also drove the frequency divider chain. The idea being to evaluate the performance of the ringing LC circuit and minimise the influence of the 100MHz ocxo. A BAW crystal could be used as a filter replacing the SAW filter used by Panek. Bruce On Wednesday, 17 June 2015 8:20 PM, Attila Kinali att...@kinali.ch wrote: On Wed, 17 Jun 2015 09:32:23 +1200 Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: Do you mean the technique that Panek et al. [1] are using? Not quite he used an impulse to excite a saw filter rather than switching off the dc current feed to an inductor or the equivalent. Is there any fundamental difference there? IIRC he got that down to 0.5ps RMS now. And yes, the major source of error is the oscillator, according to [2]. Ripamonti et al. showed in [3] that using an LC tank instead of an SAW filter will result in something in the order of 2-10ps RMS (after temperature compensation). So this system is in the same region as an well designed time-to-amplitude converter based system. The curve fitting algorithm they used is somewhat deficient as is the switching method employed one can do much better provided one has sufficient time or computing resources available. Can you give a description what you would do differently? And yes, the two authors look like fresh graduate students who were told by their professor to see whether they can reproduce Paneks results without using a SAW filter. My crude testing using a somewhat simplified diode switched current source powered by the signal itself achieved a fitting noise of around 5ps with a 14 bit ADC. A better driver and higher resolution ADC with a lower noise input amplifier than the input amplifier of the oscilloscope I used should improve the results somewhat as would a better model for the damped sine signal. Hmm.. but the diode switched current source would need a quite steep input pulse, wouldn't it? So some kind of pulse shaping would be needed for a general circuit. I also played with the idea to use a overtone crystal oscillator instead of an LC tank, as this would probably give a higher temperature stability. Attila Kinali -- I must not become metastable. Metastability is the mind-killer. Metastability is the little-death that brings total obliteration. I will face my metastability. I will permit it to pass over me and through me. And when it has gone past I will turn the inner eye to see its path. Where the metastability has gone there will be nothing. Only I will remain. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
Hoi Bruce, On Tue, 16 Jun 2015 12:24:34 +1200 Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: Using an ADC to sample a triggered damped sinewave easily achieves 5ps resolution (eg Keysight Acquiris). With a better optimised waveform model and least squares fitting routine greater resolution is feasible. The accuracy is dependent on the ADC sampling clock stability. An optical frequency standard derived clock may be required to maintain ps accuracy for long time intervals. Do you mean the technique that Panek et al. [1] are using? IIRC he got that down to 0.5ps RMS now. And yes, the major source of error is the oscillator, according to [2]. Ripamonti et al. showed in [3] that using an LC tank instead of an SAW filter will result in something in the order of 2-10ps RMS (after temperature compensation). So this system is in the same region as an well designed time-to-amplitude converter based system. I really wonder which one would be easier to build. Attila Kinali [1] Time interval measurement device based on surface acoustic wave filter excitation, providing 1ps precision and stability, by Panek andProchazka, 2007 http://dx.doi.org/10.1063/1.2779217 [2] Random Errors in Time Interval Measurement Based on SAW Filter Excitation, by Panek, 2008 http://dx.doi.org/10.1109/TIM.2007.915465 [3] High frequency, high time resolution time-to-digital converter employing passive resonating circuits, by Ripamonti, Abba, Geraci, 2010 http://dx.doi.org/10.1063/1.3432002 -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
Hi On Jun 15, 2015, at 11:26 PM, Hal Murray hmur...@megapathdsl.net wrote: kb...@n1k.org said: Since the internal PLL’s have jitter in the 20 to 30 ps RMS range, that limits a lot of the data you get. I haven't looked recently, but I doubt if much has changed. Xilinx uses DLLs rather than PLLs. The jitter on both clock sources looks pretty gaussian. They have a long chain of buffers and a giant multiplexor to select the right tap. Does anybody have data on what the jitter actually looks like? I'd expect several blurry peaks, with the spacing between peaks being the step size of the delay/mux chain and the blur being wider if there is more random logic. The calibration output is a mess … Bob -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
On Mon, 15 Jun 2015 20:26:09 -0700 Hal Murray hmur...@megapathdsl.net wrote: Does anybody have data on what the jitter actually looks like? I'd expect several blurry peaks, with the spacing between peaks being the step size of the delay/mux chain and the blur being wider if there is more random logic. Quick googling revieled these two papers: [1] Jitter issues in clock conditioning with FPGAs, by Aloisio, Giordano, Izzo, 2010 http://dx.doi.org/10.1109/RTC.2010.5750386 [2] Phase Noise Issues With FPGA-Embedded DLLs and PLLs in HEP Applications, by Aloisio, Giordano, Izzo, 2011 http://dx.doi.org/10.1109/TNS.2011.2143727 Both contain phase noise plots for different configurations of DLLs of Virtex 5. I haven't read them yet, so I cannot say anything about their content. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
On Tuesday, June 16, 2015 10:01:09 AM Attila Kinali wrote: Hoi Bruce, On Tue, 16 Jun 2015 12:24:34 +1200 Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: Using an ADC to sample a triggered damped sinewave easily achieves 5ps resolution (eg Keysight Acquiris). With a better optimised waveform model and least squares fitting routine greater resolution is feasible. The accuracy is dependent on the ADC sampling clock stability. An optical frequency standard derived clock may be required to maintain ps accuracy for long time intervals. Do you mean the technique that Panek et al. [1] are using? Not quite he used an impulse to excite a saw filter rather than switching off the dc current feed to an inductor or the equivalent. IIRC he got that down to 0.5ps RMS now. And yes, the major source of error is the oscillator, according to [2]. Ripamonti et al. showed in [3] that using an LC tank instead of an SAW filter will result in something in the order of 2-10ps RMS (after temperature compensation). So this system is in the same region as an well designed time-to-amplitude converter based system. The curve fitting algorithm they used is somewhat deficient as is the switching method employed one can do much better provided one has sufficient time or computing resources available. My crude testing using a somewhat simplified diode switched current source powered by the signal itself achieved a fitting noise of around 5ps with a 14 bit ADC. A better driver and higher resolution ADC with a lower noise input amplifier than the input amplifier of the oscilloscope I used should improve the results somewhat as would a better model for the damped sine signal. I really wonder which one would be easier to build. Keysight as far as I can tell used a discrete LC circuit to produce a damped sine wave rather than the conventional TAC approach used in the lower resolution Acquiris models. Bruce Attila Kinali [1] Time interval measurement device based on surface acoustic wave filter excitation, providing 1ps precision and stability, by Panek andProchazka, 2007 http://dx.doi.org/10.1063/1.2779217 [2] Random Errors in Time Interval Measurement Based on SAW Filter Excitation, by Panek, 2008 http://dx.doi.org/10.1109/TIM.2007.915465 [3] High frequency, high time resolution time-to-digital converter employing passive resonating circuits, by Ripamonti, Abba, Geraci, 2010 http://dx.doi.org/10.1063/1.3432002 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
Hi I’ve spent a lot of time with both of those papers and with a couple of others in the “series’. The gotcha is in the interpretation of the calibration results. It is often very unclear which pattern comes before which other pattern. Since the internal PLL’s have jitter in the 20 to 30 ps RMS range, that limits a lot of the data you get. Bob On Jun 15, 2015, at 6:03 PM, Attila Kinali att...@kinali.ch wrote: On Wed, 10 Jun 2015 21:45:33 -0400 Bob Camp kb...@n1k.org wrote: The delay line in an FPGA approach might get you to 20 ps. There is a lot of hand waving in the calibration process to get there. ( = figuring out that state A came before state B is based on things that are difficult to prove). If you do get it calibrated, you then find that it’s sensitive to both supply voltage and to temperature. The supply thing you can take care of with a good regulator. The “shifts all over the place when you put your thumb on it” T/C is not quite as easy to deal with. A TDC using an R/C and an ADC is a *much* easier way to go. Just two references on this topic: [1] Is AFAIK the only way to get FPGAs below the intrinsic cell delay (which is varies between a min of 10-20ps and a max of 100-200ps within the same FPGA) And [2] gives an idea how a possible calibration system might work. Attila Kinali [1] The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay, by Wu, Jinyuan and Shi, Zonghan, 2008 http://dx.doi.org/10.1109/NSSMIC.2008.4775079 [2] Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator, by Rivior, 2006 http://dx.doi.org/10.1109/ATS.2006.260991 -- I must not become metastable. Metastability is the mind-killer. Metastability is the little-death that brings total obliteration. I will face my metastability. I will permit it to pass over me and through me. And when it has gone past I will turn the inner eye to see its path. Where the metastability has gone there will be nothing. Only I will remain. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
kb...@n1k.org said: Since the internal PLLâs have jitter in the 20 to 30 ps RMS range, that limits a lot of the data you get. I haven't looked recently, but I doubt if much has changed. Xilinx uses DLLs rather than PLLs. They have a long chain of buffers and a giant multiplexor to select the right tap. Does anybody have data on what the jitter actually looks like? I'd expect several blurry peaks, with the spacing between peaks being the step size of the delay/mux chain and the blur being wider if there is more random logic. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
Using an ADC to sample a triggered damped sinewave easily achieves 5ps resolution (eg Keysight Acquiris). With a better optimised waveform model and least squares fitting routine greater resolution is feasible. The accuracy is dependent on the ADC sampling clock stability. An optical frequency standard derived clock may be required to maintain ps accuracy for long time intervals. Bruce On Tuesday, June 16, 2015 12:14:01 AM Attila Kinali wrote: On Thu, 11 Jun 2015 14:22:58 + Alan Ambrose alan.ambr...@anagram.net wrote: A clever interpolator for frequency or TIC would kill it - for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 bit ADC - and 1pS should be easy Which architecture for the FPGA do you have in mind? The delay line method (which is the most common one for FPGAs) has an intrinsic limit around 10-20ps. But the SR620 and the PICTIC use both a time to amplitude conversion by charging a capacitor (both include a Nutt interpolator). Using this technique, it might be possible to get into the 1ps ballpark, if the design is done carefully (according to Richard McCorkle, the limiting factor for the PICTIC II was the ADC of the PIC, followed by the stability of the reference clock). Attila Kinali ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
Hi Coming up with a reference clock can be harder than you might think. Most of the jitter numbers you see published on frequency sources are based on a “jitter mask” that runs from (maybe) 10 KHz up to 20 MHz. That’s fine for a specific telecom need. It may not in any way apply to capturing a 1 pps pulse. *IF* you believe the phase noise to jitter integration stuff (and there are reasons not to) the jitter goes way up as you integrate closer to carrier. A 0.1 ps source can quickly turn into a 10 or 100 ps source with a change of the lower bound on the jitter mask. Now, once you have the jitter number, you are only part way to knowing it’s impact on your measurement. There are *always* more things to consider. Bob On Jun 15, 2015, at 6:14 PM, Attila Kinali att...@kinali.ch wrote: On Thu, 11 Jun 2015 14:22:58 + Alan Ambrose alan.ambr...@anagram.net wrote: A clever interpolator for frequency or TIC would kill it - for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 bit ADC - and 1pS should be easy Which architecture for the FPGA do you have in mind? The delay line method (which is the most common one for FPGAs) has an intrinsic limit around 10-20ps. But the SR620 and the PICTIC use both a time to amplitude conversion by charging a capacitor (both include a Nutt interpolator). Using this technique, it might be possible to get into the 1ps ballpark, if the design is done carefully (according to Richard McCorkle, the limiting factor for the PICTIC II was the ADC of the PIC, followed by the stability of the reference clock). Attila Kinali -- I must not become metastable. Metastability is the mind-killer. Metastability is the little-death that brings total obliteration. I will face my metastability. I will permit it to pass over me and through me. And when it has gone past I will turn the inner eye to see its path. Where the metastability has gone there will be nothing. Only I will remain. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
On Wed, 10 Jun 2015 21:45:33 -0400 Bob Camp kb...@n1k.org wrote: The delay line in an FPGA approach might get you to 20 ps. There is a lot of hand waving in the calibration process to get there. ( = figuring out that state A came before state B is based on things that are difficult to prove). If you do get it calibrated, you then find that it’s sensitive to both supply voltage and to temperature. The supply thing you can take care of with a good regulator. The “shifts all over the place when you put your thumb on it” T/C is not quite as easy to deal with. A TDC using an R/C and an ADC is a *much* easier way to go. Just two references on this topic: [1] Is AFAIK the only way to get FPGAs below the intrinsic cell delay (which is varies between a min of 10-20ps and a max of 100-200ps within the same FPGA) And [2] gives an idea how a possible calibration system might work. Attila Kinali [1] The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay, by Wu, Jinyuan and Shi, Zonghan, 2008 http://dx.doi.org/10.1109/NSSMIC.2008.4775079 [2] Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator, by Rivior, 2006 http://dx.doi.org/10.1109/ATS.2006.260991 -- I must not become metastable. Metastability is the mind-killer. Metastability is the little-death that brings total obliteration. I will face my metastability. I will permit it to pass over me and through me. And when it has gone past I will turn the inner eye to see its path. Where the metastability has gone there will be nothing. Only I will remain. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
On Thu, 11 Jun 2015 14:22:58 + Alan Ambrose alan.ambr...@anagram.net wrote: A clever interpolator for frequency or TIC would kill it - for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 bit ADC - and 1pS should be easy Which architecture for the FPGA do you have in mind? The delay line method (which is the most common one for FPGAs) has an intrinsic limit around 10-20ps. But the SR620 and the PICTIC use both a time to amplitude conversion by charging a capacitor (both include a Nutt interpolator). Using this technique, it might be possible to get into the 1ps ballpark, if the design is done carefully (according to Richard McCorkle, the limiting factor for the PICTIC II was the ADC of the PIC, followed by the stability of the reference clock). Attila Kinali -- I must not become metastable. Metastability is the mind-killer. Metastability is the little-death that brings total obliteration. I will face my metastability. I will permit it to pass over me and through me. And when it has gone past I will turn the inner eye to see its path. Where the metastability has gone there will be nothing. Only I will remain. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
Hello It also depends on which device primitives you can use. Xilinx spartan series has an SRL16, 16 bit shift register that can be ganged to form dividers / pre scalers. It only takes up one lut or slice, I forget which. Link On Jun 11, 2015, at 4:11 AM, Bob Camp kb...@n1k.org wrote: Hi Depending on which chip you are using and how big it is, you can get into the 150 to 500 ps range running a carry chain as a TDC.That’s without getting into things like hand routing and temperature / voltage issues. How big a chip you need will be a function of how high you can get the internal PLL to run while packing a bunch of stuff in the chip. If you can hit 400 MHz, each carry chain will need to handle a bit more than 2.5 ns, but probably less than 5 ns. You can do that with a carry chain a few hundred bits long. There is a bit of handwaving already so this is indeed a guess rather than a design. If you run 320 bit chains and 8 inputs, you will need 2.5K registers for the carry chains. You also will need about 200 registers for the support of each chain, so that adds another 1.6K registers. Something in the 5K register range is a possible way to go for 8 inputs. Bob On Jun 11, 2015, at 2:04 AM, Gregory Maxwell gmaxw...@gmail.com wrote: On Tue, Jun 9, 2015 at 11:40 AM, Alan Ambrose alan.ambr...@anagram.net wrote: How about a 1pS resolution TIC? :) Or a 12 digit frequency counter? :) :) It's not a proper time-nut project unless there's a nutty element... Well, how complex? Front end with a fast ADC and make a DSP DMTD device? In terms of simpler things that (AFAIK) one can't go out and buy: a TIC with 4 or 8 inputs would be an interesting piece of time nut gear.even if it was 'just' 1ns resolution Surplus lab TICs are easily had but become quite a pile of equipment when you want to concurrently measure a half dozen oscillators. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
Hi The whole “weird primitives” thing is why I try to count this stuff in registers (flip flops) used rather than what ever neat name the marketing guys came up with this week that sounds better than “glob of stuff”. Bob On Jun 12, 2015, at 11:44 PM, lincoln linc...@ampmonkeys.com wrote: Hello It also depends on which device primitives you can use. Xilinx spartan series has an SRL16, 16 bit shift register that can be ganged to form dividers / pre scalers. It only takes up one lut or slice, I forget which. Link On Jun 11, 2015, at 4:11 AM, Bob Camp kb...@n1k.org wrote: Hi Depending on which chip you are using and how big it is, you can get into the 150 to 500 ps range running a carry chain as a TDC.That’s without getting into things like hand routing and temperature / voltage issues. How big a chip you need will be a function of how high you can get the internal PLL to run while packing a bunch of stuff in the chip. If you can hit 400 MHz, each carry chain will need to handle a bit more than 2.5 ns, but probably less than 5 ns. You can do that with a carry chain a few hundred bits long. There is a bit of handwaving already so this is indeed a guess rather than a design. If you run 320 bit chains and 8 inputs, you will need 2.5K registers for the carry chains. You also will need about 200 registers for the support of each chain, so that adds another 1.6K registers. Something in the 5K register range is a possible way to go for 8 inputs. Bob On Jun 11, 2015, at 2:04 AM, Gregory Maxwell gmaxw...@gmail.com wrote: On Tue, Jun 9, 2015 at 11:40 AM, Alan Ambrose alan.ambr...@anagram.net wrote: How about a 1pS resolution TIC? :) Or a 12 digit frequency counter? :) :) It's not a proper time-nut project unless there's a nutty element... Well, how complex? Front end with a fast ADC and make a DSP DMTD device? In terms of simpler things that (AFAIK) one can't go out and buy: a TIC with 4 or 8 inputs would be an interesting piece of time nut gear.even if it was 'just' 1ns resolution Surplus lab TICs are easily had but become quite a pile of equipment when you want to concurrently measure a half dozen oscillators. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
Hi Well, take the CPLD up to 100 MHz, and feed 20 ns pulses to the TDC’s RC, drive that into a cheap 24 bit sigma delta A/D and you have an easy 1 Fs. Do a little processing on multiple samples and you have 15 displayed digits. = Of course everything past about 50 ps is just noise …. It all depends on what you are after: Resolution Accuracy Repeatability The first one is easy in any system. The last one can fool you. The one in the middle is what you actually were after in most cases. Bob On Jun 11, 2015, at 10:22 AM, Alan Ambrose alan.ambr...@anagram.net wrote: Hi, So that turns into 2 games: How fast can you count? How many digits can you get in 1 second? A clever interpolator for frequency or TIC would kill it - for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 bit ADC - and 1pS should be easy Alan ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
On Tue, Jun 9, 2015 at 11:40 AM, Alan Ambrose alan.ambr...@anagram.net wrote: How about a 1pS resolution TIC? :) Or a 12 digit frequency counter? :) :) It's not a proper time-nut project unless there's a nutty element... Well, how complex? Front end with a fast ADC and make a DSP DMTD device? In terms of simpler things that (AFAIK) one can't go out and buy: a TIC with 4 or 8 inputs would be an interesting piece of time nut gear.even if it was 'just' 1ns resolution Surplus lab TICs are easily had but become quite a pile of equipment when you want to concurrently measure a half dozen oscillators. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
Hi Depending on which chip you are using and how big it is, you can get into the 150 to 500 ps range running a carry chain as a TDC.That’s without getting into things like hand routing and temperature / voltage issues. How big a chip you need will be a function of how high you can get the internal PLL to run while packing a bunch of stuff in the chip. If you can hit 400 MHz, each carry chain will need to handle a bit more than 2.5 ns, but probably less than 5 ns. You can do that with a carry chain a few hundred bits long. There is a bit of handwaving already so this is indeed a guess rather than a design. If you run 320 bit chains and 8 inputs, you will need 2.5K registers for the carry chains. You also will need about 200 registers for the support of each chain, so that adds another 1.6K registers. Something in the 5K register range is a possible way to go for 8 inputs. Bob On Jun 11, 2015, at 2:04 AM, Gregory Maxwell gmaxw...@gmail.com wrote: On Tue, Jun 9, 2015 at 11:40 AM, Alan Ambrose alan.ambr...@anagram.net wrote: How about a 1pS resolution TIC? :) Or a 12 digit frequency counter? :) :) It's not a proper time-nut project unless there's a nutty element... Well, how complex? Front end with a fast ADC and make a DSP DMTD device? In terms of simpler things that (AFAIK) one can't go out and buy: a TIC with 4 or 8 inputs would be an interesting piece of time nut gear.even if it was 'just' 1ns resolution Surplus lab TICs are easily had but become quite a pile of equipment when you want to concurrently measure a half dozen oscillators. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Using CPLD/FPGA or similar for frequency
Hi, So that turns into 2 games: How fast can you count? How many digits can you get in 1 second? A clever interpolator for frequency or TIC would kill it - for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 bit ADC - and 1pS should be easy Alan ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
alan.ambr...@anagram.net said: How about a 1pS resolution TIC? :) An alternative way to describe that sort of problem is How accurately can you locate an edge? I haven't looked carefully at the Spartan 3E. You might be able to run a signal along a column through a slow path and clock the whole column at the same time. Then sort out how far it got. That slow path is basically a delay line with many taps. It would take some experimentation, and maybe some duplicate logic for run time calibration. Or a 12 digit frequency counter? :) :) 12 digits is easy. Just wait long enough. So that turns into 2 games: How fast can you count? How many digits can you get in 1 second? Here is a toy that would be useful: assume you have a 10 MHz reference clock. make a design that captures something like a PPS and spits out the time-stamp on a serial port. I think Tom has a PIC that does that. The idea here is to use a faster clock so you get better resolution. How much resolution can you get with pure digital logic? (no delay lines) I'd like something like that watching the power line. You might need some sort of compression scheme or the serial port would get overloaded. 9600 baud is 1K characters per second. 60 Hz is 16 ms per cycle so you get 15 characters per cycle (plus a separator) unless there is noise on the line. 9 digits gives you ns. within the second. Every second or so you could send the high-order digits. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency
HI On Jun 10, 2015, at 3:28 AM, Hal Murray hmur...@megapathdsl.net wrote: alan.ambr...@anagram.net said: How about a 1pS resolution TIC? :) An alternative way to describe that sort of problem is How accurately can you locate an edge? I haven't looked carefully at the Spartan 3E. You might be able to run a signal along a column through a slow path and clock the whole column at the same time. Then sort out how far it got. That slow path is basically a delay line with many taps. The delay line in an FPGA approach might get you to 20 ps. There is a lot of hand waving in the calibration process to get there. ( = figuring out that state A came before state B is based on things that are difficult to prove). If you do get it calibrated, you then find that it’s sensitive to both supply voltage and to temperature. The supply thing you can take care of with a good regulator. The “shifts all over the place when you put your thumb on it” T/C is not quite as easy to deal with. A TDC using an R/C and an ADC is a *much* easier way to go. It would take some experimentation, and maybe some duplicate logic for run time calibration. Or a 12 digit frequency counter? :) :) 12 digits is easy. Just wait long enough. So that turns into 2 games: How fast can you count? How many digits can you get in 1 second? Here is a toy that would be useful: assume you have a 10 MHz reference clock. make a design that captures something like a PPS and spits out the time-stamp on a serial port. I think Tom has a PIC that does that. The idea here is to use a faster clock so you get better resolution. How much resolution can you get with pure digital logic? (no delay lines) It depends on how much money you want to pay for your FPGA :) If you get one that will do both edges of a 600 MHz clock and run two phases, you can get to around 1/2 ns. Can you *believe* that 1/2 ns? well ….. Do you want to spend more money on a chip than a 500 ps counter would cost at auction …. Bob I'd like something like that watching the power line. You might need some sort of compression scheme or the serial port would get overloaded. 9600 baud is 1K characters per second. 60 Hz is 16 ms per cycle so you get 15 characters per cycle (plus a separator) unless there is noise on the line. 9 digits gives you ns. within the second. Every second or so you could send the high-order digits. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Using CPLD/FPGA or similar for frequency
Hi, This thread really makes me want to do an FPGA timing project. I have a Papilio One on hand, which uses the Spartan 3E. But what to do with it? It has to be something much more interesting than what a PicDiv or simple logic can do to make it worth my time. Hmm... How about a 1pS resolution TIC? :) Or a 12 digit frequency counter? :) :) It's not a proper time-nut project unless there's a nutty element... Alan ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
I'm up for either ... My thoughts are to try it out on a development board and if it works, maybe build a few for possible sale, and also release Gerbers and VHDL files. Regards, David Partridge -Original Message- From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of cfo Sent: 08 June 2015 15:09 To: time-nuts@febo.com Subject: Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider On Sun, 07 Jun 2015 11:23:40 +0100, David C. Partridge wrote: My reading so far of what's been said in this thread is that you might get good results using a CPLD/FPGA as a divider but ... . .. .. .. Thanks again Dave Is this going to be an open source project, or something you buy ? CFO -- E-mail:xne...@luna.dyndns.dk ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
On Mon, 08 Jun 2015 16:27:26 +0100, David C. Partridge wrote: I'm up for either ... My thoughts are to try it out on a development board and if it works, maybe build a few for possible sale, and also release Gerbers and VHDL files. Regards, David Partridge I have these cheap cards , that might be a nice start. CPLD Altera EPM240 (make sure you get the blue board) Ebay: 271520142479 Fpga (2 onboard PLL's) older Cyclone2 , but prob ok. Ebay: 400630255386 Programmer: Ebay: 200943750380 If they could be the heart of the system, then everybody could get started cheap. I'm using Quartus2 on Linux (Mint17) , works ok. But Modelsim needs some extra libs to function. CFO ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
On Sun, 07 Jun 2015 11:23:40 +0100, David C. Partridge wrote: My reading so far of what's been said in this thread is that you might get good results using a CPLD/FPGA as a divider but ... . .. .. .. Thanks again Dave Is this going to be an open source project, or something you buy ? CFO -- E-mail:xne...@luna.dyndns.dk ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
My reading so far of what's been said in this thread is that you might get good results using a CPLD/FPGA as a divider but ... . Bruce pointed me to Rubiola's paper http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf, and while I'm sure the lambda divider is excellent, there's a definite problem of needing to re-square the output after every stage if you want a multi-stage design. This makes me wonder if you'd end up adding enough additional jitter/phase noise to more than counteract the benefit of the lambda divider (which produces a stepped triangle wave). TANSTAAFL seems to apply here. My biggest concern is that if I build a multi-stage divider (*) using a single CPLD or FPGA, I could end up with cross-talk problems similar that encountered with multi-gate logic packages. I don't think it makes sense to use a CPLD if you need to use a separate package for each stage. I'm also a bit concerned by Bob Camp's comment: they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you could expect under similar conditions with something like AC or faster CMOS which suggests that it will be (at least 10dB) worse than my existing design :( I guess that it might work if the output were re-synched to the input using external D-flops after the main grunt work is done in a CPLD/FPGA. I'm also a bothered by the findings in http://rubiola.org/pdf-articles/conference/2014-eftf-Noise-in-digital-components.pdf which indicate that the lowest noise devices tested were the Altera Max 3000 series which Altera dsecribe as Mature so may be at risk of obsolescence Thanks to all for the discussion to date. (*) similar to my previous effort made with 74AC logic. Thanks again Dave ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
Hi As always, the real answer is “that depends”. If you are dividing to 1 pps from 10 MHz, the CPLD or FPGA is a fine answer to the question. It will give you some cool bells and whistles (like sync and advance / retard) without adding anything to the budget. If you wish to re-sync the output with a single gate D-FF running on the “wrong edge” of the 10 MHz, that’s easily done and it adds virtually nothing to the board space or cost. If you are building a low noise PLL and going from 160 MHz down to a 40 MHz analog phase detector (with a floor of -170 dbc/ Hz), the CLPD or FPGA isn’t a good choice. You can do the complete divide with a single package part and get lower noise. The board with the 160 MHz PLL on it is going to be a single purpose layout and it will live it’s life doing one thing. The board with the 1 pps divider might get re-purposed to do a variety of things. A “universal” FPGA board with some basic timing stuff (connectors / re-sync flip flops / input gates) on it might be a very useful thing to have around ….. On Jun 7, 2015, at 6:23 AM, David C. Partridge david.partri...@perdrix.co.uk wrote: My reading so far of what's been said in this thread is that you might get good results using a CPLD/FPGA as a divider but ... . Bruce pointed me to Rubiola's paper http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf, and while I'm sure the lambda divider is excellent, there's a definite problem of needing to re-square the output after every stage if you want a multi-stage design. This makes me wonder if you'd end up adding enough additional jitter/phase noise to more than counteract the benefit of the lambda divider (which produces a stepped triangle wave). TANSTAAFL seems to apply here. My biggest concern is that if I build a multi-stage divider (*) using a single CPLD or FPGA, I could end up with cross-talk problems similar that encountered with multi-gate logic packages. Internal cross talk on FPGA’s and CPLD’s is pretty much a non-issue. That assumes that the board is properly laid out and the supplies are well bypassed. Input and output cross talk can be reduced (but not always eliminated) by running differential inputs and putting “threat” signals on different i/o banks from each other. The “properly laid out” constraint with a FPGA / CPLD forces you to a 2 layer board pretty fast. Depending on the density and a few other things you may be past 6 layers. Yes that costs money. Bob I don't think it makes sense to use a CPLD if you need to use a separate package for each stage. I'm also a bit concerned by Bob Camp's comment: they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you could expect under similar conditions with something like AC or faster CMOS which suggests that it will be (at least 10dB) worse than my existing design :( I guess that it might work if the output were re-synched to the input using external D-flops after the main grunt work is done in a CPLD/FPGA. I'm also a bothered by the findings in http://rubiola.org/pdf-articles/conference/2014-eftf-Noise-in-digital-components.pdf which indicate that the lowest noise devices tested were the Altera Max 3000 series which Altera dsecribe as Mature so may be at risk of obsolescence Thanks to all for the discussion to date. (*) similar to my previous effort made with 74AC logic. Thanks again Dave ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
Hi Last time I saw university multi project wafer prices, the cost was around $5K for a run on a “not state of the art” fab process. That included absolutely nothing in the way of design assistance. It was strictly “we fab what you told us to do”. The “run date” for the chips was also a bit vague. They used space on other design runs, so you got about a 3 month window on when your parts might run. Eventually you got back a waffle pack with some die to go wire bond up. Often the trick was to take the work of several students and put in on a single chip. The *hope* was that nothing pathogenic happened in any of the designs to render the whole thing useless. The gotcha on ASIC’s os (of course) the running cost of this stuff. If you are using a bunch of parts is’t not to bad. If not, the phone call every 4 years or so about “you need to buy a new mask set for $XXX,XXX” gets a bit old. For a state of the art process add at least one more X to that number. Coming back to timing. Once you go to an ASIC, the ability to optimize for low jitter / good ADEV (or whatever) comes into the picture. There is no reason why there should be any worse performance on the ASIC than on any logic family you can find. All of the previous caveats about phase noise floors go away. That’s not to say that things like crosstalk between two pads that are 0.05 mm apart suddenly vanishes. You still have to take care of the i/o part of the design. Bob On Jun 6, 2015, at 1:49 PM, Attila Kinali att...@kinali.ch wrote: On Sat, 6 Jun 2015 09:52:11 -0400 Bob Camp kb...@n1k.org wrote: Was it a simple counter or was there enable/up/down/load type gating involved? What would you have done if you needed to run a bit faster? Bought a faster FPGA or gone to an ASIC. Could you buy a faster chip? For enough money there’s always a faster chip :) Even if it is OT, to give this a little economic perspective: Today, an ASIC starts to be cheaper than an FPGA solution at production volumes somewhere between 1000 and 10'000 pieces (in total). If you have working (synchronous) VHDL code, going ASIC is pretty straight forward and is mostly automatic. There are several fabs in Europe and Asia that offer node sizes between 180nm and 35nm for even very small runs and help you to convert your FPGA code to proper ASIC designs. A simple ASIC project is cheap enough, that some universities offer courses where students (in a master course) design their own chips, let them produce and measure their performance later, all cost covered by the university. (If i remember correctly, the cost was around 10kUSD per design and for 20 dies, half of them in QFP, half as nacked die) Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
rich...@karlquist.com said: I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope timebase. It was great because you just write a 17 bit counter in VHDL and there it is. You don't have to know anything about building digital hardware any more (40 years of experience wasted). Nobody cares about look ahead carry, etc. Is that really true? Or perhaps, what fraction of the digital design space does it apply to? How fast was your counter running? How fast would it run? Was it a simple counter or was there enable/up/down/load type gating involved? What would you have done if you needed to run a bit faster? Could you buy a faster chip? How much more could you get with tricky logic? I agree that modern tools and parts have allowed a lot more people to build digital circuits. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
The counter only had to run at ~50 MHz, on account of our mode locked laser ran at that frequency. I don't remember what the CPLD was rated at. Rick On 6/5/2015 8:19 PM, Hal Murray wrote: rich...@karlquist.com said: I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope timebase. It was great because you just write a 17 bit counter in VHDL and there it is. You don't have to know anything about building digital hardware any more (40 years of experience wasted). Nobody cares about look ahead carry, etc. Is that really true? Or perhaps, what fraction of the digital design space does it apply to? How fast was your counter running? How fast would it run? Was it a simple counter or was there enable/up/down/load type gating involved? What would you have done if you needed to run a bit faster? Could you buy a faster chip? How much more could you get with tricky logic? I agree that modern tools and parts have allowed a lot more people to build digital circuits. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
Hi On Jun 5, 2015, at 11:19 PM, Hal Murray hmur...@megapathdsl.net wrote: rich...@karlquist.com said: I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope timebase. It was great because you just write a 17 bit counter in VHDL and there it is. You don't have to know anything about building digital hardware any more (40 years of experience wasted). Nobody cares about look ahead carry, etc. Is that really true? Yes, it’s really true. Or perhaps, what fraction of the digital design space does it apply to? The portion that does not take the design directly to an ASIC. (at least in industry). Essentially the only thing done with discrete logic these days are minor i/o chores. How fast was your counter running? How fast would it run? That depends entirely on which FPGA or CPLD you buy. An old 100 MHz part will not go as fast as a 800 MHz part. In this case speed is the toggle rate on the counter. Was it a simple counter or was there enable/up/down/load type gating involved? What would you have done if you needed to run a bit faster? Bought a faster FPGA or gone to an ASIC. Could you buy a faster chip? For enough money there’s always a faster chip :) How much more could you get with tricky logic? The days of “tricky logic” ( = stuff the software does not understand) are now the days of “hand place (route) the gates in the FPGA”. It’s routing delay that gets you before gate speed in most cases. The software routers have gotten awfully good …. I agree that modern tools and parts have allowed a lot more people to build digital circuits. They did that only after they had been allowing mass conversion of designs over to silicon for about two decades. The tools you see today are nothing like what you had to use in the early 1990’s. The other thing that the design software has done is that it’s forced people to face up to timing constraints. Just as in the semiconductor industry, there is now a “process spec” that is used to constrain the design. If it passes when fully constrained and checked, it will work in production. No more blue wires. No more “oops!” re-spins on $20,000 pc boards. Bob -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
Hi Here’s an example: http://parts.arrow.com/item/detail/arrow-development-tools/bemicromax10#pg2e https://www.altera.com/products/fpga/max-series/max-10/overview.highResolutionDisplay.html There are other outfits that make similar parts that are at least as good. This is considered a low end chip right now. The part on the demo board is a mid point for the part size wise. It will run 400 MHz clocks without much bother at all. It also is quite happy doing multiple modulo divides to take those clocks down to multiple 1 pps outputs *and* have a load function on the counter. You have enough room to use them as time tags on inputs to the FPGA and store a few hours worth of data in memory. Can you do better with a faster part? sure can. Can you find cheaper parts? yes again. Is there a competitor’s part that will do it cheaper / faster / easier (pick one) - most certainly. If you can enter a schematic into free software, you can design a pps divider with a part like this. No need to learn a programming language to work with one. The process is roughly the same as learning a new pcb layout tool. Yes it runs on Linux and on Windows. I can’t buy the parts on the demo board for what they sell the board for. I can’t buy an 8 -10 layer board that size in single piece for what they sell the demo board for. I can’t get it assembled (BGA’s …) in one piece for what they sell the demo board for. I also can’t do multiples of that counter with discrete logic on a board that size. I also can’t buy all the chips that a counter that fast going that low would require (plus the board) for what the demo board costs. Bottom line, to use them, just buy them already on a board and mount that on whatever you are doing. No I’m not trying to sell you that demo board. I’m also not trying to convince you that there is one and only one family of parts that are worth using. The point is - the world started going over to FPGA’s in the mid 1980’s. Discrete logic design started to die out with ASIC’s in the early 1970’s. For large scale stuff it was dead by the end of the 1970’s. Forty years later, there are very few places (other than i/o) that discrete gates get used. The world has changed a lot since the 1970’s. Design any UART’s with discrete logic since about 1971? Bob On Jun 5, 2015, at 11:19 PM, Hal Murray hmur...@megapathdsl.net wrote: rich...@karlquist.com said: I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope timebase. It was great because you just write a 17 bit counter in VHDL and there it is. You don't have to know anything about building digital hardware any more (40 years of experience wasted). Nobody cares about look ahead carry, etc. Is that really true? Or perhaps, what fraction of the digital design space does it apply to? How fast was your counter running? How fast would it run? Was it a simple counter or was there enable/up/down/load type gating involved? What would you have done if you needed to run a bit faster? Could you buy a faster chip? How much more could you get with tricky logic? I agree that modern tools and parts have allowed a lot more people to build digital circuits. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
On Sat, 6 Jun 2015 09:52:11 -0400 Bob Camp kb...@n1k.org wrote: Was it a simple counter or was there enable/up/down/load type gating involved? What would you have done if you needed to run a bit faster? Bought a faster FPGA or gone to an ASIC. Could you buy a faster chip? For enough money there’s always a faster chip :) Even if it is OT, to give this a little economic perspective: Today, an ASIC starts to be cheaper than an FPGA solution at production volumes somewhere between 1000 and 10'000 pieces (in total). If you have working (synchronous) VHDL code, going ASIC is pretty straight forward and is mostly automatic. There are several fabs in Europe and Asia that offer node sizes between 180nm and 35nm for even very small runs and help you to convert your FPGA code to proper ASIC designs. A simple ASIC project is cheap enough, that some universities offer courses where students (in a master course) design their own chips, let them produce and measure their performance later, all cost covered by the university. (If i remember correctly, the cost was around 10kUSD per design and for 20 dies, half of them in QFP, half as nacked die) Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope timebase. It was great because you just write a 17 bit counter in VHDL and there it is. You don't have to know anything about building digital hardware any more (40 years of experience wasted). Nobody cares about look ahead carry, etc. I cleaned up the timing with conventional logic, so I don't know what the jitter of the CPLD was. We needed jitter in the low fs, so I am sure the CPLD was not OK without cleaning up, but then that was a lunatic fringe project. Rick Karlquist N6RK On 6/2/2015 6:13 AM, David C. Partridge wrote: Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? Regards, David Partridge ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
Thanks Bruce. That is an excellent option. I did a paper over a decade ago on the jitter and phase noise for Actel (Now Microsemi) comparing their eX device to the Xilinx CPLD. It was intended to show the eX device was preferable to the Xilinx CPLD. It makes a difference as to what device is selected. Jerry On Tue, Jun 2, 2015 at 11:17 PM, Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: You can always cleanup the outputs of the CPLD or FPGA by resynchronising the outputs to the input clock using a dedicated D flipflop for each output. Bruce On Wednesday, 3 June 2015 3:22 PM, Bob Camp kb...@n1k.org wrote: Hi A lot depends on exactly which CPLD or which FPGA you are looking at and how they put the guts of it together. If you find one that is “just right” it *might* be within 10 db of high speed CMOS. Since there is a 20 db delta between the HC you mention and the AC that leaves a bit of room. If you have a part with a bias generator in it, just forget about using it. You will have all sorts of strange spurs that come and go. They will be broadband. They will take the noise floor up into the 100 dbc / Hz range in some cases. If you are trying to use the internal PLL, it’s phase noise isn’t going to be great. Numbers like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output. As straight dividers, they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you could expect under similar conditions with something like AC or faster CMOS. You are more likely to get there on a fast CLPD than on an FPGA. Either way you can run into bum parts. Bob On Jun 2, 2015, at 9:13 AM, David C. Partridge david.partri...@perdrix.co.uk wrote: Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? Regards, David Partridge ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
Hi As always, the real answer it “that depends”. If your objective is wide band phase noise and you want to start from 100 MHz and get 10 MHz (fig 6 in the Lamda paper), you can get at least another 6 db with a simple divide by 10 chip than with all the fancy stuff. Bob On Jun 3, 2015, at 12:17 AM, Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: You can always cleanup the outputs of the CPLD or FPGA by resynchronising the outputs to the input clock using a dedicated D flipflop for each output. Bruce On Wednesday, 3 June 2015 3:22 PM, Bob Camp kb...@n1k.org wrote: Hi A lot depends on exactly which CPLD or which FPGA you are looking at and how they put the guts of it together. If you find one that is “just right” it *might* be within 10 db of high speed CMOS. Since there is a 20 db delta between the HC you mention and the AC that leaves a bit of room. If you have a part with a bias generator in it, just forget about using it. You will have all sorts of strange spurs that come and go. They will be broadband. They will take the noise floor up into the 100 dbc / Hz range in some cases. If you are trying to use the internal PLL, it’s phase noise isn’t going to be great. Numbers like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output. As straight dividers, they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you could expect under similar conditions with something like AC or faster CMOS. You are more likely to get there on a fast CLPD than on an FPGA. Either way you can run into bum parts. Bob On Jun 2, 2015, at 9:13 AM, David C. Partridge david.partri...@perdrix.co.uk wrote: Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? Regards, David Partridge ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Using CPLD/FPGA or similar for frequency divider
Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? Regards, David Partridge ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? Regards, David Partridge Yes, please consider it. I would be very interested in the results. We measured under 2 ps jitter for the PIC dividers [1] used with the cute little TADD-2 board [2]. One of these days I should measure your divider board with the same setup to see how it compares with a PIC. Like a CPLD/FPGA the PIC has the advantage of being fully synchronous and all on one die. /tvb [1] http://leapsecond.com/pic/ [2] https://www.tapr.org/kits_t2-mini.html ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
Programmable logic rocks. If you need a 13 bit counter, you can do that. It is easy to create alarms and special controls. Jerry On Jun 2, 2015 2:22 PM, David C. Partridge david.partri...@perdrix.co.uk wrote: Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? Regards, David Partridge ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
Hi A lot depends on exactly which CPLD or which FPGA you are looking at and how they put the guts of it together. If you find one that is “just right” it *might* be within 10 db of high speed CMOS. Since there is a 20 db delta between the HC you mention and the AC that leaves a bit of room. If you have a part with a bias generator in it, just forget about using it. You will have all sorts of strange spurs that come and go. They will be broadband. They will take the noise floor up into the 100 dbc / Hz range in some cases. If you are trying to use the internal PLL, it’s phase noise isn’t going to be great. Numbers like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output. As straight dividers, they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you could expect under similar conditions with something like AC or faster CMOS. You are more likely to get there on a fast CLPD than on an FPGA. Either way you can run into bum parts. Bob On Jun 2, 2015, at 9:13 AM, David C. Partridge david.partri...@perdrix.co.uk wrote: Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? Regards, David Partridge ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
david.partri...@perdrix.co.uk said: Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? A CPLD is a fine way to divide by a large number. Even the smaller FPGAs are probably overkill but they should work fine. If you are interested in jitter, the main problem is due to shared power/ground lines. With things like a CPLD, the usual way to get in trouble is to put several unrelated chunks of logic into the same chip. If you only have a single divider in a chip, I'd expect the output to be clean. You can get the same problem with AC/LVC scale logic with multiple sections if you use the sections for unrelated logic. That's one of the reasons the modern single gate packages work so well. You can't screwup and put two (or more) unrelated chunks of logic in the same chip. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
Am 02.06.2015 um 21:27 schrieb Tom Van Baak: Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? Regards, David Partridge Yes, please consider it. I would be very interested in the results. I have made a stamp sized board that has a Xilinx 2C64 Coolrunner II, a 1.8V regulator for the core voltage and the programming interface for the standard Xilinx USB-cable. (parallel cable may work but my laptop has no parallel port anymore.) It runs on 3.3V. All I/O pads are fanned out to a 100 mil grid, so you can mount it easily on square pad board or solder it to an unetched copper clad board. The layout is single sided plus unbroken GND on the bottom side. pic = https://picasaweb.google.com/lh/photo/4Bpcfouj8WH0shNGIyuVUtMTjNZETYmyPJy0liipFm0?feat=directlink (top right) The CPLD has 64 Flipflops and enough combinational logic to feed them all. It runs happily at 200 MHZ. Two of these chips can make a 1pps from 200 MHz in, and another 1pps that can be stepped in 5ns increments from -100nsec to +1 second. A 2c64 costs $2 or so at digikey. BTW, the other stamps on the picture are: top left: Crystec CVH950 100 MHz VCXO locked to 10 MHz. I was too slow with those 100 MHz Wenzels this week; these would have justified a better effort; also sth. better than an 4046 ;-) bottom left: NIST doubler from 100 MHz to 200 MHz using 2*BF862, slight gain, Low-Q tuned circuit on the output side bottom right: 200 MHz to 400 MHz Schottky doubler, SAW filter, ERA-4 to bring it to 12 dBm again The boards are home-etched; because of my daytime job my pps generator makes only slow progress... A 1:1 pdf of the layout is available; one can print it to foil if one has a good printer (OKI 852 works nicely) or a print shop that can do offset films will print it to document film for €5 to 10 per ISO A4 page+ If someone want to measure it, I can send him one of those Xilinx stamps; sooner or later I'll find the time do it myself but even then the repeatability would be interesting. Also, this morning I have published an update for my 220pV/sqrt Hz preamplifier; 10uF foil capacitors one actually can buy, circuit diagrams and Gerbers for the adventurous. Be warned, this version has never been fabricated, but the changes from its predecessor are relatively small. Most of the work was the step to Altium Designer 15, Direct-X support on my virtual Win7 machine and that my libraries from Protel-99 times desparately need some work. The update can be found at http://www.hoffmann-hochfrequenz.de/downloads/downloads.html . regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
On Tue, 2 Jun 2015 14:13:04 +0100 David C. Partridge david.partri...@perdrix.co.uk wrote: Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? It depends ;-) For most things it should be ok. You can reach lower levels of noise with single 74xxx parts as you will have lower interference between different parts of the circuitry. But how much better it might be and whether other effects might actually make the discrete solution worse, i cannot say. For some rule of thumb guide lines, the poster/paper by Caloso which he presented at EFTF last year where they measured noise parameters of 4 different FPGA families. The main result is that the larger the better is also true for low noise logic gates, but there are outliers. Phase noise jitter in digital electronics, by Calosso and Rubiola, 2014 http://rubiola.org/pdf-articles/conference/2014-eftf-Noise-in-digital-components.pdf There is quite some data missing there, but I guess they hit the page limit of the paper. Also testing different FPGA families would be quite nice. Attila Kinali -- _av500_ phd is easy _av500_ getting dsl is hard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
On Tuesday, June 02, 2015 02:13:04 PM David C. Partridge wrote: Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? ` Regards, David Partridge ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. It makes it easier to implement low noise lambda dividers which overcome most of the PN degradation of digital dividers. Also the FPGA can easily be reconfigured to produce outputs different from those originally implemented. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
You can always cleanup the outputs of the CPLD or FPGA by resynchronising the outputs to the input clock using a dedicated D flipflop for each output. Bruce On Wednesday, 3 June 2015 3:22 PM, Bob Camp kb...@n1k.org wrote: Hi A lot depends on exactly which CPLD or which FPGA you are looking at and how they put the guts of it together. If you find one that is “just right” it *might* be within 10 db of high speed CMOS. Since there is a 20 db delta between the HC you mention and the AC that leaves a bit of room. If you have a part with a bias generator in it, just forget about using it. You will have all sorts of strange spurs that come and go. They will be broadband. They will take the noise floor up into the 100 dbc / Hz range in some cases. If you are trying to use the internal PLL, it’s phase noise isn’t going to be great. Numbers like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output. As straight dividers, they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you could expect under similar conditions with something like AC or faster CMOS. You are more likely to get there on a fast CLPD than on an FPGA. Either way you can run into bum parts. Bob On Jun 2, 2015, at 9:13 AM, David C. Partridge david.partri...@perdrix.co.uk wrote: Is this a sensible thing to consider doing? Or would I be better sticking to AC/HC/AHC/LVC logic? Regards, David Partridge ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
