DJ Delorie wrote:
task automatic twait
Tried that first. Icarus didn't support it.
Actually, Icarus Verilog should support automatic tasks, even
the 0.9 version that you say you're running. Maybe there is a
bug that is tripped by a specific use?
--
Steve WilliamsThe woods
The developers are pleased to announce the next stable release in the 0.9
series, version 0.9.3. Icarus Verilog is a mostly complete implementation
of the hardware description language Verilog, as described in IEEE Std
1364-2005. It also includes a number of user requested extensions. It is
What are you trying to do? Are you really trying to synthesize your
Verilog design, meaning you are trying to generate a bit stream to
load into your FPGA? Or are you trying to compile and simulate your
Verilog?
Icarus Verilog is mostly a *simulator*, not a synthesizer. There were
some synthesis
This looks like a bug in Icarus Verilog, I'm afraid. Since all the
values in your expression have explicit sizes, the bit width need
not have carry space tacked on and the width should be 26bits.
In fact, in your example the bus is particularly nasty because it
causes the enablemask bits to be
I'm a little surprised that Icarus Verilog doesn't already pay
attention to the 4 in your %4b. In any case, this should do
the trick for you:
integer result;
... $display(%b, result[3:0]); ...
or failing that, you can try:
wire [3:0] tmp = result;
... $display(%b, tmp);
Patrick
Patrick Doyle wrote:
If I want to compile and test a particular version of Icarus Verilog
without messing my existing working installation, what's the best way
to do that?
I could configure it with a prefix of some temp directory and add that
directory (/bin) to my path.
Or I could just
Patrick Doyle wrote:
On Fri, Jul 9, 2010 at 3:20 PM, Stephen Williams
steve-tqxsilaruq3qt0dzr+a...@public.gmane.org wrote:
Patrick Doyle wrote:
If I want to compile and test a particular version of Icarus Verilog
without messing my existing working installation, what's the best way
to do
Eric Brombaugh wrote:
I ran this through Modelsim LE and got the following result:
# -7.093308,7.093308,7.093308,7
Running it through my copy of Icarus 0.9.2 gives the same answer you got
above, so I'm guessing that there's something odd going on with the way
Icarus is parsing complex
Ronald Mathias wrote:
I have downloaded the windows version of icarus verilog version 0.8.1.7
from [1]http://bleyer.org/icarus/. When I install the executable, I get
the executable vlpp.exe ivl.exe. in the lib\ivl directory. I know that
vlpp.exe is the preprocessor. But I do not
Some things have indeed been done. At the very least, you can
explicitly list in $dumpvars the array words that you want to
dump. The list needs to be explicit to prevent the explosion
of traces when you have large memories in your design.
Denis Daly wrote:
Hi,
I'm trying to simulate a
Stuart Brorson wrote:
Do you foresee any other difficulties? ... aside from simulating a
hydraulic circuit with spice or generating a layout.
Actually, my first thought was: What kinds of simulations (if any)
does one do in hydraulics? Are there any standard simulators? If so,
I'm planing a circuit where some chips have a wide variety of
different power supply requirements. I'm debating with myself
whether I should create symbols that have net= attributes for
all the various power types, or if I should attach attributes
from outside the symbol, or create pins for all
Jackson Nichol wrote:
I am hoping that someone can help me with a problem that I am having. I have
upgraded to Icarus Verilog for windows v0.9.1 from the www.bleyer.org/icarus
site.
Now when I run a simple test using the following two command line options
iverilog -o tb.vvp -s tb tb.v
The Verilog target for Icarus Verilog needs attention. If it
were it a usable (even compilable) state, it would be of use
to you. Is it sits, getting it it working order would be a great
summer project for somebody.
Philipp Klaus Krause wrote:
Is it possible to use Icarus to simplify Verilog
What verion of Icarus Verilog are you using? Icarus Verilog doesn't
support specify blocks before the 0.9 release. I think with the 0.9
release, it is default turned off, you enable it with -gspecify.
Philipp Klaus Krause wrote:
I want to model gate delays, but everything happens without delay.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
It's been *years* since we've made a new stable release, but the
time has finally come. Icarus Verilog 0.9.1 is the first release
of the 0.9 series! Get the source here:
ftp://ftp.icarus.com/pub/eda/verilog/v0.9/verilog-0.9.1.tar.gz
Since this is a
Larry Doolittle wrote:
Patrick -
On Tue, Mar 03, 2009 at 12:37:17PM -0500, Patrick Doyle wrote:
Should I have been able to find that somewhere else? (I am
asking in a tone of voice of I would like to know where to look for
answers such as these so I don't have to pester the mailing
Aanjhan R wrote:
The projects that am interested in are as follows (not in any specific order):
1. Usability improvements for ngspice/Gnucap - Under gaf
2. More interesting integrations with other tools. The new Tcl
interface adds a bunch of possibilities. I know one guy is using it to
Matt Ettus wrote:
In some Xilinx models, they make instantiations like this:
block instance(ports);
defparam instance.param=VALUE
This normally works ok. The problem is that inside the block,
generate statements are being used which are dependent on the value of
the parameter. What
Yamazaki R2 wrote:
I think i might have brought this up before but I wanted to bring this
up again. I know this would be kind of a big change to the way gEDA
works, but it would be nice to combine component's schematic, symbol,
and maybe pcb view into one file. Or at least the
Stuart Brorson wrote:
My old laptop has gotten old and is starting to act like it should be
retired. I use it for hacking (including working on gEDA stuff on
those now rare occasions when I get to it), writing, accessing the
net, and as the primary computer when I travel. Its replacement
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
I've successfully simulated a non-trivial PCI device using my new
simbus package, so I think it's time to make the first snapshot:
ftp://ftp.icarus.com/pub/eda/simbus/snapshots/simbus-20081125.tar.gz
Günter Dannoritzer wrote:
Jared Casper wrote:
On Sat, Aug 16, 2008 at 12:55 PM, Günter Dannoritzer [EMAIL PROTECTED]
wrote:
So with the latest development snapshot it gave me an assertion, but
with the git version a segmentation fault.
I saw this behavior as well, so I don't think it is
I think there is a bug report related to this in the icarus verilog
bugs tracker already. automatic tasks are not supported yes, and
there is a patch that I recently applied that reports this as a
proper error.
Günter Dannoritzer wrote:
Hi,
I tried compiling some Verilog code with a 'task
Günter Dannoritzer wrote:
Hi,
I tried to install Icarus Verilog from git and wonder whether I did
something wrong, as when things go wrong it crashes with a segmentation
fault.
I have to say that I have the latest development snapshot installed in
parallel in the standard path.
That
Kai-Martin Knaak wrote:
I am curious, just how heterogeneous the group of geda users and
developers is. So I thought, I'd start this little non-random sample poll
in the mailing list:
* What OS do you run geda applications on?
Linux (openSUSE 10.x)
Mac OS X (10.5 Intel)
* How did you
[EMAIL PROTECTED] wrote:
Good day!
I'm just a NB in Verilog design, sorry if my question is too stupid :)
I've started with free Xilinx ISE, but now i'm trying to do my best to
take part in icarus verilog community.
I became familiar with IV modelling system, but synth restrain my
Stuart Brorson wrote:
You're a power user. Power users generally know about system-gschemrc,
right? Or is that an invalid assumption?
That to me is an invalid and totally exasperating assumption,
actually. My opinion (for what it's worth) is that even power
users want things clear and
Does anybody have access to a Verilog-AMS tool and can said person
attempt to run the attached sample program? It is a very simple
program, but it is an attempt to test some of my understanding of
very basic principles of Verilog-AMS.
I understand that Verilog-AMS tools are very few and very
Dan McMahill wrote:
Stephen Williams wrote:
Does anybody have access to a Verilog-AMS tool and can said person
attempt to run the attached sample program? It is a very simple
program, but it is an attempt to test some of my understanding of
very basic principles of Verilog-AMS.
I understand
When that happens, you can send to my gmail account at
steveicarus
at the usual gmail.com. In fact, at this instant that would
be more convenient as I'm furiously hacking away on my mac,
where I can read gmail.
In the mean time, I'll look at the mail blocker. Spam musta
come from comcast.
Dan
Evan Lavelle wrote:
I can't run configure after downloading from git and sourcing
autoconf.sh. The output from configure ends with:
checking for BZ2_bzdopen in -lbz2... yes
checking for BZ2_bzdopen in -lbz2... (cached) yes
../../git2/verilog/vpi/configure: line 4002: syntax error near
Evan Lavelle wrote:
I was on autoconf 2.59, which comes with Centos 4.4. I couldn't
immediately find a 2.61 rpm, so I did the AP_CHECK_FUNCS hack, which let
everything compile.
Thanks. Maybe I'll just change it to AC_CHECK_FUNCS and leave it
at that. The difference is subtle and not really
More often then not, when I had problems like that with Icarus Verilog
it turned out to be different handling (by the O/S) of dynamically
allocated memory. One or the other (I forget which) will leave random
data in malloc'ed memory. If malloc'ed data is not initialized, this
can lead to code
Attila Kinali wrote:
On Fri, 25 Apr 2008 14:04:38 -0700
Stephen Williams [EMAIL PROTECTED] wrote:
As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, How are we going
Attila Kinali wrote:
On Sat, 26 Apr 2008 09:22:17 +0200
Hagen SANKOWSKI [EMAIL PROTECTED] wrote:
Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs.
Uhm... I don't think i have to comment on something uneducated
like this, do i?
Right, let's please not fall into this
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, How are we going to
run these generated files? I'm here looking for
Darren Stevens wrote:
Hello All,
I've been trying to use a Digilent XLA development board fitted with a Xilinx
spartan XCS10 fitted.
Since the Xilinx free tools for this chip don't include a synthesis tool I've
been trying to use Iverilog, with some success.
I'm surprised by that. I
Günter Dannoritzer wrote:
Hi,
I am using the system task $readmemh to init some ROM. Now my question
is, can I specify for the simulation with Icarus somewhere the path to
the file I am using with $readmemh?
I can think of 2 ways:
You can use $value$plusargs at run time to get the path you
Ahmad Sayed wrote:
John Griessen wrote:
Are you thinking of making your special parallel port driver
GPL and eventually part of linux? That would make a great tutorial
approach for iverilog...
when i reach reasonable point, i'm going to do so, I just want with this
discussion first to be
Ahmad Sayed wrote:
Dear all,
I have an idea of a project, but actually i'm software developer rather than
hardware designer, so i need you to help me to figure out the usability of
it, my idea in short focus on the circuit designed to work wih computer e.g.
computer prephierals.
I need to
Günter Dannoritzer wrote:
Stephen Williams wrote:
Question:
Does *anybody* use or even see value in the 32bit runtime support
that Icarus Verilog includes in 64bit builds? In particular, there
is support in the Icarus Verilog source for building simultaneously
a vvp (64bit) and a vvp32
Günter Dannoritzer wrote:
Hi,
I am looking into using Icarus Verilog with Teal/Truss, a C++ based
verification framework.
With Icarus 0.8.6 all tests but the last, with release of a_wire, are
working.
It's probably a matter of it not being implemented yet. Looks like
a candidate for a bug
Question:
Does *anybody* use or even see value in the 32bit runtime support
that Icarus Verilog includes in 64bit builds? In particular, there
is support in the Icarus Verilog source for building simultaneously
a vvp (64bit) and a vvp32 (32bit) to support 32bit VPI's transported
from 32bit
I believe the current Icarus Verilog vvp now has all the infrastructure
needed to support real-valued system functions, and there are some PLI2
functions that return real values. So the PLI1 support is just a matter
of providing the right translation layer code to make it work. Any
volunteers?
Werner Hoch wrote:
Ok. I've build it now with the bz2 devel files from the i586 arch.
(not yet in the build service)
Is there an easy way to test the 32bit verilog files?
I'm not an verilog user.
Yes, run vvp32 instead of vvp. The reason for the vvp32 is to
have a 32bit runtime that can
Dan McMahill wrote:
Stephen Williams wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
I've made a new release on the Icarus Verilog v0_8-branch git branch.
This is 0.8.6, which includes various safe fixes and updates to the
stable release. The source tarball and release notes are here
Daniel O'Connor wrote:
I now get..
[inchoate 9:43] ~/work/fpga/SA iverilog -y . -y
$XILINX/verilog/src/unisims -y $XILINX/verilog/src/XilinxCoreLib SA_test2.v
/usr/local/Xilinx/verilog/src/unisims/DCM.v:45: syntax error
/usr/local/Xilinx/verilog/src/unisims/DCM.v:45: error: syntax error in
Daniel O'Connor wrote:
[moved to -user]
On Sun, 2 Dec 2007, Stephen Williams wrote:
2) This looks like a problem long since fixed. Version?
I originally had 0.8.5 - I tried 0.8.6 but no change.
[inchoate 13:55] ~/projects/verilog-0.8.6 iverilog -V
Icarus Verilog version 0.8.6 ($Name
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
I've made a new release on the Icarus Verilog v0_8-branch git branch.
This is 0.8.6, which includes various safe fixes and updates to the
stable release. The source tarball and release notes are here:
Alan M. Feldstein wrote:
I'm using
-y dir-path
in the command file to add to the library module search path after using
an external tool to locate a module definitions in specific
subdirectories of
$(DV_ROOT)/libs
The problem is that such a subdirectory will often
IVL_LO_* for logic gates, and IVL_LPM_* for more complex gates.
That is of course a proper superset of what might come out of a
completed synthesis as a small handful of devices are purely virtual.
Adam Megacz wrote:
Stephen Williams [EMAIL PROTECTED] writes:
An approximation of the answer you
Adam Megacz wrote:
Does anybody know where I might find a comprehensive list of the EDIF
cell types emitted by icarus' synthesis back-end? I'd like to try to
get an idea of where the finish line is in terms of supporting all the
cell types it might throw at my stuff.
An approximation of the
This is the first time I've used git to spit out a release. I have
to say, using the git-gui to scan the commits really puts the
summary of changes right there in my face. Writing release notes
is tons easier this way.
Anyhow, the release tarball is here:
DJ Delorie wrote:
In theory, via-in-pad lets you bring an extra row out on the top
layer. It might mean the difference between 12 and 14 layers.
Also, if you avoid masking the bottom side of the via, you suddenly
have scope access to every pad of the BGA, which I've found to be
amazingly
Matt Ettus wrote:
Got another one for you. I am now using the latest git version as of
this morning. I get the following assertion when trying to compile
the attached files. They are short, but I put them in a tarball. The
code shouldn't do anything useful yet, but I believe it is
Your example below is within the skills of Icarus Verilog, but
there was a very recent fix for exactly this problem. According to
my git logs, it was committed 6/11/2007, which is *after* the very
last snapshot. So try the current git. (It should be in the present
but stopped CVS as well.)
Matt
Dave McGuire wrote:
On Jun 16, 2007, at 1:04 AM, Samuel A. Falvo II wrote:
Fortunately, gperf is an easy one to deal with. And damn cool to
*use*, too...I've used it in a number of projects and it has been
fantastic.
I did not even know it existed until just now.
It's said that GCC uses
Dave McGuire wrote:
On Jun 16, 2007, at 1:19 AM, Samuel A. Falvo II wrote:
Well, yeah, it was authored by Linus Torvalds, so that's to be
expected. I think it's gotten a _little_ looser since then, but it's
still predominantly assuming a Posix-compatible environment.
Not OS X or
Well, I've made my choice and I'm starting the transition over
to using git for Icarus Verilog. I've made my personal repository
and I've made anonymous access to it at the url:
git://icarus.com/~steve-icarus/verilog
It this repository you'll be able to *immediately* pull anything
that I
Samuel A. Falvo II wrote:
On 6/15/07, Stephen Williams [EMAIL PROTECTED] wrote:
Well, I've made my choice and I'm starting the transition over
to using git for Icarus Verilog. I've made my personal repository
and I've made anonymous access to it at the url:
Nice! I've never liked CVS
Adam Megacz wrote:
Stephen Williams [EMAIL PROTECTED] writes:
The v0.8 releases of Icarus Verilog have decent synthesis. The
synthesis is not at all Xilinx specific, but the code generators
are. But they needn't be. The FPGA target generates EDIF, so if
your intermediate form takes EDIF
DJ Delorie wrote:
FYI, this is what a prototype mp3 player module looks like:
http://www.delorie.com/electronics/alarmclock/mp3-proto.html
You can see how small the test speakers are in that photo.
We can also see that the desk is heaped up a couple of layers deep.
Not unlike my desk,
I'm looking for a simple gadget that can connect two RS232 ports
to an ethernet. I have a pair of solar grid-tie inverters in an
under-the-house utility room. I have ethernet down there but no
computers nearby and I would like to hook the RS232 monitoring
ports to software or a workstation
[EMAIL PROTECTED] wrote:
module test;
tri blah;
assign (pull1, strong0) blah = 0 ? 0 : 1;
assign blah = 0;
initial
$display(Blah should be 0: %d, blah);
endmodule
Output:
Blah should be 0: x
Bug. It appears that the muxz
This is pretty kool. You've got a big job in front of you!
Adam Megacz wrote:
So, now that the abits work is published [1] I plan on turning my
attention to connecting the dots, so to speak.
I've pretty much resigned myself to the fact that I'll have to
implement PAR by hand (VPR has
[EMAIL PROTECTED] wrote:
module A (input theInput, output theOutput);
parameter delay = 2;
// Do something
endmodule
module B (input theInput, output theOutput);
parameter delay = a.delay + 5;
A a(theInput, theOutput);
// Do
Looks like there are some bug reports in here. I'm pretty busy with
a big task at the moment so I may not get to these right away, so
that makes filing bug reports even more important.
[EMAIL PROTECTED] wrote:
The following compiles
(and probably shouldn't, unfortunately):
module
, Stephen Williams wrote:
[EMAIL PROTECTED] wrote:
I've made a BMP image format creating module for fun.
I maintain a 640x480 24-bits per pixel buffer and then write the data
out to a file.
At first I used a reg array, but came to find that each element of such
a structure
is expressed in vvp
[EMAIL PROTECTED] wrote:
I've made a BMP image format creating module for fun.
I maintain a 640x480 24-bits per pixel buffer and then write the data
out to a file.
At first I used a reg array, but came to find that each element of such
a structure
is expressed in vvp assembly as distinct
Günter Dannoritzer wrote:
I modified the vpi_user.c to not needing the other application that
comes along with that chapter 2 example and compiled it with:
iverilog-vpi pow_vpi.c vpi_user.c
iverilog -opow_test.vvp pow_test.v
vvp -M. mpow_vpi pow_test.vvp
The output I am getting is:
Günter Dannoritzer wrote:
Hi,
I am trying out some examples from the Sutherland PLI book and for the
calltf, compiletf, and sizetf routines the book uses PLI_INT32 type as
return type.
On the Icarus VPI page http://iverilog.wikia.com/wiki/Using_VPI page in
hello.c example I see the use
This is a new release of the 0.8.4 stable branch of Icarus Verilog.
The 0.8.4 release is for those people who are sticking with the
stable branch in order to avoid the occasional breakages of the
development snapshots, but still want some more important bug fixes.
The release is here:
Evan Lavelle wrote:
Günter Dannoritzer wrote:
Andy Peters wrote:
Does iverilog support SDF backannotation? The SDF has the delay
information.
Here are some information about that and a link to a previous discussion:
http://iverilog.wikia.com/wiki/Graffiti#SDF_support
I added a section
I'm fiddling with gschem/gattrib/gsch2pcb/pcb and find that I may
want to report bugs. What I need now, though, is a place front and
center that has links to the various bug reporting databases. I
know that there are a few on sourceforge, but there is nothing
written (other then mailing list lore)
Are the Layers controls dialog box buttons connected to anything?
I try to move one of the existing layers out of the group that it
is in to a group of its own (I'm trying to create a ground plane)
but it doesn't stick. It's as if the radio button of the group
select are not connected to
[EMAIL PROTECTED] wrote:
Nested for loops don't seem to work in iverilog.
it would seem that only the inner loop is updated.
Consider the following:
module TestMultiplier;
reg signed [7:0 ] x, y;
wire signed [15:0] z;
initial
begin
$dumpvars;
[EMAIL PROTECTED] wrote:
On Sat, Mar 10, 2007 at 10:11:32PM -0500, [EMAIL PROTECTED] wrote:
Nested for loops don't seem to work in iverilog.
it would seem that only the inner loop is updated.
reg signed [7:0 ] x, y;
for (x = -128; x 128; x = x + 1)
Stop right there. x128
Stuart Brorson wrote:
* Any open-source organization can have several proposed projects for
a Google-supported student to work on. The list of projects is being
formulated and will be posted on the gEDA website soon. Once that's
done, students are invited to apply to work on one or another
Stuart Brorson wrote:
The meeting will be an open and informal working session. Bring your
laptop *and* wireless card! Some items on the agenda are:
* Steve's FPGA design flow
Is that me you are speaking of? Should I be trying to figure out
irc stuffies?
--
Steve Williams
John Griessen wrote:
Creating google checkout buttons is easy -- if you have no shipping
costs, (as in FOSS added to project CVS or SVN repository), you could
have a series of them for small project chunks, and they get paid as you
go...
Take for instance the $500 project. divide it into
al davis wrote:
Why all that overhead?
The people who made the software have already established a
track record. Anyone funding it will do so based on that. We
don't need the middleman. They can just send a check.
An advantage of electronic payments is that they can be done
John Griessen wrote:
Stephen Williams wrote:
al davis wrote:
An advantage of electronic payments is that they can be done
internationally with little fuss by credit card.
I can't see paying just anyone who comes along for enhancements to an
active project.
Well, that's up to the client
OK, I'm an idiot. How do I create a local (as in local to my
design directory) library of PCB footprints? All the documentation
I see suggests that it will automatically search in the packages
directory in the current workig directory. No?!
--
Steve WilliamsThe woods are lovely,
DJ Delorie wrote:
OK, I'm an idiot. How do I create a local (as in local to my design
directory) library of PCB footprints? All the documentation I see
suggests that it will automatically search in the packages
directory in the current workig directory. No?!
Note that a local directory
DJ Delorie wrote:
I'm puzzled by this response. Under File-Preferences in the
Library tab there is an entry box for Element directories that
asks for a colon separated list of directories. Where does this
list get stored?
These are the times I like it when I'm wrong. Both gtk and lesstif
DJ Delorie wrote:
Thank you Steve. Not speaking for the PCB developers, but I'm sure they
appreciate the bug reports; I know I do.
We appreciate all the feedback, with the understanding that we can
only get to a tiny percentage of it at a time, as there's only a few
of us, and we only do
John Griessen wrote:
wart -- Is there a way to set up iverilog with gtkwave? Why is ver 2.0
seemingly dead? and the latest version debian package is 1.3.81? And
gtkwave seems to have two home page sites saying they have the most
recent version -- one 1.3.24 and the other 3.0.22?
GTKWave
Dan McMahill wrote:
John Griessen wrote:
wart -- Is there a way to set up iverilog with gtkwave? Why is ver
2.0 seemingly dead? and the latest version debian package is 1.3.81?
And gtkwave seems to have two home page sites saying they have the
most recent version -- one 1.3.24 and the
Can I use gattrib to edit the attributes of a symbol? I have some
largish symbols that I'm incrementally working on, and editing
attributes such as pintype and pinseq are a burden. (Meaning I
see no way to do it within gschem.) But when I try to load a
symbol file into gattrib I get a SEGV:
Günter Dannoritzer wrote:
Stephen Williams wrote:
To add an add-on like a vpi package, you don't need to rebuild
the Icarus Verilog package! Just have the myhdl rpm drop the .vpi
in the right directory at install time. How does that affect Icarus
Verilog packaging?
Yes, I undestand
Günter Dannoritzer wrote:
One change done by Werner Hoch is to add build requires depending on
x86_64. I added another BuildRequires for openSuse 10.2:
-
%ifarch x86_64
BuildRequires: bzip2-32bit, glibc-devel-32bit, glibc-32bit, zlib-devel-32bit
BuildRequires: termcap-32bit,
Michael Sokolov wrote:
On some rare occasions a paid client will have me develop some piece of
software or firmware that would actually have value to humanity. On
those rare occasions I always ensure that the work gets open-sourced,
if necessary without the client's knowledge. Other times I
In the interest of breaking down barriers to further Icarus Verilog
use in the real world, I've been looking at adding support for Denali
models. This because I've encountered interest from others in the
past, and I do keep running into them during day job as well.
I contacted Denali and there
Ales Hvezda wrote:
Hi,
[snip]
It is possible for some good Samaritan to compile for windows and make
available all the updated gEDA packages?
I've had the make the Windows port available discussion many many times
(both virtually and in person). Just this last week I was talking to
DJ Delorie wrote:
Or be prepared to pay my consulting rates.
Do we need a www.gedaconsulting.org ?
I could get behind something like that.
Or rather gedaconsulting.com.
--
Steve WilliamsThe woods are lovely, dark and deep.
steve at icarus.com But I have promises to
al davis wrote:
On Tuesday 05 December 2006 14:23, Stuart Brorson wrote:
Or be prepared to pay my consulting rates.
To all reading this .. Please take this as an invitation.
There are no problems, only unmet business opportunities.
One way to increase the priority of any task is to pay
ldoolitt-dhTElhTvxjT/[EMAIL PROTECTED] wrote:
I have added some odd features
over the past couple of years. Like the ability to automatically
create a .ucf file with timing goals in it based on the comments
in the top level Verilog module:
module stacker(
input clk, // timespec
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Icarus Verilog has lacked a User Guide for too long now, so I've
started a documentation Wiki here: http://iverilog.wikia.com.
I've seeded it with some documentation that I've been hoarding
for a while now, and also got the basics of the layout more
Hi,
I've noted that the Icarus Verilog 0.8 branch gets widespread
use, and also the devel branch is still unstable, so I'm still
actively maintaining the 0.8 branch; and that leads us to the
new release 0.8.3.
This is a stable, incremental release of the compiler. It only
fixes bugs and some
1 - 100 of 102 matches
Mail list logo
