Re: z9 / z10 instruction speed(s)

2010-03-13 Thread Shmuel Metz (Seymour J.)
In , on 03/12/2010 at 02:24 PM, Martin Packer said: >Seymour, wrong by about a decade :-) ... Eight years. >3090 was first to have true Expanded Storage, 9021 the last. What about the 9121 and 9221? >With CMOS we had the "partition real memory" thing. Weren't the low end ES/9000 boxen CMO

Re: z9 / z10 instruction speed(s)

2010-03-12 Thread Martin Packer
Seymour, wrong by about a decade :-) ... 3090 was first to have true Expanded Storage, 9021 the last. With CMOS we had the "partition real memory" thing. Unless it's ME that is wrong by about a decade. :-) Martin Packer, Mainframe Performance Consultant, Worldwide Banking Center of Excellence,

Re: z9 / z10 instruction speed(s)

2010-03-12 Thread Shmuel Metz (Seymour J.)
In <1228950277-1267928263-cardhu_decombobulator_blackberry.rim.net-10127518...@bda026.bisx.prod.on.blackberry>, on 03/07/2010 at 02:17 AM, Ted MacNEIL said: >A rose is a rose is a rose. But a rose is not a sardine. >MSUs are just MIPS multiplied by a (marketting) constant or 5. No. --

Re: z9 / z10 instruction speed(s)

2010-03-12 Thread Shmuel Metz (Seymour J.)
In , on 03/08/2010 at 10:35 AM, George Henke said: >I don't see anyone complaining about 64-bit memory being to much and >asking to bring back Expanded Storage and paging. Apples and oranges. AFAIK the 308x boxen were the last to have true expanded storage instead of arbitrarily labelling

Re: z9 / z10 instruction speed(s)

2010-03-12 Thread Shmuel Metz (Seymour J.)
In , on 03/07/2010 at 06:35 AM, Timothy Sipples said: >There are, and very many. You're not speaking the same language that he is. >In my previous post it should be obvious that "smaller" means anybody >with capacity below a hypothetical non-kneecapped 7-way System z9 BC. Just as it should

Re: z9 / z10 instruction speed(s)

2010-03-12 Thread Shmuel Metz (Seymour J.)
In , on 03/08/2010 at 02:37 PM, George Henke said: >What is not just or equitable is for IBM to view EDS' efficiency and >profits from "economies of scale" as a loss of revenue to themselves >(IBM) and then create a pricing scheme that appropriates those profits >from such efficiencies for th

Re: z9 / z10 instruction speed(s) -- OCTANE of CPUs

2010-03-10 Thread Tony Harminc
On 10 March 2010 16:30, zMan wrote: > > On Wed, Mar 10, 2010 at 4:11 PM, Rick Fochtman wrote: > > > Not so much high-horsepower engines, but rather high-compression engines. > > Makes a HUGE difference in aircraft reciprocating engines. Higher > > compression leads to higher heat buildup in the c

Re: z9 / z10 instruction speed(s) -- OCTANE of CPUs

2010-03-10 Thread zMan
On Wed, Mar 10, 2010 at 4:11 PM, Rick Fochtman wrote: > Not so much high-horsepower engines, but rather high-compression engines. > Makes a HUGE difference in aircraft reciprocating engines. Higher > compression leads to higher heat buildup in the cylinder and that can lead > to pre-ignition, wit

Re: z9 / z10 instruction speed(s) -- OCTANE of CPUs

2010-03-10 Thread Rick Fochtman
Not so much high-horsepower engines, but rather high-compression engines. Makes a HUGE difference in aircraft reciprocating engines. Higher compression leads to higher heat buildup in the cylinder and that can lead to pre-ignition, with seriously detrimental effect on the engine and the power c

Re: z9 / z10 instruction speed(s) -- OCTANE of CPUs

2010-03-10 Thread Ron Hawkins
Steve, So how good is this petrol that avoids detonation? I don't see that idea catching on... (GD&R) Ron > > 100LL (Low Lead -- as in TetraEthyl Lead) is needed to avoid detonation > in high horsepower engines. > -- For IBM-

Re: z9 / z10 instruction speed(s)

2010-03-09 Thread Edward Jaffe
Bruno Sugliani wrote: On non z/OS platform like x86 with Linux or Windows servers, we often use Dev or Test machines at a purposely less than 50% capacity allowing DR on the test machines as the remaining CPU power is available. Contrary to what a lot of people say about mainframe, using CPU's at

Re: z9 / z10 instruction speed(s)

2010-03-09 Thread George Henke
speed of a 1 cpu z/10. There is a huge chunk of > this equation that I'm totally missing. How does a z/10 get so much more > done? > > > > kind regards, Lindy > > > > -Original Message- > > From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.

Re: z9 / z10 instruction speed(s)

2010-03-09 Thread Bruno Sugliani
On Mon, 8 Mar 2010 14:43:07 -0600, Rick Fochtman wrote: >But it makes excellent sense in the context of failure and recovery. >Having a spare "engine" to switch over to in the event of a failure in >the primaty engine(s) can make a HUGE difference for a shop that needs >to maximize availability.

Re: z9 / z10 instruction speed(s)

2010-03-09 Thread Richards, Robert B.
...@bama.ua.edu] On Behalf Of George Henke Sent: Monday, March 08, 2010 7:15 PM To: IBM-MAIN@bama.ua.edu Subject: Re: z9 / z10 instruction speed(s) >And, the real reason (as unpopular as it may be), is cost. No, the real reason is manipulation of supply and de

Re: z9 / z10 instruction speed(s)

2010-03-09 Thread Steve Comstock
Timothy Sipples wrote: Steve Comstock writes: I would guess the focus here was on jobs, plain and simple. Maybe installed mainframe MIPS are increasing, but jobs, especially for z/OS staff, appear to be declining (esp. in the US, but some on the list have mentioned similar trends in Europe).

Re: z9 / z10 instruction speed(s)

2010-03-09 Thread Timothy Sipples
Steve Comstock writes: >I would guess the focus here was on jobs, plain and simple. >Maybe installed mainframe MIPS are increasing, but jobs, >especially for z/OS staff, appear to be declining (esp. in >the US, but some on the list have mentioned similar trends >in Europe). I'm not sure if that's

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Gerhard Postpischil
On 3/8/2010 7:15 PM, George Henke wrote: And, the real reason (as unpopular as it may be), is cost. No, the real reason is manipulation of supply and demand by a monopoly. Perhaps some remember the days of the Cabbage Patch dolls. The manufacturer limited production while aggressively creating

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Joel C. Ewing
z/10 get so much more done? > > kind regards, Lindy > > -Original Message- > From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf > Of R.S. > Sent: 7. maaliskuuta 2010 2:23 > To: IBM-MAIN@bama.ua.edu > Subject: Re: z9 / z10 instruction speed(

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread George Henke
>And, the real reason (as unpopular as it may be), is cost. No, the real reason is manipulation of supply and demand by a monopoly. Perhaps some remember the days of the Cabbage Patch dolls. The manufacturer limited production while aggressively creating within every young girl the uncontrollable

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Ted MacNEIL
>why would I NOT use every CP available? I think this is a strawman argument. The CP's are installed, but not available. The microcode determines what is available. And, the real reason (as unpopular as it may be), is cost. You didn't pay to see those cards. - Too busy driving to stop for gas!

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread George Henke
>Failover is but one of many reasons why not using every CPU in the >book >makes sense. However, George Henke's contention is that >kneecapping CPUs is >somehow "wrong" -- that not using all the available speed is a bad idea. >Taken to its logical conclusion, not firing up every CPU in the book is

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread zMan
On Mon, Mar 8, 2010 at 3:45 PM, zMan wrote: > On Mon, Mar 8, 2010 at 3:43 PM, Rick Fochtman wrote: > >> - >> >> Given the axioms of the discussion, it would be an entire book. The >> contention was that IBM shipping capacity that is

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Tony Harminc
On 8 March 2010 15:43, Rick Fochtman wrote: > - > > Given the axioms of the discussion, it would be an entire book. The > contention was that IBM shipping capacity that isn't used "doesn't make > sense". > ---

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Steve Comstock
Timothy Sipples wrote: Radoslaw Skorupka writes: Can I ask where are new customers of this very affordable platform? Many (though not all) are in the developing world. That's why it's called "developing," I guess. :-) Some places need new credit card processing systems (to pick an example) bec

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Timothy Sipples
Radoslaw Skorupka writes: >Can I ask where are new customers of this very >affordable platform? Many (though not all) are in the developing world. That's why it's called "developing," I guess. :-) Some places need new credit card processing systems (to pick an example) because they don't have them

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread zMan
On Mon, Mar 8, 2010 at 3:43 PM, Rick Fochtman wrote: > - > > Given the axioms of the discussion, it would be an entire book. The > contention was that IBM shipping capacity that isn't used "doesn't make > sense". > --

Re: History; was "z9 / z10 instruction speed(s)"

2010-03-08 Thread Ed Gould
---SNIP - Town & Country charge seems right but do not remember. --- T &

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Rick Fochtman
- Given the axioms of the discussion, it would be an entire book. The contention was that IBM shipping capacity that isn't used "doesn't make sense". - But it makes excell

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Scott Rowe
--- From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of Scott Rowe Sent: Monday, March 08, 2010 12:32 PM To: IBM-MAIN@bama.ua.edu Subject: Re: z9 / z10 instruction speed(s) Wow, what an inappropriate analogy. >>> George Henke 3/8/2010 12:24 PM >>> Agr

Re: History; was "z9 / z10 instruction speed(s)"

2010-03-08 Thread Rick Fochtman
- Hershey bars cost a nickel") I'm dating myself, but I can remember buying Hershey bars at two for a nickel.

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Anne & Lynn Wheeler
The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well. eamacn...@yahoo.ca (Ted MacNEIL) writes: > A contention which I disagree with. > It's cheaper to build one type of chip/card, and use other methods to > limit capac

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Ken Porowski
du] On Behalf Of Ted MacNEIL Sent: Monday, March 08, 2010 3:15 PM To: IBM-MAIN@bama.ua.edu Subject: Re: [IBM-MAIN] z9 / z10 instruction speed(s) >So the next time I fill up at the gas station the price should be based >on horsepower. Actually, that analogy is a bit flawed. Higher horsepower r

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Ted MacNEIL
>So the next time I fill up at the gas station the price should be based on horsepower. Actually, that analogy is a bit flawed. Higher horsepower requires, usually, more gas/octane. So, at the same price per gallon, the more powerful vehicles are already 'penalised'. - Too busy driving to stop f

Re: z9 / z10 instruction speed(s) -- OCTANE of CPUs

2010-03-08 Thread Thompson, Steve
> So the next time I fill up at the gas station the price should be based on > horsepower. All the SUV's should pay vastlly more for the same gas that I > use for my Honda Civic. > > I always use high-test since high-octane is always better even for small > cars, better mileage and cooler runnin

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread George Henke
It is comforting to know that satire is alive and well in IT. How boring life would be without it. >However, as I recall it being explained to me by another, the "tier >based" pricings started when a big outsourcer (EDS?) would bid for >small companies' IT business. EDS was cheaper because they h

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Pommier, Rex R.
capacity and features you will never need. Back to sitting on the sidelines watching the debate. :-) Rex -Original Message- From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of Scott Rowe Sent: Monday, March 08, 2010 12:32 PM To: IBM-MAIN@bama.ua.edu Subject:

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Edward Jaffe
George Henke wrote: Capacity based pricing has nothing but "greed" written all over it. I'm glad IBM and many ISVs offer such steep discounts to smaller customers that choose to enable/use only a subset of the potential processing capacity available on the z10. Without those discounts, man

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Scott Rowe
Wow, what an inappropriate analogy. >>> George Henke 3/8/2010 12:24 PM >>> Agreed. So the next time I fill up at the gas station the price should be based on horsepower. All the SUV's should pay vastlly more for the same gas that I use for my Honda Civic. I always use high-test since high-octa

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread zMan
On Mon, Mar 8, 2010 at 12:24 PM, George Henke wrote: > So the next time I fill up at the gas station the price should be based on > horsepower. All the SUV's should pay vastlly more for the same gas that I > use for my Honda Civic. > Well, they do pay more for their vehicles -- and engine upgra

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread McKown, John
> -Original Message- > From: IBM Mainframe Discussion List > [mailto:ibm-m...@bama.ua.edu] On Behalf Of George Henke > Sent: Monday, March 08, 2010 11:24 AM > To: IBM-MAIN@bama.ua.edu > Subject: Re: z9 / z10 instruction speed(s) > > Agreed. > > So the

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread McKown, John
> -Original Message- > From: IBM Mainframe Discussion List > [mailto:ibm-m...@bama.ua.edu] On Behalf Of George Henke > Sent: Monday, March 08, 2010 9:08 AM > To: IBM-MAIN@bama.ua.edu > Subject: Re: z9 / z10 instruction speed(s) > > How can anyone have too many mai

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread George Henke
Agreed. So the next time I fill up at the gas station the price should be based on horsepower. All the SUV's should pay vastlly more for the same gas that I use for my Honda Civic. I always use high-test since high-octane is always better even for small cars, better mileage and cooler running en

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Ted MacNEIL
>The contention was that IBM shipping capacity that isn't used "doesn't make >sense". A contention which I disagree with. It's cheaper to build one type of chip/card, and use other methods to limit capacity, which is what software pricing is based on. I knew, in the mid-1980's, when IBM introdu

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Anne & Lynn Wheeler
E http://www.garlic.com/~lynn/2010e.html#31 What was old is new again (water chilled) http://www.garlic.com/~lynn/2010e.html#36 What was old is new again (water chilled) http://www.garlic.com/~lynn/2010e.html#42 search engine history, was Happy DEC-10 Day http://www.garlic.com/~lynn/2010e.h

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread George Henke
Let's not be "bit wise, and byte foolish". There is merit in "intentionally overcapcitating" not just in MIPS, but also DASD. I don't see anyone complaining about 64-bit memory being to much and asking to bring back Expanded Storage and paging. On Mon, Mar 8, 2010 at 10:30 AM, zMan wrote

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread zMan
On Mon, Mar 8, 2010 at 10:24 AM, Scott Rowe wrote: > Timothy, > > Even if there was no kneecapping, there could still be CPUs turned off and > on, so the minimal configuration would be a single CPU z9BC, not a 7 way. > Given the axioms of the discussion, it would be an entire book. The contentio

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Scott Rowe
Timothy, Even if there was no kneecapping, there could still be CPUs turned off and on, so the minimal configuration would be a single CPU z9BC, not a 7 way. >>> Timothy Sipples 3/7/2010 6:35 AM >>> Peter Farley writes: >But Tim, there *aren't* any "smaller" mainframe customers >any more (at

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread George Henke
How can anyone have too many mainframe MIPS? Really? Dahh. Just look at SHADOW, the Data Direct Product that enables a TCB workload, through some niffty fancy footwork, to run workloads on a Ziip processor which handles SRB only workloads. I have a former client who automagicall

Re: z9 / z10 instruction speed(s)

2010-03-08 Thread Tom Marchant
On Sat, 6 Mar 2010 19:25:35 -0500, Timothy Sipples wrote: >a fully >configured System z9 BC (until end of June). I don't like MIPS metrics, but >for those that still do it'd be thousands of MIPS. Thousands? Not quite. >Now IBM introduces the System z10 BC, and you upgrade. You get thousands >mo

Re: z9 / z10 instruction speed(s)

2010-03-07 Thread R.S.
Timothy Sipples pisze: [...] By the way, IBM substantially reduced the price of z/VSE for many/most customers (including smaller ones) via the new MWLC sub-capacity licensing for Version 4, so again I have no idea where you're getting your information. Same with z/VM: IBM has slashed the price, b

Re: z9 / z10 instruction speed(s)

2010-03-07 Thread Gerhard Postpischil
On 3/8/2010 1:03 AM, Tony Harminc wrote: I don't know about a total IT budget of $38k, but in 1975 licensed software was pretty much a novelty. The first priced version of MVS (or any other IBM OS except perhaps ACP/TPF?) had yet to appear, and most software was written in house. I worked for A

Re: z9 / z10 instruction speed(s)

2010-03-07 Thread Ed Gould
--SNIP- Hershey bars cost a nickel") > I don't know about a total IT budget of $38k, but in 1975 licensed software was pretty much a novelty. The first priced version of MVS (or any other IBM OS exce

Re: z9 / z10 instruction speed(s)

2010-03-07 Thread Tony Harminc
On 7 March 2010 06:35, Timothy Sipples wrote: > > For reference, when you convert $150,000 in 2009 to 1975, you get $38,040. > That is, a total IT budget of $38,040 in 1975 would be equivalent, in > Consumer Price Index terms, to a $150,000 budget in 2009. > > I don't know Did anybody work fo

Re: z9 / z10 instruction speed(s)

2010-03-07 Thread Timothy Sipples
Peter Farley writes: >But Tim, there *aren't* any "smaller" mainframe customers >any more (at least not in the USA). There are, and very many. I don't know where you're getting your information. In my previous post it should be obvious that "smaller" means anybody with capacity below a hypothetic

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread Anne & Lynn Wheeler
li...@akphs.com (Phil Smith III) writes: > If you look at carefully written PC software like, say, Steve Gibson's > stuff (www.grc.com -- not a plug, just an example that comes to mind), > you'll see incredibly rich and powerful stuff that fits in the palm of > your PC's hand, so to speak. http://w

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread Phil Smith III
On Sat, Mar 6, 2010 at 8:43 PM, Lindy Mayfield wrote: >This has been a very interesting thread for me. If I remember correctly from >the time I saw the z/10 with plexiglass outsides and a hardware guy there to >explain what was what, and one of the things he told me was the cpu speed was >(I

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread Ted MacNEIL
>I don't like MIPS metrics A rose is a rose is a rose. MSUs are just MIPS multiplied by a (marketting) constant or 5. - Too busy driving to stop for gas! -- For IBM-MAIN subscribe / signoff / archive access instructions, send ema

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread Lindy Mayfield
more done? kind regards, Lindy -Original Message- From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of R.S. Sent: 7. maaliskuuta 2010 2:23 To: IBM-MAIN@bama.ua.edu Subject: Re: z9 / z10 instruction speed(s) Edward Jaffe pisze: [...] > People with PC-only experien

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread Farley, Peter x23353
-Original Message- From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of Timothy Sipples Sent: Saturday, March 06, 2010 7:26 PM To: IBM-MAIN@bama.ua.edu Subject: Re: z9 / z10 instruction speed(s) > Note that I don't speak for IBM, but let me come right out

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread R.S.
Henry Willard pisze: "R.S." wrote: Edward Jaffe pisze: [...] People with PC-only experience are always astonished when I tell them about modern mainframe provisioning capabilities. They always assume when your hard drive fills up you need a new one or when your CPU is too slow you need a new o

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread Henry Willard
"R.S." wrote: > Edward Jaffe pisze: > [...] > > People with PC-only experience are always astonished when I tell them > > about modern mainframe provisioning capabilities. They always assume > > when your hard drive fills up you need a new one or when your CPU is too > > slow you need a new one. W

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread Charles Mills
Now there you go being logical again. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of Timothy Sipples Sent: Saturday, March 06, 2010 4:26 PM To: IBM-MAIN@bama.ua.edu Subject: Re: z9 / z10 instruction speed(s) Leaving aside the

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread Timothy Sipples
Leaving aside the important point that System z is certainly not the only CPU to offer the option of kneecapped CPUs -- Intel Celeron, anyone? -- imagine (briefly) a world in which CPU kneecapping was not available. Now, what would be the smallest capacity System z available? Answer: a fully config

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread R.S.
Edward Jaffe pisze: [...] People with PC-only experience are always astonished when I tell them about modern mainframe provisioning capabilities. They always assume when your hard drive fills up you need a new one or when your CPU is too slow you need a new one. What we do seems like magic to t

Re: z9 / z10 instruction speed(s)

2010-03-06 Thread Anne & Lynn Wheeler
The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well. jmfbahciv writes: > ROTFLMAO. A typing fo-paw? re: http://www.garlic.com/~lynn/2010e.html#47 z9 / z10 instruction speed(s) yep ... oh well .. s/invented/invi

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread Shane Ginnane
Until you tell them the (upfront) cost to get into a mainframe - or the cost to turn on those CPs. Then the look of awe turns to derisive laughter. And growing DASD is only a big deal to us because of our history - ask gil about ZFS; ask a Linux admin about LVM (or even EVMS). Who cares about the

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread Edward Jaffe
zMan wrote: ... distributed folks don't understand issues like "small" volumes (226GB being smaller than the hard drive in my laptop)... It has already been said by IBM, but obviously bears repeating... The 226GB per volume EAV limit is nowhere near the *architectural* limit of EAV--which is

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread Blaicher, Chris
rocessors turned on. $ Chris Blaicher Phone: 512-340-6154 Mobile: 512-627-3803 -Original Message- From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of zMan Sent: Friday, March 05, 2010 1:46 PM To: IBM-MAIN@bama.ua.edu Subject: Re: z9 / z10 instruction sp

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread zMan
On Fri, Mar 5, 2010 at 2:01 PM, Edward Jaffe wrote: > Today's mainframe dynamic provisioning capabilities are truly leading-edge, > and improving with each new generation. > > We can dynamically grow any DASD volume--on the fly--up to 226GB in size. > We can download and dynamically apply a patch

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread Edward Jaffe
George Henke wrote: This is simply incredible, to think that IBM would deliberately run BCT loops to throttle, slowdown, CPs. It is one thing to cut back the CPU cache. It is quite another to deliberate slow things down. IBM's current knee-capping approach is far superior to the old adjus

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread Anne & Lynn Wheeler
The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well. eamacn...@yahoo.ca (Ted MacNEIL) writes: > Why? If you don't need the capacity, what's the issue? > Would you rather pay full hardware & software costs for capacity

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread Tom Marchant
On Fri, 5 Mar 2010 11:02:22 -0500, George Henke wrote: >This is simply incredible, to think that IBM would deliberately run BCT >loops to throttle, slowdown, CPs. Check the archives for discussions of kneecapped processors. This has been covered many times. >It is one thing to cut back the CPU c

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread Mark Zelden
On Fri, 5 Mar 2010 11:18:08 -0500, zMan wrote: >On Fri, Mar 5, 2010 at 11:02 AM, George Henke wrote: > >> This is simply incredible, to think that IBM would deliberately run BCT >> loops to throttle, slowdown, CPs. >> >> It is one thing to cut back the CPU cache. It is quite another to >> delib

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread Ted MacNEIL
>This is simply incredible, to think that IBM would deliberately run BCT loops >to throttle, slowdown, CPs. Why? This kind of thing has been around nearly as long as commercial computing. I remember when upgrades consisted of removing circuitry that slowed the processor down. The AMD470 had bui

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread Anne & Lynn Wheeler
The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well. gahe...@gmail.com (George Henke) writes: > The current trend towards CMMI and the Six Sigma standard of quality, 6 > standard deviations (3.4 defects in a million)

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread zMan
On Fri, Mar 5, 2010 at 11:02 AM, George Henke wrote: > This is simply incredible, to think that IBM would deliberately run BCT > loops to throttle, slowdown, CPs. > > It is one thing to cut back the CPU cache. It is quite another to > deliberate slow things down. > I thought this debate ended w

Re: z9 / z10 instruction speed(s)

2010-03-05 Thread George Henke
This is simply incredible, to think that IBM would deliberately run BCT loops to throttle, slowdown, CPs. It is one thing to cut back the CPU cache. It is quite another to deliberate slow things down. When will they ever learn that quality sells more than anything else and that making anything l

Re: z9 / z10 instruction speed(s)

2010-03-03 Thread Edward Jaffe
McKown, John wrote: There are multiple z9 "models". Each model has its own MSU rating, which is basically related to the number of CPs enabled and their "speed". Now, I know that all the CPs on all z9 run same hardware speed. So, I'm wondering how they are "knee capped"? Now, I know that the "k

Re: z9 / z10 instruction speed(s)

2010-03-02 Thread Tony Harminc
On 2 March 2010 16:59, McKown, John wrote: > There are multiple z9 "models". Each model has its own MSU rating, which is > basically related to the number of CPs enabled and their "speed". Now, I know > that all the CPs on all z9 run same hardware speed. So, I'm wondering how > they are "knee c

Re: z9 / z10 instruction speed(s)

2010-03-02 Thread Thompson, Steve
-Original Message- From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of McKown, John Sent: Tuesday, March 02, 2010 3:59 PM To: IBM-MAIN@bama.ua.edu Subject: z9 / z10 instruction speed(s) There are multiple z9 "models". Each model has its own MSU rating

Re: z9 / z10 instruction speed(s)

2010-03-02 Thread Shane Ginnane
I was told (years ago,different hardware) that the pipeline was filled with the appropriate number of NOPs. Might have just been an engineer finding a convenient explanation for a sysprog though ... I always wondered how that worked across different workloads - with all the smarts built into the

z9 / z10 instruction speed(s)

2010-03-02 Thread McKown, John
There are multiple z9 "models". Each model has its own MSU rating, which is basically related to the number of CPs enabled and their "speed". Now, I know that all the CPs on all z9 run same hardware speed. So, I'm wondering how they are "knee capped"? Now, I know that the "knee capping" is done

Re: z9 / z10 hardware question - unused CPs

2010-02-11 Thread R.S.
Tom Marchant pisze: On Thu, 11 Feb 2010 10:00:30 -0500, zMan wrote: On Thu, Feb 11, 2010 at 9:58 AM, Tom Marchant wrote: A z10 is not 4 times faster than a z9 with the same number of engines, or even for maximum z9 compared to maximum z10. Not even close. It is closer to a 50% increase. Ch

Re: z9 / z10 hardware question - unused CPs

2010-02-11 Thread Tom Marchant
On Thu, 11 Feb 2010 10:00:30 -0500, zMan wrote: >On Thu, Feb 11, 2010 at 9:58 AM, Tom Marchant wrote: > >> A z10 is not 4 times faster than a >> z9 with the same number of engines, or even for maximum z9 compared to >> maximum z10. Not even close. It is closer to a 50% increase. Check the >> LS

Re: z9 / z10 hardware question - unused CPs

2010-02-11 Thread zMan
On Thu, Feb 11, 2010 at 9:58 AM, Tom Marchant wrote: > A z10 is not 4 times faster than a > z9 with the same number of engines, or even for maximum z9 compared to > maximum z10. Not even close. It is closer to a 50% increase. Check the > LSPR for details. > Isn't it more like 2x, "reduced" to

Re: z9 / z10 hardware question - unused CPs

2010-02-11 Thread Tom Marchant
On Wed, 10 Feb 2010 19:18:40 -0600, Trivers Software wrote: >isn't it also 4 times faster, for only 50% increase. >Wouldn't 4 times as many servers would be 400% increase in power, >so 50% versus 400% increase is a big savings. So it might actually be green? It would be helpful if you'd quote a

Re: z9 / z10 hardware question - unused CPs

2010-02-10 Thread Trivers Software
isn't it also 4 times faster, for only 50% increase. Wouldn't 4 times as many servers would be 400% increase in power, so 50% versus 400% increase is a big savings. So it might actually be green? -- For IBM-MAIN subscribe / sign

Re: z9 / z10 hardware question - unused CPs

2010-02-09 Thread Timothy Sipples
I should have said "...in normal operations." - - - - - Timothy Sipples IBM Consulting Enterprise Software Architect Based in Tokyo, Serving IBM Japan / Asia-Pacific E-Mail: timothy.sipp...@us.ibm.com -- For IBM-MAIN subscribe /

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread Paul Gilmartin
On Mon, 8 Feb 2010 16:03:56 +0100, Vernooij, CP - SPLXM wrote: > >No, based in the internal activity. The modern version of the 360, so >you can again see what's going on inside, more or less. > Gee! A mood ring for your computer. Hang it in front of the blower exhaust. -- gil -

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread Paul Gilmartin
On Mon, 8 Feb 2010 14:21:28 +0100, R.S. wrote: >>> >> So, no power reduction when a processor is in a wait state? > >I don't know. I suspect no. In PC program hang usually means 100% CPU >utilization. BTW: Power consuption depends on type of instruction >performed. I was told that it was analyzed b

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread McKown, John
> -Original Message- > From: IBM Mainframe Discussion List > [mailto:ibm-m...@bama.ua.edu] On Behalf Of Vernooij, CP - SPLXM > Sent: Monday, February 08, 2010 9:04 AM > To: IBM-MAIN@bama.ua.edu > Subject: Re: z9 / z10 hardware question - unused CPs > No, based in

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread zMan
On Mon, Feb 8, 2010 at 10:03 AM, Vernooij, CP - SPLXM wrote: > > No, based in the internal activity. The modern version of the 360, so > you can again see what's going on inside, more or less. > That would be way cool! But I'm betting on green -- maybe 2 stripes. Or 11. -

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread Pommier, Rex R.
d have put in a sealed water tube behind the purple stripe and ran a bubbler through it, like an old-time jukebox! Rex -Original Message- From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of Chase, John Sent: Monday, February 08, 2010 7:07 AM To: IBM-MAIN@bama.ua.edu

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread Steve Comstock
Vernooij, CP - SPLXM wrote: "McKown, John" wrote in message news:. .. -Original Message- From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of zMan Sent: Sunday, February 07, 2010 10:49 AM To: IBM-MAIN@bama.ua.edu Subject: Re: z9 / z10 hardwar

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread Vernooij, CP - SPLXM
"McKown, John" wrote in message news:. .. > > -Original Message- > > From: IBM Mainframe Discussion List > > [mailto:ibm-m...@bama.ua.edu] On Behalf Of zMan > > Sent: Sunday, February 07, 2010 10:49 AM > > To: IBM-MAIN@bama.ua.edu > > Su

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread McKown, John
> -Original Message- > From: IBM Mainframe Discussion List > [mailto:ibm-m...@bama.ua.edu] On Behalf Of zMan > Sent: Sunday, February 07, 2010 10:49 AM > To: IBM-MAIN@bama.ua.edu > Subject: Re: z9 / z10 hardware question - unused CPs > > On Sun, Feb 7, 2010 a

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread Staller, Allan
Compare the total power consumption of a z/10 to the consumption of the server farm (potentially 1000's of squatty boxes) it can replace. This is why it can be considered a "green machine". An example would be "green z10" - I wouldn't really care about power consumption unless I heard opinions "o

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread Mark Zelden
On Mon, 8 Feb 2010 09:09:20 +0100, R.S. wrote: >Timothy Sipples pisze: >[...] >> Also, I'm quite sure that there's presently no cycle steering or other >> clock speed tricks to adjust power consumption dynamically, at least on the >> z cores. Considering the role mainframes play (running at high

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread R.S.
Paul Gilmartin pisze: On Mon, 8 Feb 2010 09:09:20 +0100, R.S. wrote: Timothy Sipples pisze: [...] Also, I'm quite sure that there's presently no cycle steering or other clock speed tricks to adjust power consumption dynamically, at least on the z cores. Considering the role mainframes play (ru

Re: z9 / z10 hardware question - unused CPs

2010-02-08 Thread Paul Gilmartin
On Mon, 8 Feb 2010 09:09:20 +0100, R.S. wrote: >Timothy Sipples pisze: >[...] >> Also, I'm quite sure that there's presently no cycle steering or other >> clock speed tricks to adjust power consumption dynamically, at least on the >> z cores. Considering the role mainframes play (running at high u

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