Re: [ARTIQ] FW: initial specification of the project

Great! Sounds like a plan. Tom From: Slichter, Daniel H. (Fed) [daniel.slich...@nist.gov] Sent: 12 April 2016 16:40 To: Thomas Harty; artiq@lists.m-labs.hk Subject: RE: FW: initial specification of the project Hi Tom, Responses inline below! Agreed that we are

Re: [ARTIQ] FW: initial specification of the project

Hi Tom, Responses inline below! Agreed that we are pretty much on the same page regarding our end goals, and I am flexible in how they are achieved (backplane clocks would be great!) as long as we aren't sacrificing performance in a substantial way. Cheers, Daniel It looks like we agree that

Re: [ARTIQ] FW: initial specification of the project

y Cc: Slichter, Daniel H. (Fed); artiq@lists.m-labs.hk <mailto:artiq@lists.m-labs.hk> Subject: Re: [ARTIQ] FW: initial specification of the project Hi tl;dr: distributing a reference clock at something like 10MHz-100MHz over the backplane, and generating the required DAC/upconverter cl

Re: [ARTIQ] FW: initial specification of the project

.pl> Cc: Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov>; artiq@lists.m-labs.hk Subject: RE: [ARTIQ] FW: initial specification of the project Greg, In case of backplane, there is available WR-compatible version that I mentioned in the datasheet I atached. It has all the cloc

Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 12 April 2016 1:55:45 AM HKT Slichter, Daniel H. (Fed) wrote: > On the DSP/"Sayma" boards, a hard SoC could have use for reducing the time > it takes to perform feedback calculations (e.g. shifts of output signal > frequency based on ADC readings). Can't this be done on the Metlino

Re: [ARTIQ] FW: initial specification of the project

> On Saturday, 9 April 2016 6:10:36 PM HKT Grzegorz Kasprowicz wrote: > > Why do you think that CPUs have negative value? You don't have to use > > them at all. > > I already explained that the MPSoC has to be dealt with and cannot be > completely ignored. If we have two SDRAM systems, maybe we

Re: [ARTIQ] FW: initial specification of the project

> > Why do you think that CPUs have negative value? You don't have to use > them > > at all. > > I already explained that the MPSoC has to be dealt with and cannot be > completely ignored. If we have two SDRAM systems, maybe we can to a > reasonable > extent, but then it does complicate the board.

Re: [ARTIQ] FW: initial specification of the project

On Saturday, 9 April 2016 6:10:36 PM HKT Grzegorz Kasprowicz wrote: > Why do you think that CPUs have negative value? You don't have to use them > at all. I already explained that the MPSoC has to be dealt with and cannot be completely ignored. If we have two SDRAM systems, maybe we can to a

Re: [ARTIQ] FW: initial specification of the project

.com [mailto:kaspr...@gmail.com] On Behalf Of Grzegorz Kasprowicz Sent: 08 April 2016 11:34 To: Thomas Harty Cc: Slichter, Daniel H. (Fed); artiq@lists.m-labs.hk Subject: Re: [ARTIQ] FW: initial specification of the project Hi tl;dr: distributing a reference clock at something like 10MHz-100MHz o

Re: [ARTIQ] FW: initial specification of the project

...@elka.pw.edu.pl] Sent: Friday, April 08, 2016 2:00 PM To: 'Sébastien Bourdeauducq' <s...@m-labs.hk> Cc: 'Grzegorz Kasprowicz' <kaspr...@gmail.com>; 'Slichter, Daniel H. (Fed)' <daniel.slich...@nist.gov>; artiq@lists.m-labs.hk Subject: RE: [ARTIQ] FW: initial specification of the project

Re: [ARTIQ] FW: initial specification of the project

Anyway, we have already plenty of things to do so I'd relay on existing backplane at the moment:) On 8 April 2016 at 12:51, Grzegorz Kasprowicz wrote: > Well, I don't have such template so all must be done from scratch. > It's really big piece of PCB, we need at least 6..8

Re: [ARTIQ] FW: initial specification of the project

On Friday, 8 April 2016 12:37:02 PM HKT Grzegorz Kasprowicz wrote: > Modification of the backplane is quite difficult and expensive. If we have a minimalistic backplane with just power, maybe IPMI, 4x differential pairs between MCH and each AMCs, and clock - why is that particularly expensive?

Re: [ARTIQ] FW: initial specification of the project

Modification of the backplane is quite difficult and expensive. You have to have really good reason and money to pay to NAT, ELMA or other company. But the good news is that together with NAT we are working on AMC backplane optimized for timing distribution. So additional layers of PCB are

Re: [ARTIQ] FW: initial specification of the project

On Friday, 8 April 2016 11:53:25 AM HKT Grzegorz Kasprowicz wrote: > Btw, > ZU11 FPGA costs more or less the same as 7K325 and offers almost twice more > logic resources. The price of ZU11 is $1,376.00 at 100pcs. > Since we will buy such quantity for our CBM project (Fair facility in GSI), > we

Re: [ARTIQ] FW: initial specification of the project

hk] > Sent: Wednesday, March 30, 2016 1:50 PM > To: Grzegorz Kasprowicz <kaspr...@gmail.com> > Cc: 'Slichter, Daniel H. (Fed)' <daniel.slich...@nist.gov>; 'Grzegorz > Kasprowicz' <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk > Subject: Re: [ARTIQ] FW: initial spe

Re: [ARTIQ] FW: initial specification of the project

Correction in point 2: The distributor I meant was HMC6832, not HMC830 and I meant to say "will degrade the Wenzel oscillator's phase noise somewhat at higher frequencies" (not "considerably")... T From: Thomas Harty Sent: 04 April 2016 18:38 To: Slichter,

Re: [ARTIQ] FW: initial specification of the project

Daniel, thanks for the feedback. "A few" comments in response: tl;dr: distributing a reference clock at something like 10MHz-100MHz over the backplane, and generating the required DAC/upconverter clocks locally using VCOs seems to be by far the nicest, most scalable and flexible solution. There

Re: [ARTIQ] FW: initial specification of the project

On Friday, 1 April 2016 5:25:19 PM HKT Thomas Harty wrote: > d) Something else I'm missing? Low-frequency jitter of the PLL? ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] FW: initial specification of the project

Agreed, clock phase noise is _very_ important, and backplane crosstalk will be a killer if clocks are distributed without due care. Having said that, I'm not convinced that clock distribution via the backplane isn't the right way to go if done properly -- even for the most demanding

Re: [ARTIQ] FW: initial specification of the project

Re DAC clock: presumably, the plan is to distribute a 10MHz (or 100MHz, or whatever) clock with really low close-in phase noise to each MCH, and then from each MCH to the AMCs via the backplane. Why not send this from the AMC to the FMC boards via the FMC connectors? Then, have the FMC board

Re: [ARTIQ] FW: initial specification of the project

< > gkasp...@elka.pw.edu.pl>; Leibrandt, David R. (Fed) < > david.leibra...@nist.gov>; Sébastien Bourdeauducq <s...@m-labs.hk>; > artiq@lists.m-labs.hk > *Subject:* Re: [ARTIQ] FW: initial specification of the project > > > > Here is example of CERN carrier with a

Re: [ARTIQ] FW: initial specification of the project

On 31 March 2016 at 04:58, Sébastien Bourdeauducq wrote: > On Wednesday, 30 March 2016 9:37:51 PM HKT Grzegorz Kasprowicz wrote: > > Well, you don't have to write it. > > It is already available for RTOS and linux. > > We are not using RTOS or Linux. > you can also program it

Re: [ARTIQ] FW: initial specification of the project

On Wednesday, 30 March 2016 9:37:51 PM HKT Grzegorz Kasprowicz wrote: > Well, you don't have to write it. > It is already available for RTOS and linux. We are not using RTOS or Linux. > But it's true - it occupies MIO bank and dedicated DDR port. But this is axi > and can be easily accessible

Re: [ARTIQ] FW: initial specification of the project

ien Bourdeauducq <s...@m-labs.hk>; artiq@lists.m-labs.hk Subject: Re: [ARTIQ] FW: initial specification of the project Here is example of CERN carrier with analogue voltages: http://www.ohwr.org/projects/fmc-pci-carrier/wiki "+5V, -2V, -5V2 and -12V optionally wired on HPC pins"

Re: [ARTIQ] FW: initial specification of the project

.@elka.pw.edu.pl>>; Leibrandt, David R. (Fed) <david.leibra...@nist.gov<mailto:david.leibra...@nist.gov>>; Sébastien Bourdeauducq <s...@m-labs.hk<mailto:s...@m-labs.hk>>; artiq@lists.m-labs.hk<mailto:artiq@lists.m-labs.hk> Subject: Re: [ARTIQ] FW: initi

Re: [ARTIQ] FW: initial specification of the project

;; Leibrandt, David R. (Fed) <david.leibra...@nist.gov>; Sébastien Bourdeauducq <s...@m-labs.hk>; artiq@lists.m-labs.hk Subject: Re: [ARTIQ] FW: initial specification of the project Well, it depends on trace width matching. We can simulate and characterize it even at much higher frequ

Re: [ARTIQ] FW: initial specification of the project

:* Wednesday, March 30, 2016 3:13 PM > *To:* Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov> > *Cc:* Robert Jördens <r...@m-labs.hk>; Grzegorz Kasprowicz < > gkasp...@elka.pw.edu.pl>; Leibrandt, David R. (Fed) < > david.leibra...@nist.gov>; Sébastien

Re: [ARTIQ] FW: initial specification of the project

...@gmail.com] Sent: Wednesday, March 30, 2016 2:41 PM To: Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov> Cc: Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl>; Leibrandt, David R. (Fed) <david.leibra...@nist.gov>; Sébastien Bourdeauducq <s...@m-labs.hk>; artiq@lists.m-labs.hk

Re: [ARTIQ] FW: initial specification of the project

Actually HPC with LPC IO assignment and 8 x GTP links is popular configuration So you have 34 LVDS pairs and 8 GTP links. If this works for you then I don’t have major objections. The other issue to consider is power rails, since for the analog circuitry we will probably want +/- 5V, +/- 15V

Re: [ARTIQ] FW: initial specification of the project

com] > *Sent:* Wednesday, March 30, 2016 2:44 PM > *To:* Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov> > *Cc:* Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl>; Leibrandt, David R. > (Fed) <david.leibra...@nist.gov>; Sébastien Bourdeauducq <s...@m-labs.hk>;

Re: [ARTIQ] FW: initial specification of the project

Actually HPC with LPC IO assignment and 8 x GTP links is popular configuration So you have 34 LVDS pairs and 8 GTP links. On 30 March 2016 at 23:00, Slichter, Daniel H. (Fed) < daniel.slich...@nist.gov> wrote: > > On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed) > >

Re: [ARTIQ] FW: initial specification of the project

> On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed) > wrote: > > Now, as you suggest we could just change the level at which we make this > break from the AMC card, shift the DACs and ADCs onto the daughter card as > well, and use FMC to communicate with the

Re: [ARTIQ] FW: initial specification of the project

Such assembly technique is called: castellated PCB module https://www.google.pl/search?q=castellated+RF+modules=1920=917=lnms=isch=X=0ahUKEwjRvuqko-nLAhWnnXIKHe_IARsQ_AUIBygB

Re: [ARTIQ] FW: initial specification of the project

On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed) wrote: > Now, as you suggest we could just change the level at which we make this > break from the AMC card, shift the DACs and ADCs onto the daughter card as > well, and use FMC to communicate with the whole

Re: [ARTIQ] FW: initial specification of the project

Well, we can do another crazy thing - solder small module with RF stuff on the FMC board, under same shield. In this way we keep 3 simple FMCs with expensive ADCs/DACs and define the functionality by soldering (automatic or manual) of just RF modules. WE can even design such modules to hold the

Re: [ARTIQ] FW: initial specification of the project

> Maybe we should come back to the roots:) What if we use standard FMCs > (LPC) with DAC/ADC channels and RF stuff _on_ them. > JESD204B and some pins would go to the FPGA while DAC and RF clock would > be fed externally. > In this way we leave general purpose AMC board and define its

Re: [ARTIQ] FW: initial specification of the project

ucq <s...@m-labs.hk>; Grzegorz Kasprowicz <kaspr...@gmail.com> Cc: 'Grzegorz Kasprowicz' <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk Subject: RE: [ARTIQ] FW: initial specification of the project > I like this plan. I think 4 + 4 channels will also make the front >

Re: [ARTIQ] FW: initial specification of the project

rowicz <kaspr...@gmail.com>; 'Grzegorz Kasprowicz' <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk; Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov> Subject: Re: [ARTIQ] FW: initial specification of the project On Wednesday, 30 March 2016 3:15:59 PM HKT Leibrandt, David R. (Fe

Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote: > [GK] If you don't use ARM, you still get hardened SDRAM controller and > GBE MACs. Yes, that's what I was saying: you cannot get rid of them (i.e. use their pins like other IOs). So you need to use the Zynq-specific

Re: [ARTIQ] FW: initial specification of the project

, March 30, 2016 1:50 PM To: Grzegorz Kasprowicz <kaspr...@gmail.com> Cc: 'Slichter, Daniel H. (Fed)' <daniel.slich...@nist.gov>; 'Grzegorz Kasprowicz' <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk Subject: Re: [ARTIQ] FW: initial specification of the project On Tuesday, 29 March 20

Re: [ARTIQ] FW: initial specification of the project

On Wed, Mar 30, 2016 at 5:57 PM, Slichter, Daniel H. (Fed) wrote: >> > What are you thinking for number of daughter cards? I suppose that >> > more would give us more flexibility, but less would be more economical >> > in terms of cost and layout area. Perhaps two

Re: [ARTIQ] FW: initial specification of the project

> > What are you thinking for number of daughter cards? I suppose that > > more would give us more flexibility, but less would be more economical > > in terms of cost and layout area. Perhaps two daughter cards would be > reasonable: > > one for all of the inputs and one for all of the outputs?

Re: [ARTIQ] FW: initial specification of the project

> I like this plan. I think 4 + 4 channels will also make the front panel > connector > density more reasonable. What are you thinking for number of daughter > cards? I suppose that more would give us more flexibility, but less would be > more economical in terms of cost and layout area.

Re: [ARTIQ] FW: initial specification of the project

spr...@gmail.com> Cc: 'Grzegorz Kasprowicz' <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk; Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov> Subject: Re: [ARTIQ] FW: initial specification of the project On Tuesday, 29 March 2016 11:55:19 PM HKT Grzegorz Kasprowicz wrote: &g

Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote: > [GK] If you don't use ARM, you still get hardened SDRAM controller and GBE > MACs. Yes, that's what I was saying: you cannot get rid of them (i.e. use their pins like other IOs). So you need to use the Zynq-specific features

Re: [ARTIQ] FW: initial specification of the project

On Friday, 25 March 2016 12:24:02 PM HKT you wrote: > * whether or not we use Zynq remains to be decided. > **The price difference is not that high (a few tens of $) and we get > plenty of CPU power Yes, but Zynq chips are annoying to program (even if we do not use the ARM cores) and more

Re: [ARTIQ] FW: initial specification of the project

: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Slichter, Daniel H. (Fed) Sent: Monday, March 28, 2016 5:25 PM To: Sébastien Bourdeauducq <s...@m-labs.hk> Cc: Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk Subject: Re: [ARTIQ] FW: initial specification of

Re: [ARTIQ] FW: initial specification of the project

ka.pw.edu.pl>; artiq@lists.m-labs.hk > Subject: Re: [ARTIQ] FW: initial specification of the project > > Let me make clear that I don't have any specific opposition to FMC for the > power/digital signals. The only reason for considering other types of > connectors would

Re: [ARTIQ] FW: initial specification of the project

ducq <s...@m-labs.hk>; Grzegorz Kasprowicz > <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk > Subject: Re: [ARTIQ] FW: initial specification of the project > > On Tue, Mar 29, 2016 at 5:16 PM, Slichter, Daniel H. (Fed) > <daniel.slich...@nist.gov> wrote: > >

Re: [ARTIQ] FW: initial specification of the project

> > OK. Then mixing SMP with something else is fine IMO. > > The other connector can well be FMC. We need at least ~40 signals other > than the analog ones going to the cards. A bunch of different power supplies, > SPI control lines, identification buses, switching, attenuation settings etc.

Re: [ARTIQ] FW: initial specification of the project

> If 65 dB between neighboring channels is the requirement, then > comprehensive board level shielding appears to be required. Yes, this will be necessary. See my previous emails. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] FW: initial specification of the project

On Tue, Mar 29, 2016 at 11:56 AM, Sébastien Bourdeauducq wrote: > On Monday, 28 March 2016 6:30:52 PM HKT Slichter, Daniel H. (Fed) wrote: >> Thus for the two examples above, using digital connectors with a 9 mm or 11 >> mm total stackup height would give 250 um axial misalignment

Re: [ARTIQ] FW: initial specification of the project

On Mon, Mar 28, 2016 at 9:14 PM, Slichter, Daniel H. (Fed) wrote: > http://suddendocs.samtec.com/testreports/hsc-report-seam-seaf-07mm_web.pdf > > There is too much crosstalk in FMC connectors (~40-65 dB typical @ 3 GHz) for > us to use them for the RF/analog

Re: [ARTIQ] FW: initial specification of the project

On Saturday, 26 March 2016 4:06:17 PM HKT Slichter, Daniel H. (Fed) wrote: > The cost savings from using FMC, which might amount to $50 per AMC, are not > worth if the crosstalk will make the cards not useful for researchers. It's not only about cost of the connector - the RF daughter cards