Re: [casper] Anyone have an asynchronous VACC?

Well that's convenient! Thanks Andrew. On Tue, Jun 20, 2023 at 2:43 PM Andrew Martens wrote: > Hey MoragSARAO has one (used in MeerKAT X-engines) that might be > useful.CheersAndrewOn Tue, 20 Jun 2023, 14:37 Morag Brown, < > mbr...@sarao.ac.za> wrote:Hey all,As the subject says. We might need

Re: [casper] Anyone have an asynchronous VACC?

Hey Morag SARAO has one (used in MeerKAT X-engines) that might be useful. Cheers Andrew On Tue, 20 Jun 2023, 14:37 Morag Brown, wrote: > Hey all,As the subject says. We might need an async vacc for a project, so > checking if anyone here already has one working with the toolflow in the >

[casper] Anyone have an asynchronous VACC?

Hey all, As the subject says. We might need an async vacc for a project, so checking if anyone here already has one working with the toolflow in the hopes of saving myself some frustration. Would be eternally grateful. Morag Disclaimer The information contained in this communication from the

Re: [casper] Doubts about clocking in RFSOC4x2

Hi Ross,Thanks for sharing this information. I would be very keen to help out with porting this tool you have to RFSoC 4x2. It sounds awesome.I’ll reach out to you in a separate email. MitchOn Jun 14, 2023, at 4:55 PM, 'Ross Martin' via casper@lists.berkeley.edu wrote:Hi Sebastian,I have an app

Re: [casper] Doubts about clocking in RFSOC4x2

Hi Sebastian, I have an app that I'd like to port to the RFSoC4x2 that might help -- when I can get some help porting it. It currently works on several boards including the ZCU208, which has the same clock chips as the RFSoC4x2. The app allows you to set the ADC clocks to almost any desirable

[casper] Doubts about clocking in RFSOC4x2

Hi, I want to change the sampling rate of the ADCs programing the LMX and LMK but I have some doubts about how the clocking scheme is done. The clocking diagram in the RFSoC4x2 reference manual shows that the LMK has one output of 122.88MHz that goes to the pin AN11, another clock of 245.76

Re: [casper] Error in Matlab running startsg

Hi Ben, I just took a look and this seems to an issue with the model. - Some of test models in that folder appear to be out of date, and this particular test file used a custom bit of code to test the crc of the packet that looks like it was not checked in along with the model, so the model can't

Re: [casper] Error in Matlab running startsg

Hi Jonathon, hi all,Thank you - this did the trick! Simulink looks normal now and I can get into the model without errors. However, when updating the test_snap.slx model (just to check that things are indeed working alright), I now encounter a new error (or rather, set of similar errors)

Re: [casper] Error in Matlab running startsg

Forgot to mention that these instructions were a bit RFSoC specific... Cheers, Kaj On Fri, 9 Jun 2023 at 23:36, Kaj Wiik wrote: > Hi Ben, > > Here are my install notes and snippets copied from the web: > https://gitlab.utu.fi/kjwiik/casper-installation/-/blob/main/README.md > > In fact, I

Re: [casper] Error in Matlab running startsg

Hi Ben, Here are my install notes and snippets copied from the web: https://gitlab.utu.fi/kjwiik/casper-installation/-/blob/main/README.md In fact, I found that Ubuntu 18.04 works a bit better, e.g. the CASPER tools in the Simulink menu does not appear in 20.04. Hope this helps, Kaj On Fri, 9

Re: [casper] Error in Matlab running startsg

Hi Ben, You may have already, but there are a couple of other places to move libgmp that might be worth trying: (From this issue: https://github.com/casper-astro/mlib_devel/issues/190) cd /opt/Xilinx/Model_Composer/2021.1/lib/lnx64.o/Ubuntu mkdir exclude mv libgmp.so* exclude/ cd

[casper] Error in Matlab running startsg

Hi all,I have been trying to set up the Toolflow quite closely following the setup guide (using the recommended versions: a completely fresh Ubuntu 20.04 install, Vivado 2021.1, mlib_devel m2021a). I get to the point under "Running the toolflow" but when I run the startsg script while

Re: [casper] tut_rfdc on RFSoC4x2

Thank you all for your answers. .dtbo generation is good now. No luck yet with the ADC, but we will work on it. Cheers, Cedric and Nhung Le 08/06/2023 à 17:14, Jonathon Kocz a écrit : Hi Cedric and Nhung, A couple of things to check: 1) Have you updated the startsg.local file with the

Re: [casper] tut_rfdc on RFSoC4x2

Also potentially confusing for us new users is that the example rfsoc starts file < https://github.com/casper-astro/tutorials_devel/blob/main/rfsoc/startsg.local.example> incorrectly sets JASPER_BACKEND=vivado Jason On Fri, Jun 9, 2023 at 7:04 AM Jason Gallicchio wrote: > I too was stuck on

Re: [casper] tut_rfdc on RFSoC4x2

I too was stuck on this for at least a day. I had JASPER_BACKEND=vivado from the previous tutorial or from < https://casper-toolflow.readthedocs.io/en/latest/src/Configuring-the-Toolflow.html> and the rfsoc getting started tutorial doesn't really call attention to this change. Even just a comment

Re: [casper] tut_rfdc on RFSoC4x2

Hi Cedric and Nhung, A couple of things to check: 1) Have you updated the startsg.local file with the paths for creating the .dtbo files? You'll need to set the JASPER_BACKEND to vitis also (e.g): JASPER_BACKEND=vitisXLNX_DT_REPO_PATH=/sandbox/xilinx/device-tree-xlnx The dtbo file will not

[casper] tut_rfdc on RFSoC4x2

Hi! We are starting to use ADCs with our RFSoC4x2 and we encounter 2 related (?) problems. First, the tutorials says that we should pay attention to the generation of a .dtbo by Vivado. We can't find it after building the tutorials (and not in the jasper/vivado logs). That was ok for

Re: [casper] How to monitor the 100Gbe port on a RFSoC 4x2 ?

Ken, I understand a bit better what you are after now. Some more information inline below. Best, Mitch On Jun 7, 2023, at 1:43 PM, Ken Semanov wrote: Dear Mitchell Burnett, Thank you for the help with this matter. The manufacturer of the optical transceiver is likely confused as to the

Re: [casper] How to monitor the 100Gbe port on a RFSoC 4x2 ?

Dear Mitchell Burnett, Thank you for the help with this matter. The manufacturer of the optical transceiver is likely confused as to the nature of the RFSoC 4x2, justifiably. To make some progress with them, I would need a kind of utility for the 100Gbe port. Something which reads raw

Re: [casper] Re: Sync ADC16 in ROACH2

Hi Wang, This is strange and concerning (the ROACH2 branch of mlib_devel should be the reliable one!) but glad you found a fix (and thanks for posting a link to the repo that worked for you) Cheers Jack On Wed, 7 Jun 2023 at 10:32, Wang wrote: > Hi everyone, > > I solved this problem by using

[casper] Re: Sync ADC16 in ROACH2

Hi everyone, I solved this problem by using an older version of mlib_devel. Files · edbc38236f2a756e169b74a7bad0d76263c0f91a · ALPACA / CASPER / mlib_devel · GitLab (byu.edu) [observer@cylctrl

Re: [casper] How to monitor the 100Gbe port on a RFSoC 4x2 ?

Ken, The 100 GbE ethernet is not a processing system attached core in the typical sense like your NIC on your servers. These are connected directly to the fabric of the FPGA and are polled using their memory map register. The 100 GbE is covered in tutorial 4 for the RFSoC tutorials. More is

[casper] How to monitor the 100Gbe port on a RFSoC 4x2 ?

board = Zynq UltraScale+ RFSoC4x2board (Gen 3 ZU48DR) I am in contact with a manufacturer of 100Gbe optical transceivers. For troubleshooting, they want to see connection logs and alarms for the 100Gbe port. I am sending data from the 100Gbe ethernet leaving the 4x2 on IP 10.17.16.20. (I am

Re: [casper] Designing blocks in Simulink or Vivado to interop with an external PPS?

Mitch, These look very good. Thank you.  On Tuesday, June 6, 2023 at 5:19:12 PM UTC-4 Mitch Burnett wrote: > Hi Ken, > > Kindly go through the second RFSoC CASPER tutorial showing how to use the > casperfpga programming utility for scripted command and control of the > rfsoc4x2 platform.

Re: [casper] Designing blocks in Simulink or Vivado to interop with an external PPS?

Hi Ken, Kindly go through the second RFSoC CASPER tutorial showing how to use the casperfpga programming utility for scripted command and control of the rfsoc4x2 platform. The relevant commands using casperfpga are upload_clk_file() and prgpll(). That section of the tutorial starts here:

Re: [casper] Designing blocks in Simulink or Vivado to interop with an external PPS?

Dear Mitch Burnett, Thank you for the prompt response. I have read elsewhere that external software is needed to program the Texas Instruments LMK04828. In particular, the software is run at board startup, and is used to change the input clock source, or modify the LMK's output frequencies,

Re: [casper] Designing blocks in Simulink or Vivado to interop with an external PPS?

Hi Ken, There are not any good examples in the CASPER Tutorials yet for how to configure this, however the capability is there. In CASPER tools the signals out of the comparator/ADS7885S/etc. in that diagram and into the FPGA fabric are accessed via a GPIO yellow block using the name given to

Re: [casper] RFSoC 4x2 10 MHz Ext. Ref. Clk?

Hi Jason, Yes you can use a 10 MHz ext. ref. clk with LMK on RFSoC 4x2. Yes, the LMK will need to explicitly load another configuration. There are methods in casperfpga to upload new exported register files from TICS and to program the LMK ( upload_clk_file(), progpll() ). Attached is a zip

[casper] Re: RFSoC2x2 board USB not recognized on Ubuntu. No Serial connection through USB. (CASPER toolflow)

This has been solved. The serial connection is available through the Micro USB port, not the Micro USB 3.0 port. On Saturday, May 13, 2023 at 4:11:59 PM UTC-4 Ken Semanov wrote: > *RFSoC 2x2 kit University , Xilinx ZYNQ UltraScale+ RFSoC ZU28DR FPGA* model > no. HTG-ZRF2-XUP > > board boot

[casper] Sync ADC16 in ROACH2

Hi everyone, When I validated my design on ROACH2, I found that there were some issues with the synchronization of the adc chip. The environment I used was ubuntu14 ise14.7 matlab2013b mlib_devel-roach2. The parameter of my XSG_core_config module is set to ROACH2:sx475t adc0_clk 200MHz. I

[casper] RFSoC 4x2 10 MHz Ext. Ref. Clk?

I'd love to use a 10 MHz GPS disciplined oscillator to make a 10 MHz RF SYS REFCLK or SYSREF, along with a nice round sampling rate. With the LMK, is it possible to use a 10 MHz Ext. Ref. Clk if it's plugged in, and the 160MHz VCXO OSC IN otherwise? Or do you need to explicitly load one or the

[casper] Designing blocks in Simulink or Vivado to interop with an external PPS?

*board = Zynq UltraScale+ RFSoC4x2board (Gen 3 ZU48DR)* *.* [image: smlexternal_PPS.png] The above shows an external PPS driving an ADC that is SPI's into the XCZU48DR. In what manner would the FPGA fabric access these pins in a design? Should the PLLs be programmed externally to align with

Re: [casper] SNAP Tutorial 3

Does anybody have a snap_tut_spec.fpg built with mlib_devel branch m2021a that works with casperfpga branch py38-dev, and passes the rampTest calibration procedure? I'm still having issues. If I use the older branch py38, and the example .fpg file included in tutorials_devel at

Re: [casper] RFSoC4x2 tut_rfdc and tut_spec building only without filename changes

I had the same issue and found that when copying the block or changing the name of the slx doesnt update the internal names (I faced the same problem in some old ROACH models). What I found to work is to open the dialog of the block, modify a parameter and apply the changes, then return the

Re: [casper] RFSoC4x2 tut_rfdc and tut_spec building only without filename changes

Yes, this seems to be the problem. If by "look underneath the RFDC yellow block," you mean go into the BLOCK toolbar and click Expand. The gateways that are revealed do include the name of the original file, not the renamed file. Creating a new RFDC block and Expanding it does give the gateways

Re: [casper] RFSoC4x2 tut_rfdc and tut_spec building only without filename changes

Hi Jason, If you look underneath the RFDC yellow block, the gateways should have names which include a prefix which is the model name + RFDC block name. Are these correct in your broken models, or do they reflect a previous model name? If they are wrong, does creating a new RFDC block and

[casper] RFSoC4x2 tut_rfdc and tut_spec building only without filename changes

I can run jasper to build rfsoc4x2_tut_rfdc_real.slx and rfsoc4x2_tut_spec.slx

Re: [casper] Question on Casperfpga python 3.8 version

Dear June, I am sorry you are encountering this problem. SKARAB has only been baselined and fully tested using Python 2.7 for casperfpga. Yes, some attempts have been made to port it to Python 3.8, but as far as I am aware there have been issues that were never fully sorted out. It looks like you

[casper] Question on Casperfpga python 3.8 version

Dear all, Due to the upgrade of '*casperfpga*' library from python 2.7 to 3.8, I have tried to upgrade my software to a newer version. But still got stuck on problems that I still can't properly install and use it as I have followed the information on

Re: [casper] SNAP Tutorial 3

> > Wei Liu's code helped because it gave me the idea to call rampTest() > first. Is rampTest() the only "calibration" that Wei Liu's code is > doing? rampTest() calls alignLineClock() and alignFrameClock(). Is this all > that you mean by "calibration"? Not some fine-tuning or balancing of gains >

Re: [casper] SNAP Tutorial 3

Thanks. I figured it out enough to move on. The following initialization code works, but if I switch the order of the last two lines (rampTest and selectInput), I basically the bad pattern of near-zero values that I originally emailed about: adc = casperfpga.snapadc.SnapAdc(fpga, num_chans=1,

[casper] RFSoC2x2 board USB not recognized on Ubuntu. No Serial connection through USB. (CASPER toolflow)

*RFSoC 2x2 kit University , Xilinx ZYNQ UltraScale+ RFSoC ZU28DR FPGA* model no. HTG-ZRF2-XUP board boot image = (CASPER) rfsoc2x2_casper.img Ubuntu 20.04 LTS , Kernel 5.15.0-71-generic (long term) I need to log into this 2x2 board's internal Petalinux, so that I can configure its

Re: [casper] SNAP Tutorial 3

Jason, I think the data problem is with the ADC calibration. - And I agree, the inconsistent renames were hugely frustrating. Sorry you've hit these errors. The original SNAP calibration routine did not work with python3 and needed to be rewritten entirely. It was left in a broken state for a

[casper] position at Seattle for daq scientist

Dear Casper-ites, At the University of Washington, Seattle, we are using a new technique to measure nuclear beta decay spectra and search for hints of new physics by measuring cyclotron radiation frequencies of betas in magnetic fields of a few Tesla. The technique requires measurements in the

Re: [casper] XPORT adress

Thank you very much, Jonathon！ Cheers， Kuma 在2023年4月24日星期一 UTC+8 01:15:13 写道： > Hi Kuma, > > 1) The ROACH2 does not support XPORT (that was only for the ROACH1). - You > can find the hardware specs of both on the old wiki: > https://casper.astro.berkeley.edu/wiki/ROACH, >

Re: [casper] XPORT adress

Hi Kuma, 1) The ROACH2 does not support XPORT (that was only for the ROACH1). - You can find the hardware specs of both on the old wiki: https://casper.astro.berkeley.edu/wiki/ROACH, https://casper.astro.berkeley.edu/wiki/ROACH-2_Revision_2) 2) As (1) above. 3) The V6 Net interface is a direct

[casper] XPORT adress

Hi everyone, I'm using roachnest to monitor and manage ROACH2. I have never changed the relevant configuration of Xport. The default Xport address of ROACH2 is 192.168.4.20. I entered 192.168.4.20 in the Xport address, but the address failed to be pinged. [image: roachnest.png] I have some

Re: [casper] Unable to program bit stream from filename.bof

Hi，CASPER I know what the problem is. ~ # mount -t nfs -o nolock 192.168.25.101:/srv/roach_boot/etch/boffiles /mnt ~ # cp /mnt/roach2_fengine_led.bof /boffiles/ cp: can't create '/boffiles/roach2_MAC_wz.bof': No space left on device BW， Wang Wang 于2023年4月22日周六 11:21写道： > Hi CASPER， > I

[casper] Re: The output data of the fft_biplex_real_2x

I had trouble understanding how the fft module works before, but now I understand. Therefore, the content expressed is very messy and takes up your time. I am very sorry. 在2023年4月12日星期三 UTC+8 00:47:14 写道： > Hi CASPER, > > I've recently been designing the Corner Turner module.Converts the data

[casper] Unable to program bit stream from filename.bof

Hi CASPER， I failed to run the bof file. Here are the details: 1）I have 7 ROACH2s, 6（netboot） of which ran the bof file successfully and the seventh（soloboot） failed. 2）Seventh (failed), can run other bof files. ?progdev roach2_MAC_wz.bof #log info 1206015602753 raw

[casper] The output data of the fft_biplex_real_2x

Hi CASPER, I've recently been designing the Corner Turner module.Converts the data shape from [input channel, frequency] to [frequency, input channel]. My understanding of FFT module is not enough, especially the relationship between data and frequency points. fft_biplex_real_2x block:Fft

Re: [casper] Roach2 progremote error & CASPER slack account

Hi So that does look like an older version of tcpborphserver - if my history is correct, that version doesn't even have a ?progremote command yet, though it should have an ?upload command which does something similar. I suppose you could run ?status or ?fpgastatus to confirm that the fpga hasn't

Re: [casper] Roach2 progremote error & CASPER slack account

Hi Marc, Thanks for the rapid response. Here's the log-lvl info. Trying 192.168.4.20... Connected to 192.168.4.20. Escape character is '^]'. #version memcpy-88-g38ad77a-dirty #build-state 2013-04-11T11:50:43 ?log-level debug !log-level ok debug #log info 1133318717282 raw

Re: [casper] Roach2 progremote error & CASPER slack account

Hi Austin, Here is an invite to the CASPER slack group: https://join.slack.com/t/casper-astro/shared_invite/zt-1s7l3vt1z-1TdvVDh6Y4ZFRoimzXrUgw . Kind regards, Adam On Fri, Mar 31, 2023 at 9:28 PM Marc wrote: > On Fri, Mar 31, 2023 at 6:38 PM Austin Dymont > wrote:Hello,Hi My name is

Re: [casper] Roach2 progremote error & CASPER slack account

On Fri, Mar 31, 2023 at 6:38 PM Austin Dymont wrote: > Hello,My name is Austin Dymont, a new graduate student at the University > of Chicago. I'm in need some help regarding the setup of a ROACH2. I'm > running into an issue with programming the roach with a new .fpg file. I > followed through

[casper] Roach2 progremote error & CASPER slack account

Hello, My name is Austin Dymont, a new graduate student at the University of Chicago. I'm in need some help regarding the setup of a ROACH2. I'm running into an issue with programming the roach with a new .fpg file. I followed through with some of the intro tutorial from the

[casper] Research Computer Technology Fellow position at McGill in Canada

Dear Colleagues, The Trottier Space Institute at McGill is searching for Research Computer Technology Fellow. If signal processing / computing is your thing, consider applying. Info below. Matt *Applications are open for a postdoctoral Research Computer Technology Fellowship at the

Re: [casper] Roach monitor and management subsystem

Hi Russ， Thank you very much！ Cheer， Wang 在2023年3月23日星期四 UTC+8 12:05:17 写道： > Hi Wang, > > > I searched on Github and found roachnest.py. > > https://github.com/telegraphic/roachnest​ > > > Thanks, > > Russ​ > -- > *From:* cas...@lists.berkeley.edu on behalf > of

Re: [casper] Roach monitor and management subsystem

Hi Wang, I searched on Github and found roachnest.py. https://github.com/telegraphic/roachnest? Thanks, Russ? From: casper@lists.berkeley.edu on behalf of Wang Sent: Wednesday, March 22, 2023 11:48 PM To: casper@lists.berkeley.edu Cc: Kaj Wiik Subject:

Re: [casper] Roach monitor and management subsystem

Hi Kaj， Thank you for your reply. The information on this web page is very useful to me. However, the python scripts included do not have links or have broken links. How did you find this page? I want to find out something else I can use. Does anyone have a backup of roach_monitor.py or

[casper] Casperfpga module -- snapadc attribute

Hi, Does the current casperfpga module have casperfpga.snapadc attribute? I successfully installed casperfpga module, but it's complaining that the snapadc attribute is missing. Please advise. Thank you. cheers, Liju -- You received this message because you are subscribed to the Google Groups

Re: [casper] Roach monitor and management subsystem

Hi! I do not have experience on ROACH but found this: http://telegraphic.github.io/roachnest/ Cheers, Kaj On 22/03/2023 18:54, Wang wrote: Hi CASPER， I want to manage and monitor ROACH2 status. I found this website has what I want. Roach monitor and management subsystem - Casper

[casper] Roach monitor and management subsystem

Hi CASPER， I want to manage and monitor ROACH2 status. I found this website has what I want. Roach monitor and management subsystem - Casper (berkeley.edu) But the python code link is broken. Does anyone have a

[casper] Ubuntu 20.04 and enbr64 error (solved!)

Hi! In case others are struggling with this problem... When running a simulation in my Ubuntu 20.04 system I got "Error: no such instruction: `endbr64'". I spent a lot of time on this including making links to /usr/include without success. Then I tried !gcc /tmp/hello.c /tmp/cc2Od0Ug.s:

Re: [casper] Installing the toolchain (segfault!)

Hey everyone I have set up a VirtualBox virtual machine with the 2021 tools installed. I have been using it for the last few months and a few others have used it successfully as well. Please email me if you want a download link. It is large >250GB. You will need to add your Matlab and Xilinx

[casper] Job opportunity - CASPER / RFSoC Postdoctoral Researcher

Hello everyone, This might be relevant to some of you. Please pass it on to anyone you think might be interested. cheers, Derek. Postdoctoral researcher / Project researcher fixed-term position at the Finnish Centre for Astronomy with ESO Applications are invited for a postdoctoral

Re: [casper] Save the raw data output from the ADC

    Hello, we do that at Nançay radio telescope with instrument WIBAR: two ADC 1.1GHz, downloaded via two 10Gb fibers. This is used to iteratively test RFI reduction strategies, taking the same waveform as input. Starting five years ago, we needed several disks in RAID0, feeded in two PCs per

Re: [casper] Save the raw data output from the ADC

Dear Wang, I use ROACH 1 with iADC.  Block library's may be different. Logic you can use it by replacing the ADC block with your ADC library and 10 GBe library. Thanks and regards Indrajit On 08/03/23 1:46 pm, Wang wrote: Caution: This email originated outside IIA. Hi Indrajit, May I

Re: [casper] Save the raw data output from the ADC

Hi Indrajit, May I ask what is the environment in which you built the model? And do you have a description of the model？ The model is not complete after I opened it. Regards Wang 在2023年3月8日星期三 UTC+8 15:20:54 写道： > Hi Wang, > > > Generally, I use Burst mode (Non continues ) of RAW voltage

Re: [casper] Save the raw data output from the ADC

Hi Indrajit， Thank you very much for your sharing! The file has access permission and I have applied for it. BW！ Wang 在2023年3月8日星期三 UTC+8 15:20:54 写道： > Hi Wang, > > > Generally, I use Burst mode (Non continues ) of RAW voltage recording for > ADC testing and other testing, Herewith I shared

Re: [casper] Save the raw data output from the ADC

Hi Wang, Generally, I use Burst mode (Non continues ) of RAW voltage recording for ADC testing and other testing, Herewith I shared the design file which packs the raw voltage (iADC) into the 10 Gbe. https://drive.google.com/file/d/17766ANxnbz9Um-RdTiUrtZl5KOQAhNqq/view?usp=sharing Thanks

[casper] Save the raw data output from the ADC

Hi CASPER， I built the FX correlator using ROACH2 and GPU server. Now there is a problem, I want to save the raw data that the ADC board outputs. I don't know how to do that. Has anyone thought about this problem or has a way to save ADC output data? I would appreciate a lot if you could

[casper] CASPER Workshop 2023 - First Announcement

Dear Colleagues, We are pleased to announce that the CASPER Workshop of 2023 will be held at the University of Central Florida, with proposed dates of the 6th - 10th November. A more detailed announcement with registration and other information will follow in a few weeks. Until then, it would

Re: [casper] Installing the toolchain

Morag, Mitch, Many thanks for your replies! The problem was indeed missing ES. I was not able to add just those, I ended up reinstalling Vivado and also Matlab because after the upgrade, matlab crashed with a segfault :-D. But now everything seems to be working, I just built the ZCU216

Re: [casper] Installing the toolchain

Hi Kaj, To follow on to Mitch's mention of licensing issues, you may want to put together a simple design in Vivado itself and try run synth and implementation there - if it's a licensing issue, the Vivado log will give you more info. Or check the Vivado licence manager to make sure you have the

Re: [casper] Installing the toolchain

Kaj, When installing Vivado, at the installation configuration window there is a drop down for installing RFSoC engineering silicon parts. This needs to be selected. The default parts in the toolflow are engineering silicon (ES). Probably bad defaults now that when you buy a 216/208 or any

Re: [casper] Installing the toolchain

A quick update: I get the same error in the nrp-nautilus cloud. Any suggestions? Thanks, Kaj On 21/02/2023 17:13, Kaj Wiik wrote: Hi! As a test I made a design with only sysgen, ZCU111 and rfdc block and I got the same The S-function 'sysgen' in

Re: [casper] Installing the toolchain

Hi! As a test I made a design with only sysgen, ZCU111 and rfdc block and I got the same The S-function 'sysgen' in 'sysgen_only/rfdc/sysgen_only_rfdc_s00_axis_tdata' has specified the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for

Re: [casper] Installing the toolchain

Hi! After setting numpy<1.20 in requirements.txt and doing this (copying it here because the link was broken yesterday!): https://docs.xilinx.com/r/2021.2-English/ug1483-model-composer-sys-gen-user-guide/Supported-MATLAB-Versions-and-Operating-Systems - Prerequisites

Re: [casper] Installing the toolchain (segfault!)

Hi Kaj There is a (possibly not bleeding edge) version of the tools for use online via the Pacific Research Platform. There is a Slack channel where you can get more information at

Re: [casper] Installing the toolchain (segfault!)

Hi Andrew, On 17/02/2023 21:08, Andrew Martens wrote: For those interested - I have a virtual machine with the latest (MATLAB 2021a) tools where I have solved a lot of these issues. One just needs to add licenses for MATLAB and Xilinx. VirtualBox, and it's big (>100GB). Hit me up with a

Re: [casper] Installing the toolchain

Hi! On 17/02/2023 21:08, Andrew Martens wrote: I would also recommend our 'cloud' solution. Interesting, what's that? Cheers, Kaj -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop

Re: [casper] Installing the toolchain

For those interested - I have a virtual machine with the latest (MATLAB 2021a) tools where I have solved a lot of these issues. One just needs to add licenses for MATLAB and Xilinx. VirtualBox, and it's big (>100GB). Hit me up with a shared folder if you'd like to give it a spin. I would also

Re: [casper] Installing the toolchain

Hi! This is an old thread but as there was no confirmation of a working environment I decided to share my solution because I stubled exactly to this problem when restarting the development after a long pause (Matlab r2021a, Vivado & Vitis 2021.1, Ubuntu 20.04). There seems to be a number of

[casper] QTT Digital Backend Engineer Recruitment

Hi CASPERites, After more than ten years of preparation, the QTT (QiTai radio Telescope) project was officially launched in 2022. In order to provide scientists with the best observation instruments, QTT plan to use the most advanced signal processing technology such as RF-direct sampling,

[casper] The deadline to submit abstracts to URSI radio science meeting in Japan has been extended until 10 February

*Submission Deadline Extension URSI GASS 2023* View this email in your browser *SUBMISSION DEADLINE EXTENSION* *for Regular Paper Submission, Young Scientist

[casper] abstracts due january 25, for URSI General Assembly in Japan August 023

Dear CASPER collaborators, reminder, abstracts are due january 25: Danny Price, Andrew Van Der Byl, and I are organizing a session on "real-time processing for radio astronomy" for the International Union of Radio Science (URSI) general assembly in Sapporo, Japan, August 19-26, 2023.

[casper] Opportunity: Hosting of the CASPER 2023 Workshop

Dear Casperites, Through a combination of (happy) circumstances, the opportunity to host the 2023 CASPER workshop has become available. If you think your institution might be interested, please get in touch with the advisory board via casper-advisory-bo...@lists.berkeley.edu (cc'd), or me

Re: [casper] SSL error, can't see the wiki

the casper wiki is back, but still has a problem with https security. (matt is still trying to get a certificate from letsencrypt - it's a tricky problem...). if you are using the chrome browser to go to the wiki you'll get a message: "your connection is not private". click on "advanced", and

Re: [casper] SSL error, can't see the wiki

Hi David, Hopefully the website will be back up soon, but in case it helps, for that specific PFB link, there is a copy of the memo here: https://github.com/casper-astro/publications/blob/master/Memos/files/Casper_memo_pfb.pdf (More generally, while we don't have all the hardware info there,

Re: [casper] SSL error, can't see the wiki

Ah, been there too :-)... Take your time! Cheers, Kaj On Wed, 11 Jan 2023 at 23:26, Dan Werthimer wrote: > > sorry about this. > i think people can't get to the wiki right now because matt lebofsky is > currently working trying to renewing our https certificate from > letsencrypt. > > > > > >

Re: [casper] SSL error, can't see the wiki

sorry about this. i think people can't get to the wiki right now because matt lebofsky is currently working trying to renewing our https certificate from letsencrypt. On Wed, Jan 11, 2023 at 1:19 PM Kaj Wiik wrote: > I can confirm this, definitely something wrong with the server setup. > >

Re: [casper] SSL error, can't see the wiki

I can confirm this, definitely something wrong with the server setup. Thanks, Kaj On Wed, 11 Jan 2023 at 23:08, dps7802 wrote: > Casperites, > > I'm getting SSL errors when I try to look at links from my notes. > > I can see the main page > https://casper.berkeley.edu/ > > but when I click

[casper] SSL error, can't see the wiki

Casperites, I'm getting SSL errors when I try to look at links from my notes. I can see the main page https://casper.berkeley.edu/ but when I click the Wiki link on the main page I get an SSL error. https://casper.astro.berkeley.edu/wiki/Main_Page Error code: SSL_ERROR_RX_RECORD_TOO_LONG The

[casper] save the Holmdel CMB Horn

Dear CASPERites, Is this the first request to sign a petition sent to this exploder? It’s relevant to what we do: Please, CASPERites, consider signing, and forward to others. There is a great short video explaining the horn’s historical relevance, featuring a very enthusiastic founding

Re: [casper] very recent results from monitoring masers

Hi Ross and all, Yes I did exactly that. This research is one of the reasons I was so happy to get Heystek on board at HartRAO to improve our spectrometer. Better backends equal better (and more) science. Sorry I was trying to send this email to Andrew and did not check the cc list. Happy New

Re: [casper] very recent results from monitoring masers

I assume you removed the linear before performing the sine fit? On Fri, Dec 30, 2022, 6:09 PM Dr Gordon MacLeod wrote: > Hi Andrew, > > Hope you are enjoying your Christmas break, Merry Christmas! > > I thought I'd share with you an image I've recently created on excited-OH > masers at 6.035

[casper] ROACH2 output issues

Hi CASPER, I use ROACH2 to send data to the server. I wrote a script and ran it. I used wireshark to capture the data. ROACH2 sent data once, and the source address and destination address were both correct.[image: capture.png] I want ROACH to be able to send data to the server all the time,

Re: [casper] Model Composer fails to launch simulink

Thanks so much Mitch! As expected moving the libgmp seemed to do the trick! This was really helpful! Cheers, Mayukh Mayukh Bagchi (He/Him), MSc Graduate Student Department of Physics, Engineering Physics, and Astronomy mayukh.bag...@queensu.ca [Queen's

Re: [casper] Model Composer fails to launch simulink

Hi Mayukh, This issue is caused by library dependency differences between what Ubuntu base uses and what the Xilinx Model Composer and MATLAB Simulink are wanting to use. Particularly the various libgmp libraries used. To side step this issue requires altering your Model Composer installation

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