hat it has not yet been written back to main memory. That's one scenario,
though others may be possible.
Regards - Eliot Moss
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Dear gem5-ers:
While I'm not working on it just at the moment, I was hoping there might be
support for dynamic page mapping for I/O devices via the PCIe ATS (Address
Translation Services) PRI (Page Request Interface) facility. My reading of
the ARM SMMU code is that it is not *quite* there, and
tc., as on a real processor, but there
are many other small ways in which simulations
are not exact replicas of real CPUs.
Best wishes - Eliot Moss
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On 2/21/2024 5:04 AM, chengyong zhong via gem5-users wrote:
Thanks for the clarification.
IMP, it is a common scenario for modeling a HPC core, can anyone provide some
tips or sample programs?
On the other hand, I found that multi-bank is supported in the RUBY cache model(ruby/structures/BankedA
On 2/20/2024 9:29 PM, chengyong zhong wrote:
Hi Eliot,
Thanks for your kind reply. Are there any sample to implement the feature in
the Gem5 code repository?
I wrote: Unless I've missed something, gem5 does not provide dual / multi port
caches at present.
Hence, no example (that I am aware o
On 2/20/2024 8:18 AM, chengyong zhong via gem5-users wrote:
Hi all,
I'm using the O3CPU model for performance evaluation, we have two LoadUnit, I find that if dual load issued same time,
the second load will be blocked and rescheduled after a few cycles of latency.
The O3CPUAll and Xbar trace s
On 2/14/2024 1:14 PM, Eliot Moss via gem5-users wrote:
On 2/14/2024 12:52 PM, reverent.green--- via gem5-users wrote:
I would like to add some additional information. The register number does
vary in each iteration, sometimes it is above 100. So I think it should be
the physical register value
On 2/14/2024 12:52 PM, reverent.green--- via gem5-users wrote:
I would like to add some additional information. The register number does
vary in each iteration, sometimes it is above 100. So I think it should be
the physical register value. If my understanding is correct, the physical
register
On 2/14/2024 12:26 PM, reverent.green--- via gem5-users wrote:
Hey Eliot,
thank you for your answer. I have a follow-up question.
I know, that there are more physical registers than architectural ones and that the achitectural state should be set in
the final commit state.
So if the debug messag
mapping. If necessary, the architectural state
can be constructed, but generally would not be unless you're switching threads
or something. While IEW may update the registers (I believe), it is the
commit stage that makes the change "permanent".
Does that he
On 2/6/2024 11:13 AM, Nazmus Sakib via gem5-users wrote:
I think gem5 has this SplitDataRequest() method that breaks the request if it
would need more than one cacheline.
In fact, the page fault is occurring before it goes to the cache. The panic message says the address is 0x400. By
looking in
(byte) works fine !!
*From:* Eliot Moss
*Sent:* 05 February 2024 09:47
*To:* The gem5 Users mailing list
*Cc:* Nazmus Sakib
*Subject:* Re: [gem5-users] Effective address and ISA
but I hope I've answered
your question. Was it just a point of curiosity, or is there something
specific you're trying to do?
Eliot Moss
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directory. I'm sure that
people have written all kinds of shell scripts wrappers (as I have) to
handle this.
Eliot Moss
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be more helpful :-) ...
Eliot Moss
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model. Of course, the system may already
be doing that for you.
Another possible issue is whether you're firing up a gazillion
server processes in the OS. Trimming down the boot sequence
helped me save a lot.
HTH
Eliot Moss
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On 12/28/2023 9:24 PM, Arka Maity via gem5-users wrote:
Hi Eliot,
Thanks for your response. Yes, the above issue is just a warning and does not seem to affect the actual simulation runs.
I was just worried, that something could be wrong with my configuration, which might cause issues later.
it, just realizing that some edge that is supposed to be there won't
be. The program / script that sets up to call dot might possibly be changed to do some things in a different way to
avoid this, of course.
Hope this helps, at least with understanding what is going on
use a block *can* be moved
from the IO cache (for example) to the last level cache. A block brought
from memory is by definition clean, so that part holds. I think violation of
your assumption would be rare, and perhaps in some systems it would always
hold.
HTH.
Eliot
On 12/1/2023 6:24 PM, zahra moein via gem5-users wrote:
Thank you for your response.
I would like to seek further clarification regarding the parameter
RecvTimingResp:
void BaseCache::recvTimingResp(PacketPtr pkt)
Could you please confirm if this parameter represents a packet that is receive
On 11/30/2023 2:07 PM, zahra moein via gem5-users wrote:
Hi everyone,
As we already know, a "Read miss" at the last cache level (LLC) means that the desired block in the LLC for reading was
not found. Consequently, it is necessary to locate a victim block and copy the desired block from the mai
On 11/21/2023 12:16 PM, Arth Shah via gem5-users wrote:
Hi everyone,
I'm running a benchmark on the O3CPU model (aarch64) and see something strange that I wasn't able to understand. I see a
lot of Squashed loads and stores in the LSQ but it doesn't seem like it is due to branch misprediction or
-order) are the same.
If I am wrong I'm sure someone will correct me!
Best wishes - Eliot Moss
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You observed that the check on line 471 in tlb.cc did not seem to be the one
causing the fault in the case you were looking at. It occurs to me that the
line 471 check is for a *resident* page. If the page is *not* resident, some
other check would apply, and the fault might be raised when the OS
cc is where
the check in question happens:
https://github.com/gem5/gem5/blob/48a40cf2f5182a82de360b7efa497d82e06b1631/src/arch/x86/tlb.cc#L471
Note that the raw bits of the PTE have been abstracted out in the gem5 TLB
entry data structure, hence properties such as entry->user.
HTH
El
On 9/25/2023 4:59 PM, Leonard Peterson via gem5-users wrote:
Hello,
I'm trying to implement an instruction "myinst" that accesses dependent memory locations (similar to
pointer chasing) using the TimingCPU model (initiateAcc() and completeAcc()). For example:
myinst r0,0x14000
generally work in gem5 is that you get a stats dump at
the end of a run. There are also ways to request such dumps more frequently.
You get a lot of details about accesses to caches and memories. Are you
looking at stats dumps and not seeing what you hope for?
Best - Eliot Moss
On 9/5/2023 9:30 AM, 中国石油大学张天 via gem5-users wrote:
Hello, I would like to ask, in Gem5, will differences in the order of magnitude of operations such
as Add affect factors such as latency or execution speed?
I'm not sure how to answer that. Things depend so much on processor
model and workloa
Linux dtb file. This
was a while ago, so I'm not sure it's still true ...
Best - Eliot Moss
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On 8/14/2023 3:47 PM, Khan Shaikhul Hadi wrote:
Instead of directly connecting all level 1 caches ( icache, dcache etc) to CPU and next level bus, I
want to create a controller module that will have all those caches . This controller module will
receive all cpu requests and distribute them to ca
On 8/14/2023 1:42 PM, Khan Shaikhul Hadi wrote:
Initially I was thinking doing something like this as you suggested:
CpuSidePort cacheMemSidePortConnection = cache.memSidePort;
MemSidePort cacheCpuSidePortConnection = cache.cpuSidePort;
problem is when I looked into how python code don
On 8/14/2023 11:58 AM, Khan Shaikhul Hadi via gem5-users wrote:
In my code I'll have a simobject which has its own cache. As classical cache use CpuSidePort and
MemSidePort to receive and respond to request, I want to create some internal CpuSidePort and
MemSidePort in my simobject like below
On 8/6/2023 1:50 AM, Kaiwen Xue via gem5-users wrote:
On Sat, Aug 5, 2023 at 5:13 AM Eliot Moss via gem5-users
wrote:
On 8/5/2023 2:16 AM, Kaiwen Xue via gem5-users wrote:
Hi,
I'm new to gem5 and trying to follow the official tutorial [1] to
build an x86 opt target from commit hash 48
On 8/5/2023 2:16 AM, Kaiwen Xue via gem5-users wrote:
Hi,
I'm new to gem5 and trying to follow the official tutorial [1] to
build an x86 opt target from commit hash 48b4788.
The compilation failed with Error 134. Outputs didn't seem to be
meaningful - they are just normal building messages and
e to find each
prior stage of handling.
Best wishes - Eliot Moss
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On 8/2/2023 3:20 PM, Khan Shaikhul Hadi via gem5-users wrote:
But my gdb traces showing that request->isMemAccessRequired() is returning false. That's where I'm
confused. I'm running this simulation in SE mode.
I always deal with FS mode, but I don't think that matters.
I wonder if the parti
o do the write. Eventually a
suitable packet
will be sent to memory (interestingly, it carries no data).
HTH
Eliot Moss
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on
of what to do about the stats in this case, there being no obvious basis for
determining a latency. [We could change the senderState to include the time
the prefetch began, though, and use HardPFReq as the command.]
Regards - Eliot Moss
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flush operations.
Not sure when I will be able to accomplish putting these together
as patches for the powers that be to review ...
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On 7/11/2023 9:13 PM, Nick F via gem5-users wrote:
Good afternoon,
I have been trying to use Gem5 to research and study the performance of several different computer
architectures. However, I have been noticing that I may be unable to accurately model the
differences in cycle length for comput
On 7/11/2023 5:46 PM, Ayaz Akram via gem5-users wrote:
Hi Eliot,
Based on my understanding, when pkt->makeResponse() is called it updates the "cmd" of the pkt with
the appropriate responseCommand (this line of code: cmd = cmd.responseCommand();) . If you look at
"MemCmd::commandInfo[]" in pa
On 7/11/2023 3:03 PM, John Smith wrote:
Thanks for responding, Elliot. I somewhat understand that after the write is accomplished, the
returning packet won't have the data. But still, why is the returned value 0 in that case? Shouldn't
it still be equal to the memory access latency.
In the Ato
On 7/11/2023 3:20 PM, Ayaz Akram via gem5-users wrote:
Hi John,
If you are checking if the pkt is write when pkt->hasData() condition is true in recvAtomicLogic()
function, the check (pkt_is_write) will always be false. The reason is that a write pkt would have
already written its data to the
On 7/11/2023 1:28 PM, John Smith via gem5-users wrote:
So, I used the function pkt->isWrite() to check if the packet is a write request. And I observed
that inside the pkt->hasData() if condition, pkt->isWrite() returned false. Hence only the read
packets were entering the if(pkt->hasData()) con
On 7/11/2023 1:01 PM, Eliot Moss wrote:
On 7/11/2023 12:52 PM, John Smith wrote:
Okay, but I've also noticed that a WriteReq generally carries no data. Why exactly is that? Cause
if we are writing to memory, then the memory access latency shouldn't be 0 right?
I believe that happ
On 7/11/2023 12:52 PM, John Smith wrote:
Okay, but I've also noticed that a WriteReq generally carries no data. Why exactly is that? Cause if
we are writing to memory, then the memory access latency shouldn't be 0 right?
I believe that happens if the write got its data by snooping a cache.
The
On 7/11/2023 12:37 PM, John Smith via gem5-users wrote:
Hi everyone,
Could someone please help me with explaining what's happening in the below code snippet? It's the
receiveAtomicLogic() function in mem_ctrl.cc. Why are we returning the latency as 0 if the packet
doesn't have any data? And in
On 7/10/2023 5:17 PM, John Smith wrote:
I understood how to pass it. However, --param='system.membus.snoop_filter=NULL' doesn't seem to
work. I'm getting the following error:
NameError: name 'NULL' is not defined
I see. Well, this line was in an older version of XBar.py:
snoop_filter = Param
On 7/10/2023 3:59 PM, John Smith via gem5-users wrote:
I'm sorry. Here's the error message I got:
build/X86/mem/snoop_filter.cc:197: panic: panic condition !is_hit && (cachedLocations.size() >=
maxEntryCount) occurred: snoop filter exceeded capacity of 131072 cache blocks
That snoop filter ca
On 7/6/2023 12:48 PM, John Smith via gem5-users wrote:
I've looked into the schedule() function which is used to schedule events. But can this function be
used to simulate delays?
Not by itself. You schedule an event at something like curTick() + 100.
When the event happens, a function gets ca
On 7/6/2023 11:12 AM, John Smith via gem5-users wrote:
Greetings,
If I want to, for example, add a delay of 100 ticks before a line of code executes in the function
handleTimingReqMiss() in cache.cc, how do I go about doing that?
Generally speaking, you'll have to schedule an event and then do
On 7/4/2023 7:17 PM, Eliot Moss via gem5-users wrote:
Dear gem5-ers --
I am thinking of trying to put together something that roughly models ARM's
R82, which is an 8-stage, width 3, in order cpu. (It's also not a single
thing, but has numerous options you choose, and then set up R
Dear gem5-ers --
I am thinking of trying to put together something that roughly models ARM's
R82, which is an 8-stage, width 3, in order cpu. (It's also not a single
thing, but has numerous options you choose, and then set up RTL and can have
your design manufactured.) I see that there are thre
e a driver, and that driver maps a kernel and gives access to it,
allowing it to be mapped. But that's more complicated and more work than
just sharing an ordinary page.
Regards - Eliot Moss
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To unsu
use python to generate the tedious repetitive details).
Does this help? If you're asking is there anything pre-built for this, I
think the answer is no.
Regards - Eliot Moss
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On 6/22/2023 8:19 PM, Khan Shaikhul Hadi via gem5-users wrote:
Hi,
Thank you for your response with the patch link. It helped me a lot to understand what's going on
and limitations with clflush.
Do you have any idea if clflush alternative for arm isa is implemented in gem5 properly or not. I
On 6/22/2023 5:47 PM, Khan Shaikhul Hadi wrote:
Hi Eliot,
Thank you for your detailed answer.
For my current work, I need "CLFLUSH" and "MFENCE" to work properly. For clflush, I was planning to
modify the instructions execution to issue a flush request to the cache and handle the rest using
dir
tics requires loads to be
handled in order, and stores to be handled in order, but the two queues are
separate. (A load does need to see preceding stores to the same byte by the
same cpu, though.)
Regards - Eliot Moss
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On 6/20/2023 10:41 AM, 中国石油大学张天 via gem5-users wrote:
How to simulate a multi-core processor with Gem5, such as how to write configuration files? For
example, in the following form:
You don't write config files. You write python code that creates
instances of python classes. The gem5 system w
On 6/16/2023 11:39 AM, Khan Shaikhul Hadi via gem5-users wrote:
Hi,
I'm trying to figure out how "clflush" instruction works in gem5. Specially, how it issues a signal
to the cache controller to evict the block from cache hierarchy throughout the system and how it
receives confirmation to clea
On 6/16/2023 3:07 AM, Alexandra-Nicoleta DAVID via gem5-users wrote:
Dear gem5 Community,
I am currently using the gem5 simulator for my research work and I find it a powerful and insightful
tool for studying and understanding the inner workings of computer architectures.
I am particularly in
On 6/14/2023 11:30 AM, Derek Christ wrote:
Hello Eliot Moss, [one ell please]
a shared Python file with parameter settings sounds useful.
What I meant with running gem5 without the gem5 executable was to use the
compiled library directly from the Python configuration script.
From
uch slower.
HTH - Eliot Moss
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On 6/13/2023 9:07 AM, Vincent Abraham wrote:
Sure, I'm using the 22.1.0.0 version and the memory controller files (MemCtrl.py, mem_ctrl.cc,
mem_ctrl.hh) are located in src/mem/.
On Tue, Jun 13, 2023 at 8:32 AM Eliot Moss mailto:m...@cs.umass.edu>> wrote:
On 6/13/2023 7:10
On 6/13/2023 7:10 AM, Vincent Abraham wrote:
Hi,
I'm afraid just changing the parameters doesn't do the job for me. I want to add a delay at the
memory controller level, when it sends the requests to the memory. Could anyone point me to a
function where I should do the changes? Also, how should
Yes, adjusting some parameters in the memory controller
may be the easiest then - though Id have to analyze the
parameters and their meanings to see whether you'd need
to add new parameter(s) and code.
EM
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On 6/10/2023 2:32 PM, Vincent Abraham via gem5-users wrote:
I'm extremely sorry if I worded my question incorrectly. I'm actually trying to introduce a delay
whenever a read/write request happens in the main memory. For example, in a memory write, the data
would only be flagged as dirty after a
ite().
The one piece I did not mention yet is adding a sample to the histogram. When
a packet finishes and you know its latency, just do:
arrivalTimes.sample(latency);
The magic of stats will do the rest.
Cheers - Eliot Moss
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opposed to number when used in
python).
To be able to mention the class by name in fs.py you may
need to edit Options.py or MemConfig.py.
Some of these are more deeply embedded into the compiled
code and changes require a rebuild.
HTH - Eliot Moss
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the
new class. You can additional field of blk.hh / blk.cc, etc.
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On 5/7/2023 9:15 PM, Xiang Li via gem5-users wrote:
Hi,
I'm running X86 FS model, it would take me a long time for starting a FS model. I find it just using
one CPU, can gem5 use more CPU when running FS model?
No. It's modeling a whole complex system at the level of individual small
steps o
On 5/7/2023 10:50 AM, 中国石油大学张天 via gem5-users wrote:
Sorry for taking so long to reply to you. The goal I want to achieve is a simple reproduction of
this article (Extending Moore's Law via Computationally Error Tolrant Computing), ultimately
completing such a system. I believe the core goal sho
On 5/2/2023 1:01 PM, Shen, Fangjia wrote:
Regarding the data latency, I think it depends on whether the cache is sequential access (access
cache tags, then data) or parallel access (access tags and data at the same time - common
optimization for the L1 cache). See the code for BaseCache::calcul
ke MEM_TCK to be set before running this
piece of script, but otherwise to supply the default value 0.357ns (for
example). Once all the above is done, the command line itself must include
${GEM5_XPARAMS} to expand out all of the above. Also, I know its confusing,
but in an NVM only system, the NVM c
On 3/27/2023 6:13 AM, gabriel.busnot--- via gem5-users wrote:
Thanks, Gabriel, for your response, now a month ago. I want to turn my
attention back to this ... :-)
I can’t provide you with an assertive answer but I’ve also been looking at
CXL recently so here is what I understand so far.
F
On 4/20/2023 12:20 PM, 中国石油大学张天 via gem5-users wrote:
Okay, thank you. I have received your suggestion and I will think it over tomorrow. It's already
midnight here, so I'll go to bed first 😊。 Thank you again. By the way, it seems that every time I
send you an email, you always reject it.
If y
On 4/20/2023 11:56 AM, 中国石油大学张天 via gem5-users wrote:
Thank you for your reply again, hahahaha. I have been thinking recently whether it is possible to
design ALU through Verilog, translate it through Verilator or other tools, and ultimately use it in
Gem5. I'm not sure if it's feasible. I am so
On 4/20/2023 11:33 AM, Eliot Moss via gem5-users wrote:
On 4/20/2023 10:58 AM, 中国石油大学张天 via gem5-users wrote:
Hello everyone, I would like to ask, when executing non memory access instructions in Gem5,
shouldn't it be executed in ALU? But ALU has not been specifically designed and implem
On 4/20/2023 10:58 AM, 中国石油大学张天 via gem5-users wrote:
Hello everyone, I would like to ask, when executing non memory access instructions in Gem5,
shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented, how is
this instruction executed?
gem5 does not model a
on rate of nearly 10
insts per nanoseond
- Maybe the cpu is idle a lot
It should not be too hard to find where those statistics are defined, output,
and manipulated
in the source code, by using grep.
HTH - Eliot Moss
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ols myself, but am generally aware of them.
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On 4/12/2023 7:17 AM, Eliot Moss wrote:
On 4/11/2023 11:50 PM, 中国石油大学张天 via gem5-users wrote:
In gem5, where are the actual definitions of various functional units? For example, where is the
definition of IntAlu?
src/cpu/o3/FuncUnitConfig.py
Typed too fast:
Not to be snarky, but I found
On 4/11/2023 11:50 PM, 中国石油大学张天 via gem5-users wrote:
In gem5, where are the actual definitions of various functional units? For example, where is the
definition of IntAlu?
src/cpu/o3/FuncUnitConfig.py
No to be narky, but I found this in less than 30 seconds using grep over the
sources.
Best
, etc.
Regards - Eliot Moss
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their outputs (both the gem5 output
and the simulated program's output) to different files. When I
do this I also have some temporary mounts that I need to be
careful about so I copy the (fortunately small) different
mounted drive files.
Anyway, I do this all the time.
HTH --
On 4/5/2023 1:25 PM, Ponda, Esha Ashish via gem5-users wrote:
I tried to look into it and found that my OS has libprotobuf17 installed
./build/ARM/gem5.opt configs/example/arm/starter_se.py --cpu="minor"
tests/test-progs/hello/bin/arm/linux/hello
I am trying to run the above command and get
ld at this point - Ubuntu bionic offers 10, for example.
Regards - Eliot Moss
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an wind
backward and forward through an execution) to serve me well on
the C++ code.)
Best wishes - Eliot Moss
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do with how much of that memory is used
by the simulated application. Using grep over the source
code can help answer questions like this :-) ...
Regards - Eliot Moss
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think* I'm most interested in CXL.cache (giving a device
high performance coherent access to memory) and possibly
CXL.mem. I'm more interested in modeling the performance
than in modeling all the parameter read-out and setup that
would be in CXL.io, as I understand it.
Regar
On 3/22/2023 12:09 PM, Priyanka Ankolekar via gem5-users wrote:
Regarding the other part of your email:
Let me begin by saying I am a novice to both RISCV and gem5.
I have a RISCV RTL with a certain config. I have set up gem5 to match that configuration. I want to
make sure that they are indeed
On 3/22/2023 11:11 AM, Priyanka Ankolekar wrote:
Sorry, I should have clarified. I am using the RISCV ISA in gem5.
(As you could have done,) I checked the gem5 sources,
and it *does* model that register, returning totalInsts
as gem5 calculates that. Presumably that is the same as
statistics wi
little and tell
us what you're really trying to do, since neither the
retired instructions stats nor a full trace seem to meet
your need ...
Best - Eliot Moss
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On 3/20/2023 5:05 PM, Priyanka Ankolekar via gem5-users wrote:
Hi Eliot,
(Picking this up again after a while.) :-)
Thank you for your detailed answer. I was able to get a lot of useful data
points from these statistics.
Is there a way to get what instruction was retired/committed and when (tic
On 3/18/2023 10:40 PM, Ayaz Akram via gem5-users wrote:
Hi Eliot,
MemCtrl() memory controller in gem5 can control a single DRAM interface or a single NVM interface at
a time. I think one way to verify that things are set-up correctly is to confirm this from the
"m5out/config.ini". If config.in
t maybe that was not intended?)
Regards - Eliot Moss
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, then "type python" will show you.
Cheers - Eliot Moss
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On 3/13/2023 5:33 PM, Abitha Thyagarajan via gem5-users wrote:
Hi Eliot and Mirco,
I had the same issue with `palignr_Vdq_Wdq_Ib` being unimplemented. I tried compiling my application
binary (i.e., the one I was trying to run on gem5, not gem5 itself) to exclude SSE which contains
that instruc
me of the
valgrind tools, for example.
Others might be able to confirm or argue against my sense of the slowdown
factor (which I sometimes call the *time dilation* of simulation).
HTH - Eliot Moss
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nning with emulated syscalls, though of
course it will tend to be a bit slower to simulate.
Regards - Eliot Moss
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