Re: [casper] Regarding 32 channel ADC channel calibration in ROACH2

no? > > I am using ROACH2 revision 2 board. It has two 16 channel ADC cards. I > want to calibrate both the ADC cards at the same time. That’s why I > mentioned as 32 channel ADC calibration. > > Thank you. > > Sivasankar.S > > On Mon, Mar 18, 2024 at 11:10 PM 'Dan W

Re: [casper] Regarding 32 channel ADC channel calibration in ROACH2

hi sivakumar, for low sample rate FFT's (where the FPGA clock = sample rate), i suggest you consider: fft_biplex_real_2x (Real-sampled Biplex FFT, with Output Demuxed by 2) fft_biplex_real_4x

Re: [casper] state of the art single bit correlators

t; > > Altera (Intel) do the Stratix 10 GX with a maximum of 1152 LVDS pairs > running at 1.4 Gbps. > > > > Thanks, Neil > > > > *From:* casper@lists.berkeley.edu *On Behalf > Of *Dan Werthimer > *Sent:* 11 November 2023 21:30 > *To:* casper@lists.berkeley.

Re: [casper] state of the art single bit correlators

r this that I can > include in the paper and an IEEE transaction journal? > > > > Many thanks, > > Neil > > > > *From:* casper@lists.berkeley.edu *On Behalf > Of *Dan Werthimer > *Sent:* 11 November 2023 21:52 > *To:* casper@lists.berkeley.edu > *Subject:*

Re: [casper] state of the art single bit correlators

with more LVDS inputs, but there's no market. best wishes, dan Dan Werthimer Astronomy Dept and Space Sciences Lab University of California, Berkeley On Sat, Nov 11, 2023 at 1:39 PM salmon.na via casper@lists.berkeley.edu < casper@lists.berkeley.edu> wrote: > Hi Dan, > > > >

Re: [casper] state of the art single bit correlators

, 2^18 counters, and you'll also need 2^18 registers (for readout), assuming a 500 MHz clock. i think that will all fit into a giant FPGA, but it will be tight. i suggest you compile it and see. best wishes, dan Dan Werthimer Astronomy Dept and Space Sciences Lab University of California

Re: [casper] state of the art single bit correlators

correlator would manage making the > cross-correlations of 512 single bit channels at 1 GbpS, on say a single > FPGA, Xilinx or Altera ? > > > > Cheers, > > Neil > > > > *From:* casper@lists.berkeley.edu *On Behalf > Of *Dan Werthimer > *Sent:* 11 No

Re: [casper] state of the art single bit correlators

11, 2023 at 12:22 PM Dan Werthimer wrote: > > hi neil, > > by number of receiver channels, i presume you mean number of antennas? > are these single or dual polarization? > > how many spectral channels do you need in your correlator ? > > for a large number of spectra

Re: [casper] state of the art single bit correlators

hi neil, by number of receiver channels, i presume you mean number of antennas? are these single or dual polarization? how many spectral channels do you need in your correlator ? for a large number of spectral channels, you'll likely want to use an FX architecture correlator (not XF). in an FX

[casper] SNAP Boards are available again

dear casperites, if you are in need of SNAP boards (also called SNAP 1), these boards are back in stock at digicom electronics (contact info below). you can read about SNAP here: https://casper.astro.berkeley.edu/wiki/SNAP SNAP is an FPGA board with either 12 ADCs at 250 Msps, or 6 ADCs at 500

Re: [EXTERNAL] [casper] Re: Advice for radio astronomy components student project

hi colm, for frequency synthesizers: ebay, ali-express, and i think amazon have some synth boards with display and controls that go to 4.4 GHz for about $150. ds instruments has nicer synths (enclosed, usb/ethernet control, front panel display and controls) that cost $400 to $2K, and go up to 22

Re: [casper] Convert from 100GbE QSFP28 at RFSoC4x2 to 10gbE sfp+

hi parham, one way to do this would be to buy a switch with a 100Gbit port, and a 10Gbit port. but this would cost about $1K for the switch, and you'd need to purchase a pair of 100Gbit transceivers and cable. another way is to buy a 100Gbit NIC, and throw away your 10Gbit NIC, but this has a

[casper] casper instrumentation discovers gravitational waves constantly churn space and time

dear casper collaboration, you might have read about the discovery of the stochastic background of gravitational waves. "the cosmic hum of gravitational waves". i'm appending some media coverage from yesterday and today, from science and the washington post. there's a live video public

[casper] The deadline to submit abstracts to URSI radio science meeting in Japan has been extended until 10 February

*Submission Deadline Extension URSI GASS 2023* View this email in your browser *SUBMISSION DEADLINE EXTENSION* *for Regular Paper Submission, Young Scientist

[casper] abstracts due january 25, for URSI General Assembly in Japan August 023

Dear CASPER collaborators, reminder, abstracts are due january 25: Danny Price, Andrew Van Der Byl, and I are organizing a session on "real-time processing for radio astronomy" for the International Union of Radio Science (URSI) general assembly in Sapporo, Japan, August 19-26, 2023.

Re: [casper] SSL error, can't see the wiki

"advanced", and then click on "proceed to casper.astro.berkeley.edu " best wishes, dan On Wed, Jan 11, 2023 at 1:29 PM Kaj Wiik wrote: > Ah, been there too :-)... Take your time! > > Cheers, > Kaj > > On Wed, 11 Jan 2023 at 23:26, Dan Werthimer wrote: >

Re: [casper] SSL error, can't see the wiki

sorry about this. i think people can't get to the wiki right now because matt lebofsky is currently working trying to renewing our https certificate from letsencrypt. On Wed, Jan 11, 2023 at 1:19 PM Kaj Wiik wrote: > I can confirm this, definitely something wrong with the server setup. > >

Re: [casper] xillinx Kuria

tools and libraries to a variety of new boards. if several people express interest in porting casper to kria and other SOMs, we could start up a slack channel. xilinx is coming out with some more powerful SOMs that would be even more interesting for casper. best wishes, dan Dan Werthimer Astronomy

[casper] Seeking radio astronomy instrumentation abstracts for URSI General Assembly in Japan August 19-26 2023

Dear CASPER collaborators, Danny Price, Andrew Van Der Byl, and I are organizing a session on "real-time processing for radio astronomy" for the International Union of Radio Science (URSI) general assembly in Sapporo, Japan, August 19-26, 2023. Information on the conference is at:

Re: [casper] PAPER Correlater's Corner Turner Modes and MIRIAD Channel Mapping

hi wang, a bit more about the corner turner - you probably know about this, but just in case: for an FX correlator, there's an F engine for each antenna and each polarization to break the time domain signal into frequency channels. for large antenna arrays or large bandwidths, the correlation

Re: [casper] PAPER Correlater's Corner Turner Modes and MIRIAD Channel Mapping

hi wang, i can only answer two of your questions: 1) the "corner turner" is also called a "data re-order" or a "matrix transpose". it's job is to change antenna ordered data to frequency ordered data. 2) "miriad" is an open source data reduction software package for radio antenna arrays. e.g.

Re: [casper] Looking for suggestions for a QSFP+ IP to work with HTG RFSoC GEN2 ZU28DR

hi hussam, i'm a bit confused about what you are trying to do: are you seeking a board that connects FMC to QSFP+ ? several vendors make these boards. e.g.: http://www.hitechglobal.com/Accessories/FMC_Modules.htm i think you could adapt casper's 100Gbit ethernet block to drive the QSFP

[casper] CASPER 2022 workshop: registration payment problems

i haven't been able to pay for casper workshop registration using any of my credit cards. the payment website sends error messages about each card i've tried. has anybody else had this problem ? suggestions ? thanks, dan On Tue, Jun 28, 2022 at 3:43 AM Andrea Melis wrote: > Hi Ross, > > I

Re: [casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

nowhere in sight, stay afloat if lucky) > > > > Many thanks to you both for help. > > Best wishes, Neil > > > > *From:* Dan Werthimer > *Sent:* 19 March 2021 17:41 > *To:* CASPER Mailing List > *Subject:* Re: [casper] quantum entanglement sensing using hig

Re: [casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

hi neil, there's a quad 16 Gsps 4 bit ADC FMC board developed by CFA/Smithsonian that connects to a VCU128 FPGA board that might be useful for your work. the analog bandwidth of the ADC doesn't get up to 30 GHz, so you'd have to mix down your band before digitizing. you could break your 20 GHz

Re: [EXT]Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

can't see why firmware bit-streams would not be > identica/transferrablel for the two systems. > > On Tue, 9 Mar 2021 at 22:31, Dan Werthimer wrote: > >> >> perhaps there's an easier way casperite's could get about 10Gbit/sec >> ethernet from the RFSOC2x2: >> >

Re: [EXT]Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

connectors, and there are $50 SFP+ zysygy mezzanine boards... best wishes, dan . Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Tue, Mar 9, 2021 at 1:59 PM 'Timothy Bateman' via casper@lists.berkeley.edu wrote

Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

at 2:53 PM Dan Werthimer wrote: > > > hi dave, > > > i think the $1900 two input RFSOC 2x2 board only has 1 Gbe. > > > if you need higher I/O rates, they have a syzygy parallel I/O connector: > > > >>> The GEM is connected to the ARM PS of the RFSOC &

Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

; > "Breakfast is available daily in the kitchen. Menu may vary by locale." > > Bon appétit, > Dave > > On Feb 10, 2021, at 11:00, Dan Werthimer wrote: > > > > dear casper community, > > please see email below from xilinx's patrick lysaght, > about their

Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

time, but will be looking forward to hearing >> more about the board. Hopefully the presentation will be >> recorded. >> >> Cheers >> >> Glen >> >> >> > On Feb 10, 2021, at 2:00 PM, Dan Werthimer >> wrote: >> > >> > >

[casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

dear casper community, please see email below from xilinx's patrick lysaght, about their new low cost RFSOC board for academia, and the february 28 tutorial about this board. best wishes, dan -- Forwarded message - Date: Wed, Feb 10, 2021 at 10:00 AM Subject: Emailing:

Re: [casper] New setup installation problems (python setup.py egg_info" failed with error code 1)

hi kaj, regarding your interest in ZCU111: there's a casper slack channel on RFSOC that you might find useful. wei liu recently developed a casper ADC yellow block for the ZCU111. best wishes, dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University

[casper] Fwd: Prize postdoc opportunity

Hi Dan, You may know of some clever EE or experimental physicist who would be interested in this job: https://academicjobsonline.org/ajo/UCD/Physics/BPF Nominal application soft deadline is 10 days away. Thanks, Tony -- You received this message because you are subscribed to the Google

Re: [casper] ADC ROACH2 clock signal, or Function generator

://www.valonrf.com/frequency-synthesizer-6ghz.html best wishes, dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Tue, Dec 1, 2020 at 11:36 AM luis javier Ulloa wrote: > Hello everyone, I hope you are well. > I am w

[casper] 32 port 100Gbe switch for $1400

dear casperites, if you are seeking a 32 port 100Gbit ethernet switch, terabit systems has arista DCS7060 for $1400. these are "used", but the one we bought looked new, and had arista packaging. we've bought a few switches from daniel at terabit and all have worked well so far. they test every

[casper] High Density FPGA 1U Server with 3.2 Tbit/sec ethernet

Hi Casperites, If you are seeking a 1U server with four large ultrascale+ VU13P FPGA's (each with 2TB DDR4), 32 100Gbit/sec ethernet ports (3.2 Tbit/sec full duplex), and a motherboard with two zeon processors and lots of DRAM, here's a blurb: Pack Four Achronix, Intel, or Xilinx FPGA-based

Re: [casper] MKID ADC-4x problem the clock rate of FPGA

hi ZHANG Laiyu, from rick, who designed that ADC board: "The ADC produces full-parallel data at 550 or 400MHz DDR, so the ADC core would normally run at half of this- I don't see any reason to run it slower. I can't remember who did the yellow block; I have code that runs on a mini-roach for

Re: [casper] ADCs in CASPER

. there's a dual 10.6 Gsps ~10 bit AD ADC board under development at GBO. best wishes, dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Mon, Oct 26, 2020 at 5:50 AM Gareth Callanan wrote: > Hi Casper Commun

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

hi jeb, regarding your ZCU111 RFDC question: here's some info that might be helpful from wei liu, cc'ed on this. btw, wei liu recently made casper yellow blocks for the ZCU111 ADC's. he's now working on ZCU111 yellow blocks for 1, 10, and 100 Gbit ethernet. from Wei Liu:

[casper] seeking Roach 1 boards

Dear Casperites, My colleague Anton Tremsin (cc'ed), from the Berkeley's Experimental Astrophysics group at Space Sciences Laboratory, still uses Roach 1 boards with CX4 connectors in their detectors and would be very thankful if someone can donate/sell them decommissioned Roach 1 boards. Anton

Re: [casper] references to recent cross-correlator technology developments

Hi Neil, regarding using GPU's or FPGA's for the X engine of an FX correlator: You probably appreciate GPU's are best used in correlators with a large number of antennas. The problem with using GPU's for a small number of antennas is the GPU is limited by input data rate. The correlator input

Re: [casper] arecibo broken cable causes damage to dish and gregorian

3R (operations and spectrum manager) says the panels can all be replaced but the facility will be down for a while. https://www.ucf.edu/news/broken-cable-damages-arecibo-observatory/ Hopefully, the structure will be secure for any of the fall's hurricanes or tropical storms! 73, Ward N0AX

[casper] arecibo broken cable causes damage to dish and gregorian

sad news about arecibo damage from broken cable: photo of damaged dish in this news piece: https://www.vice.com/en_us/article/9358be/a-broken-cable-has-wrecked-one-of-earths-largest-radio-telescopes a few details : Becker, Tracy M. tracy.bec...@swri.org via

Re: [casper] Converting ADC output back to 8 bits

hi molly, i think most engineers and programmers that deal with fixed point numbers prefer to use fractional representation between -1 and +1, as then it doesn't make much difference how many bits the numbers have - they will all have the same range. a 16 bit number will range from -1 to +1, and

Re: [casper] 10GbE_V2 adc_mkid_4x tut2

hi zhang laiyu, here are three things you could try: 1) send your adc samples into a short fifo, then feed five of the 12 bit ADC samples at a time (instead of four samples) from the fifo into each 64 bit word feeding the 10Gbe block. do this for the first 103 fpga clocks out of 128,

Re: [casper] ROACH2 / katADC million channel spectrometer

hi molly, regarding making a large FFT from small FFT's: as jason pointed out, there's a way to compute a million point spectrum from lots of small FFT's. the technique jason described is to implement a course channelization polyphase filter bank spectrometer to divide the band into 1024

[casper] Fwd: warning about Tenma dc power supplies

-- Forwarded message - From: Paul Horowitz Date: Tue, Feb 18, 2020 at 7:24 AM Subject: warning about Tenma dc power supplies we've had an epidemic of failing Tenma dc supplies that fail to maximum voltage (shorted pass transistor), and have blown out expensive stuff in some

Re: [casper] Solar Spectrometer Channeliser

to minimize image rejection, and the adc's might not have enough analog bandwidth. quadrature dowconverters also need good amplitude and phase matching to reduce image rejection, but it's a bit easier to manage this than interleaved adcs. dan Dan Werthimer Marilyn and Watson Alberts Chair

Re: [casper] Issue compiling SNAP design with reorder block

Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Thu, Feb 6, 2020 at 9:05 PM Danny Price wrote: > Hi all, > > I am having difficulty compiling a SNAP design, which I have narrowed down > to a reorder block

Re: [casper] Solar Spectrometer Channeliser

rsts do (easily > 40-50dB or more) for bright bursts. We have built 8 bit spectrometers in > 40-80Mhz, but have found then when the burst is pretty strong, saturation > effects starts kicking in. > > > Thanks, > Mugundhan > > > On Wed, 5 Feb 2020, 21:52 Dan Werthimer, wr

Re: [casper] Solar Spectrometer Channeliser

Gsps, or 16 inputs at 2 Gsps), but i think the new generation has 14 bit ADC's ?the RFSOC boards cost more than snaps, but RFSOC was designed in dublin, so you can probably get one from xilinx dublin the ZCU111 board has not been fully casperized yet though. best wishes, dan Dan

Re: [casper] One input FFT block [ROACH2]

hi franco, are you looking for an FFT with a real input and complex output? you mentioned you are connected the unused inputs of the the biplex_real-4x to ground. this is useful, as the compiler should remove all the unused parts of the FFT, although it's probably not as resource efficient as a

Re: [casper] heliospectroscope

are on the casper wiki pages. best wishes, dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Tue, Nov 12, 2019 at 1:27 AM Tavi B wrote: > Hello, > > I'm new in this research, in Romania there is no scienti

Re: [casper] 10Gb packatizer from desktop.

can you verify your spectrometer design in simulink ? simulink allows you to read data from a file and use that data as a test vector. you can also use the simulink virtual test equipment generators to generate test vectors for your spectrometer: (sine, square, triangle wave generators, noise

Re: [casper] SNAP ADC at 1GSps

with the adc's clock termination resistors and clock distribution chip parameters, or use an external dual 1gps zdoc adc. best wishes, dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Fri, Oct 11, 2019 at 12:56 AM Nitish

Re: [casper] Strange leakage effect in high decimation spectrometer in ROACH2

with a pure sine wave, and when the sine wave grows by 10 bits, you'll have 34 bits of dynamic range at the end of the fft computation. best wishes, dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Thu, Sep 12, 2019 at 7:15

Re: [casper] Strange leakage effect in high decimation spectrometer in ROACH2

significant bits, (eg: an 8 bit adc is input into the 8 MSB's of an18 bit FFT), then you need to downshift every stage (set shifter setting to ). best wishes, dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Wed

Re: [casper] Red Pitaya Autocorrelation spectrometer using casper biplex FFT

... if you add a few LSB of noise or signal, then the pattern is not dependent on the DC offset. best wishes, dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Fri, Sep 6, 2019 at 9:51 PM Mugundhan vijayaraghavan

[casper] casperites receive breakthough prize

casperites, several casper people received the breakthrough prize today for making the first image of a black hole, including jonathan weintroub, homin jiang, nimish patel, matt dexter, arash roshanineshat, laura vertaschitsch, and casper co-founder mel wright. the $3M prize is divided equally by

Re: [casper] Strange leakage effect in high decimation spectrometer in ROACH2

ght? because I tried to add noise to my system and didn't see a > difference. > > > El mié., 4 sept. 2019 a las 14:14, Dan Werthimer () > escribió: > >> >> you can get extremely high SNR if you add noise to your sine wave signal. >> and then integrate many spect

Re: [casper] Strange leakage effect in high decimation spectrometer in ROACH2

get 150 dB SNR if you add enough spectra together. dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Wed, Sep 4, 2019 at 10:39 AM Sebastian Antonio Jorquera Tapia < sebastian.jorqu...@ug.uchile.cl> wrote:

Re: [casper] Use of xBlock for block scripting

i don't know much about xblocks, so can't add much to jack's comments, except: about a dozen years ago chris dick and others at xilinx recommended casper use xblocks, so hong chen tried it out, and ported several of the casper dsp blocks. i think it worked well, and hong chen liked xblocks, but

[casper] email from Digicom about Roach2 boards : get 'em while they last

Hi Fellow Casperians, Mo at Digicom Electronics asked me to relay this message to you: - Dear Casper Collaborators, Due to reduced volume of demand for Roach2 boards we are approaching end of life. If you have any scheduled plans to acquire any of these boards, or associated ADC

Re: [casper] FIR and decimating CIC filter

jason, some info on SSR on pages 114-117 of: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug897-vivado-sysgen-user.pdf dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Thu, Jun 27, 2019

Re: [casper] FIR and decimating CIC filter

ndy, luke and the folks at green bank can help with this if you are interested. best wishes, dan Dan Werthimer Marilyn and Watson Alberts Chair Astronomy Dept and Space Sciences Lab University of California, Berkeley On Thu, Jun 27, 2019 at 7:51 AM Jason Manley wrote: > Hi CASPERites &

[casper] Fwd: Designing next-generation networking platform? Introducing VCU129 Evaluation Kit

hi casperians, is your casper application I/O bound ? this $15K VCU129 ultrascale+ FPGA board has 2.5 Tbit/sec in, 2.5 Tbit/sec out. https://www.xilinx.com/products/boards-and-kits/vcu129-pp.html dan View on Web

[casper] $9K VCU128 Board, Virtex UltraScale+ HBM Production FPGA

View on Web [image: Xilinx Logo] Available Now [image: VCU128] *Virtex® UltraScale+™ HBM FPGA Evaluation Kit*

Re: [casper] 1-bit quantization using Xilinx transceivers

chain. they found the LVDS inputs have high bandwidth (but not nearly as high as the serdes inputs), and they have have low offset and the offset is fairly stable with temperature. i think this work is written up in a chapter in andrew howard's thesis. best wishes, dan Dan Werthimer Marilyn

[casper] postdoc position at JPL

Here's radio astronomy instrumentation postdoc at JPL (from Joe Lazio): https://jpl.jobs/jobs/2019-10427-Radio-Astronomical-Instrumentation-Postdoctoral-Scholar > Located in Pasadena, California, JPL has a campus-like environment situated on 177 acres in the foothills of the San Gabriel

Re: [EXTERNAL] [casper] seeking high accuracy GPS disciplined time/frequency standards ?

you are not going to rely on raw GPS, > rather on the time-corrected GPS time. In the meantime your clock will > freewheel with your oscillator, which will be extremely accurate anyway. > > > > John > > > > > > > > On Sat, Mar 9, 2019 at 3:08 PM Dan Werthi

Re: [casper] Timestamp in ROACH2 and PTP

hi franco, i think we picked the word "arm" because it's similar to arming a gun, getting it ready to fire, but not firing it. "arm" is not the signal that directly resets the elapsed time counter. the arm signal is a software command that says: on the next 1 PPS, the elapsed time counter

Re: [EXTERNAL] [casper] seeking high accuracy GPS disciplined time/frequency standards ?

ric disturbance? > > > On Mar 8, 2019 2:55 PM, Dan Werthimer wrote: > > hi robert, randall, dale and casperites, > > thanks for your time/freq standard suggestions. > > our problem to get accurate 1 PPS wrt UTC is not limited by internal > oscillator stability. > t

Re: [casper] Timestamp in ROACH2 and PTP

hi franko: i think jack meant "<100ns" in his email below. (not "<100us"). here's another description of the technique used in casper instruments to get accurate time stamps: from peter mcmahon's thesis, section C.5: https://arxiv.org/pdf/1109.0416.pdf C.5 Precise Timing using ARM and 1PPS

[casper] seeking high accuracy GPS disciplined time/frequency standards ?

in a somewhat related question. can anybody give us advice about GPS disciplined oscillators time/freq standards that are very accurate wrt UTC? we don't want to buy a hydrogen maser (too pricy). we have been looking at a company called endrun technologies that sell time/freq standards accurate

Re: [casper] SNAP Tutorial 3

hi david, when you have no signal going into an adc, it will typically chatter between two values, around -1, 0 and +1, and you'll see a lot of RFI and interleave spurs, so the spectrum you sent around doesn't surprise me, but if you put in a sine wave that is much larger than the ADC chatter,

Re: [casper] VCU118 Support

jack, did you do all this work? hong ?brian ? dan On Mon, Jan 14, 2019 at 7:23 PM Jack Hickish wrote: > Hi CASPERites, > > I know a few of you have been playing around with the VCU118 Virtex > Ultrascale Plus dev board. For a while the toolflow has been able to > compile designs for

Re: [casper] SNAP2 with ADC16 board

put the > samples in time-stamped packets and ship them out towards a processing > server. > > We already have one SNAP2 board. Once, Dan Werthimer suggested using the > ADC16 board > to obtain 16 additional channels. We have a few questions about this > implementation: > &g

Re: [casper] CASPER design question

hi dale and neal, do you know how many frequency channels are needed? or is this a continuum correlator ? i think the lowest cost system would be a conventional casper packetized FX correlator architecture using snap1 boards, a 40Gbit ethernet switch (for the corner turn), possibly adding an

Re: [casper] Getting a new ROACH2 board

hi franco, roach2's, and various accessories (power supply, enclosure, memory, mezzanine boards, ADC boards), are available from http://digicom.org. it's an open source board, so you can build it yourself, but it's easier to purchase a tested assembled board from digicom. the virtex6 fpga on

Re: [casper] Inverse of fft_wideband_real

dave, jack, jonathan, going back to august emails, here's another trick to computing an inverse FFT from a forward FFT. the usual technique to implement a inverse complex FFT from an complex forward FFT: 1) complex conjugate the input 2) complex forward FFT 3) complex conjugate the output 4)

Re: [casper] New Pulsar Back-end

hi Guillermo, here's some info on a snap based fast read out spectrometer for pulsar and frb: https://casper.berkeley.edu/wiki/Crab_Giant_Pulse_Project it's not exactly what you want, but it might be a start: this snap based spectrometer has two inputs (two pols) at 2 Gsps, using an external

Re: [casper] Availability of SNAP board for the Mauritius Deuterium Telescope

o SDR and FPGA development > and once the experiment is over the SNAP can be reused for any other > experiment. Prof Inngs and I agreed that to build expertise for hosting > SKA type telescopes it is essential we get started with what the astronomy > community is using. >

Re: [casper] Availability of SNAP board for the Mauritius Deuterium Telescope

es, and nothing on the FPGA, except demod, > decimation. > > Thanks for the ideas coming in to the team. > > Regards > > > On Fri, 25 May 2018 at 18:59, Dan Werthimer <d...@ssl.berkeley.edu> wrote: > >> >> >> if vinand, >> >> if you wa

Re: [casper] Availability of SNAP board for the Mauritius Deuterium Telescope

if vinand, if you want to digitize 48 signals with 250 KHz bandwidth, you might want to consider purchasing a 48 input PCIe ADC board and doing the signal processing in a computer (in software). (not use FPGA boards). but then you'd have to mix the deuterium line to baseband, so you'd need 48

Re: [casper] temporary ROACH2 faults after power dips and spikes

hi jonathan, here's a remote possibility that might explain some of the behaviour you are seeting: when the power goes down to your roach2's, does the power also go down on the sample clock or 1 PPS distribution? if the sample clock continues to be fed to the ADC's, then the CMOS adc chips can

Re: [casper] Xilinx RF SoC

hi colm, thanks for telling us about this interesting board. do you know what the rough cost is? i don't see any high speed ethernet ports, but perhaps the board could talk to a NIC over PCIe3, or we could make a backplane that connected the PCIe serdes lanes to a QSFP+ connector... RFsoc data

Re: [casper] Quick prototype platform

hi karl, to add to what jack emailed about using a snap board for your non-astronomical array: snap has 12 ADC's on board.if you want more analog inputs, you could plug in an ADC16 board; then you'd have 12 + 16 = 28 inputs, up to 250 Msps each. as jack pointed out, snap only has a pair of

Re: [casper] KAT-7 KatADC on ROACH2

hi dale, thanks for helping out zhu yan and FAST. dan On Wed, Mar 7, 2018 at 5:14 AM, Gary, Dale E. wrote: > Hi Yan, > > This sounds like the problem we had until Matt Dexter and Dave MacMahon > determined that some KatADC registers need to be set for correct ADC >

Re: [casper] Myricom 10G-PCIE-8A-C

> the value to 1024 and it works correctly. > > I no longer see UDP packets when I adjust the value to 512 ... > > Can it be a problem with my network card? > > Regards > > 2018-03-05 19:15 GMT-06:00 Dan Werthimer <d...@ssl.berkeley.edu>: > >> >>

Re: [casper] Myricom 10G-PCIE-8A-C

-250MHz 50Ohm 0dBm > > According to what I see in the image "input_to_quadc.png" that I obtained > with an oscilloscope, the signal that input to the quadc is -5.5dBm. > > Could this be the problem? > and if this were the problem, why before everything worked well? > &

Re: [casper] Myricom 10G-PCIE-8A-C

hi rolando, are you dropping packets? have you used tcpdump or other packet sniffer code (eg: gulp...), to investigating what's going on when you change the integration time? is the number of packets/second correct for the integration time you set? if not, perhaps you accidently changed the

Re: [casper] CASPER Workshop 2018 - First Announcement

dear ran, thanks for sending out this email. perfect ! and thanks for all your work arranging the casper workshop. dan On Wed, Feb 7, 2018 at 7:05 PM, Ran Duan wrote: > Dear Colleagues, > > > We are pleased to announce that the 2018 CASPER Workshop will be held at

Re: [casper] Pulsar backends

hi rich, i know a bit about the meerkat pulsar search. (i'm not on the team, but we've been working with those guys...). i don't know much about meerkat pulsar timing (the timing and search are different groups). scott ransom knows a bit about SKA pulsar search design team at oxford. i know a

Re: [casper] adc5g four inputs

hi michael, i don't know anyone who has converted the dual input ADC5G to a quad input board; as you pointed out, you'd to add two sma connectors, two baluns, and associated input circuitry. if you need several of these, it might be best to make a revised PCB. there are a few companies that make

Re: [casper] Dealing with extreme RFI

hi xavier, it sounds like you are switching between two signal sources, one is a reference load with a very small signal level, and the other is a signal from the sky with strong RFI? if that's the case, can you turn up the signal level on your reference level? it would be best if the RMS is

Fwd: [casper] Dealing with extreme RFI

hi xavier, we use 8 bit wideband digitizers at arecibo and parkes where the RFI is fairly strong. do you think you might be able to get away with 8 bits ? : perhaps you know all this adc and dsp dynamic range stuff already, but here are some thoughts: an 8 bit digitizer usually works well if

[casper] nrao's central lab is seeking a correlator designer

dear casperites, anybody want a job ? NRAO's central design lab (CDL) is hoping to hire an engineer or researcher to help design correlators for ALMA and ngVLA. job description here: http://jobs.jobvite.com/nrao/job/oUkj6fwn -- You received this message because you are subscribed to the

Re: [casper] Application of SMA correlator design to a larger array

hi dale, i'd be happy to talk to you on the phone about pros and cons of different options if you'd like. jack also told me a bit about your plans - he'd be good at providiing advise on the different options.. dan 510-418-0546 On Tue, Nov 7, 2017 at 9:29 AM, Gary, Dale E.

Re: [casper] CASPER to ASIC

for example these two references: A 1.5GS/s 4096-Point Digital Spectrum Analyzer for Space-Borne Applications <http://bwrc.eecs.berkeley.edu/php/pubs/pubs.php/1090.html>, Brian Richards, Nicola Nicolici, Henry Chen, Kevin Chao, Robert Abiad, Dan Werthimer, Borivoje Nikolic, IEEE Custom Integrated Ci

Re: [casper] contact

adding to adam's email: all casper software, gateware, GPUware, tools, libraries, etc, are free and open source. but you also need software from xilinx and from the mathworks to be able to compile casper fpga code. if you are at a university, you can likely get a donation of the xilinx

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