Hello all,
I've been trying to move away from such big heavy models, my ultimate goal
being to have VHDL black boxes instead of precompiled ones made from Xilinx
or Casper DSP blocks.
Jack Hickish's HDL Black Box Tutorial (
https://casper.berkeley.edu/wiki/Tutorial_HDL_Black_Box) demonstrates a
v
bug_snap_select = debug_snap_select['coarse_72'] # Update
the desired bit (or bits, using the conveniently provided dictionary in
this case)
fpga.write_int('control', struct.unpack('>I',
control_reg_bitstruct.build(control_reg))[0]) # Write the new data back.
Does anyone have any thoughts? Would this perhaps help with maintainability
and debugging, or is it a bit of overkill, solving a problem that wasn't
really there in the first place? I'm eager to hear any feedback from others
who may have walked this path before.
I've formatted the python code portions of the above message to a
fixed-width font, I hope it comes through on the mailing list...
Regards,
James Smith
I think currently the fpg files that are automatically
> parsed by casperfpga are only generated for ROACH2, but it would be easy to
> add ROACH support.
>
> Cheers
> Paul
>
>
>
>
> On 20 March 2015 at 09:08, James Smith wrote:
>
>> Hello all,
>>
>
a library anyway and seeing if I can get it to work with ROACH
using a work-around which Paul suggested. I'll post my findings to the
mailing list next week sometime.
Regards,
James
On Fri, Mar 20, 2015 at 10:01 AM, Marc Welz wrote:
>
>
> On Fri, Mar 20, 2015 at 7:08 AM,
Hi all,
As per Paul's suggestion, I'm migrating towards using registers and snaps
with bit-fields in them, and casperfpga instead of corr for the computer
side of things. There was a minor problem with the "program" function, but
I fixed it (I think?) and my pull request is currently waiting for t
g and writing other registers works just fine. Telnetting into the
ROACH and trying to write the snap_ss_ctrl register that way also fails, so
it's quite likely that the problem is not with the casperfpga module (the
snapshot one anyway, don't know about the KatADC one).
Could there be a
uture, but if anyone else comes across
similar problems then that might be a good place to start looking for a
solution.
Regards,
James
On Tue, May 19, 2015 at 12:49 PM, James Smith wrote:
> Hello again, Casperites,
>
> Further tracking of my challenge, I removed the KatADC from the
Hi all,
I'm working on a simple design for a two-stage high-resolution
spectrometer, which almost gets finished compiling, sysgen seems to finish,
and then at the end fails with a most uninformative error message:
##
## Creating EDK files ##
##
Er
in your model file.
>
> Cheers
> Paul
>
>
> On 1 June 2015 at 10:27, James Smith wrote:
>
>> Hi all,
>>
>> I'm working on a simple design for a two-stage high-resolution
>> spectrometer, which almost gets finished compiling, sysgen seems
t; Hi James
>
> You can see that your error is happening in this section of that script:
>
> if isempty(strtrim(value)) == 1,
> error('Empty value?');
> end
>
>
> So add some debug logging there and rerun the gen_xps_add_design_info
> part of the build.
>
gging to the script, so check out the latest
> version.
>
> Have you used the debug logging before? Try setting:
>
> casper_log_groups={'all'}
>
> And rerunning your scripts.
>
> Cheers
> Paul
>
>
>
> On 1 June 2015 at 15:24, James Smith wrote:
>
>
Hi Victor,
We used to use Ubuntu 14.04, and it kind of worked, but it wasn't stable.
Switched to the most recent version of CentOS about a month ago and haven't
had problems since.
Xilinx v14.7, Matlab 2012b.
Regards,
James
On Wed, Jun 24, 2015 at 1:10 AM, Mark Wagner
wrote:
> Hi Victor,
>
>
Hello Victor,
Are you planning on using telnet or python? If python, check out the
casperfpga module on ska-sa Github. It's not documented in the tutorials
unfortunately, and it takes a little bit of doing to install, but once
you're there it's very easy to us, especially with ipython.
I've recen
Hello Aniket,
casperfpga is the one you want:
https://github.com/ska-sa/casperfpga
It has a few dependencies to build, but it's much nicer than corr.
Regards,
James
On Tue, Sep 1, 2015 at 11:39 AM, aniket
wrote:
> Dear CASPER colleagues,
>
> Myself Aniket Hendre working as a Project Engineer
d due to receiving some commands it didn't like.
>>
>> Kind regards.
>> Craig
>>
>> On 2015-09-02 08:18, aniket wrote:
>>
>>> On 2015-09-02 11:28, James Smith wrote:
>>>
>>>> Hello Aniket,
>>>>
>>>> You seem t
Hello all,
I've put together a little Qt GUI in python for monitoring what's going on
on a ROACH. It should work on a ROACH2 as well, but I don't have one to
test it.
If anyone would like to use it, it can be found here:
https://github.com/james-smith-za/RoachRegisterMonitor
May
Something we've had with PFBs and FFTs is that they don't resize properly
if you simply change their length in a design. It may be worth deleting
them and putting new ones.
On 12 Sep 2015 20:03, "Danny Price" wrote:
> Hi Michael
>
> I always blame the sync gen first! I’d suggest just sending out
Hello Neil,
CASPER tools could probably do what you're looking for, but I found your
description a bit confusing. You're going to need to clarify somewhat.
Regards,
James
On Fri, Dec 18, 2015 at 4:15 PM, Neil Salmon wrote:
> Anyone help?
>
>
>
> I’m working in academia and need to build a 300
Hi Rolando,
Have you tried one of the built-in Xilinx FFTs? As far as I know, the
Casper ones really only exist because the Xilinx ones only accept one input
at a time.
If you do use them, they are really efficient with resources.
Regards,
James
On Tue, Jan 19, 2016 at 11:11 PM, Rolando Paz w
Hi Rolando,
I can't recall that it does, off the top of my head, but the Casper one can
be set up to use just one input. This is what I've done in the past, I
think.
Regards,
James
On Wed, Jan 20, 2016 at 7:39 AM, Rolando Paz wrote:
> Hi James and Andrew
>
> Thank for yours advices.
>
> I'm t
urce-wise, they're the same. This is because of algorithmic
>> limitations; there is a resource efficiency you gain by doing two complex
>> FFTs at once.
>>
>> This is a time for a streaming Xilinx FFT.
>>
>> --Ryan
>>
>>
>> On 01/19/2016
Hi all,
Are the presentations from the 2016 workshop going to be made available at
all?
I'd be keen to review some of the things that I saw there.
Regards,
James
Haven't encountered that specific issue before but I see a capital letter
in your path. That may be an issue.
On 11 Feb 2016 12:44, "Mugundhan vijayaraghavan"
wrote:
> Hello guys,
>
> I'm running matlab/xilinx and mssge tools on a ubuntu 14.04 system. When I
> do casper_xps and start compiling, I
Matlab_2012b
>>>
>>> Particularly this step:
>>>
>>> The syntax in the Xilinx Perl scripts is not supported under the Ubuntu
>>> default shell Dash. Change the symbolic link sh -> dash to sh -> bash:
>>>
>>>- cd /bin/
>>>
I should probably mention - clone casperfpga from the "devel" branch, not
"master".
On Mon, Feb 15, 2016 at 9:13 AM, James Smith wrote:
> Mugundhan,
>
> The fpg file is intended for ROACH2 and tcpborphserver3 - you can safely
> ignore it, but it's useful fo
Hi all,
Is there any reason to believe that the input on the KatADC board (or any
ADC board which we might end up using) is not a 50-ohm? How would one go
about determining that? The wiki says nothing about its VSWR or related
information.
Any thoughts would be appreciated.
Regards,
James
Hello Vishwa,
I'll answer your questions slightly out of order - someone else may be able
to give a more thorough answer but just for a first order:
3. As far as I understand it, "corr" was written specifically for the KAT-7
digital back-end, so many of its features are specific to that. As far a
Hello Shotaro,
What are the specifications of the computer that you're using?
Regards,
James
On Fri, Jul 15, 2016 at 8:07 AM, 江藤 翔太郎 (鹿児島大学) wrote:
> Dear Casperites,
>
> I am Shotaro, a graduate student at Kagoshima university, working on a new
> spectrometer for Nobeyama 45m telescope using
Hello Alec,
I've just cloned the repo fresh and it installed just fine. Looking at the
line in question, it might be using a feature of a slightly newer version
of python. I have python 2.7.6 installed - that would be my first
suggestion. Would it be difficult to update your python version in your
Hello Heystek,
It would be a bit easier to debug if you posted the terminal session, along
with the commands you ran.
Also, please run "ls -l" in the directory and post that as well. It might
just be that you need to give the file executable permissions.
Regards,
James
On Mon, Aug 15, 2016 at
untu:/opt/mlib_devel-master$
>
> if this is unclear I attached screenshots of the terminal session.
>
>
> Thank you for your help
>
> Heystek
>
>
>
>
>
>
>
>
>
>
>
> On Mon, Aug 15, 2016 at 11:27 AM, James Smith wrote:
>
>> Hello H
ur IT guy to give you sudo rights, but if you are
>> working off the university server that may be an issue - as James says, you
>> shouldn't need this if you install into your home directory.
>>
>> Kind Regards,
>>
>> Adam
>>
>> On Mon, Aug 15, 2016
en first
> pass text file at
> /home/heystek/Desktop/tut1/sysgen/sysgen/masterScript423796839757439882
> 5.pl
> line 559'
>
>
>
>
> Do you perhaps have an idea how I can fix it?
>
> Thanks for all the help.
>
> Have a wonderful day.
>
>
l or .slx?
>
> Thank for your help
>
> Heystek
>
> On Tue, Aug 16, 2016 at 5:40 PM, James Smith wrote:
>
>> Hello Heystek,
>>
>> Just to get you an answer quickly, try the following command:
>>
>> chmod 777 -R /home/heystek/Desktop/tut1
>>
Hello Heystek,
Before you program the ROACH2, I'd suggest trying fpga.is_connected() and
fpga.est_clk_frequency() to check whether you can actually communicate with
the ROACH2. It might be a network cable that's been unplugged by accident -
that's where I've seen those errors before. The
fpga=casp
I can ping the board, but I cant
>>> open a Telnet connection.
>>>
>>> When I open a ttyUSB connection to the Roach en monitor it, and try to
>>> upload the fga file, the Roach gives the same error "progremote"
>>>
>>> Thats why I'm co
I get the following error when I run
> the tut3.py script:
>
> ImportError: No mode named spead
>
> Do you perhaps have any ideas on how to solve it?
>
> Thank you!!
>
> Heystek
>
> On Fri, Oct 7, 2016 at 11:01 AM, James Smith wrote:
>
>> Hello Hey
use --upgrade): spead in
> usr/local/lib/python2.7/dist-packages
> cleaning up
>
> Any ideas?
>
> I am a bit lost to be honest.
>
> On Fri, Oct 7, 2016 at 11:09 AM, James Smith wrote:
>
>> Hello Heystek,
>>
>> I vaguely recall installing spead f
ead" instead -- I don't recall
>> ever using it myself, but it appears to be the pip-sanctioned way of
>> removing something.
>>
>> On 10/07/2016 02:24 AM, James Smith wrote:
>>
>> Hello Heystek,
>>
>> Pip is seeing that you've alrea
in using the script with the .bof
> file. I am very new to python but have training in C, C#, Java and Assembly.
>
> I run the script as follows:
> python tut3.py 192.168.33.7
>
>
> On Tue, Oct 11, 2016 at 1:06 PM, James Smith wrote:
>
>> Hello Heystek,
>>
>&g
Hello Heystek,
I'm not sure what you mean by 'live' data. Wesley's mail correctly refers
you to tut 3 which will let you plot your spectrum, but that's somewhat
staggered. Having it display on a continuous basis will take a fair amount
more work and will probably require having a 10 GbE connection
ta from an FM antenna. Wesley suggested
> that I use a snap block. So basically al I need to do is add a snap block
> at the end of the simulation from tut3 that says "evan" and "odd" and plot
> the data that has been captured inside them.
>
> Thank you
>
> Heys
Hello Franco,
If you're only using 1 sample at a time, you needn't use a CASPER FFT, the
Xilinx ones do the trick nicely. You can use an asynchronous 1-input PFB if
you want to as well.
You would probably need to rework your down-stream stuff though.
Regards,
James
On Tue, Apr 4, 2017 at 2:48
Hi Heystek,
I adapted casperfpga to work with ROACH but before you take the following
advice please bear in mind that I haven't updated my working version of it
for some time: I'm on commit 475ed6826b893230d62da8c7dcdcc2541bea83cf of
the devel branch, Fri Mar 4 17:27:09 2016. Newer versions *shoul
is is done in one step. Unfortunately. But apart from that it works very
well.
On Mon, Apr 24, 2017 at 10:06 AM, James Smith wrote:
> Hi Heystek,
>
> I adapted casperfpga to work with ROACH but before you take the following
> advice please bear in mind that I haven't updated my
Hello Heystek,
The KatADC is described here:
https://casper.berkeley.edu/wiki/KatADC
It's got two channels which you need to enable if you want to use them, and
31.5 dB variable attenuators which you need to set.
So if you want them to be on all the time, just hard-wire some 1s into en0
and en1.
ystek Grobler
wrote:
> Hi James
>
> Thanks for the help!! I had to add software registers to en0 and en1 as
> well but know it compiles.
>
> Thanks for the help!!
>
> I really apreciate it
>
> Heystek
>
> On Mon, May 8, 2017 at 2:23 PM, James Smith wrote:
>
>
Hello Heystek,
If you're not sure on Marc's suggestion -- ssh in and use "df -h" and it
should tell you how much space you have left on the ROACH's filesystems.
Regards,
James
On Mon, May 15, 2017 at 1:48 PM, Marc Welz wrote:
> Long shot - could you have run out of space on the roach ?
>
> On
Hello Heystek,
If you're not getting a spectrum, what are you getting? How have you
connected your katadc? (Both physically and with the yellow block)?
Regards,
James
On Wed, May 17, 2017 at 9:46 AM, Heystek Grobler
wrote:
> Good day everyone
>
> I am trying to implement tutorial 3 on a ROACH
The simulink model is connected as follows:
>
> [image: Inline image 2]
> If I program the ROACH and pull a spectrum of It I get nothing (only a
> straight line through zero) or sometimes I get the most random noise that
> is all over the place.
>
> Heystek
>
>
>
>
>
&g
Hello Heystek,
Yes, a sin-wave (usually called CW or continuous wave signal) is the ideal
thing to do. I use 800 MHz on a ROACH1, though I understand that they can
go a bit higher. Other more experienced users might be able to comment more.
My particular setup is: valon synth inside the ROACH's b
Hello Heystek,
On Thu, May 25, 2017 at 2:50 PM, Heystek Grobler
wrote:
> How does the gain work when pulling a spectrum out of the BRAMS?
You're going to need to be a bit more specific. I'm not too sure what
you're trying to do here.
Regards,
James
--
You received this message because you a
Hello Yunpeng,
Just to echo what Michael and Vereese said - those tools can help you get a
bit more insight into what's going on, and how badly your timing problem
is, but the timing report should tell you how by how much you're missing
timing (should be some nanosecond value).
If it's just a sma
;>
>>
>>
>> ---
>> Yunpeng Men
>> PhD student
>> Department of Astronomy & Kavli Institute for Astronomy and
>> Astrophysics, Peking University
>> Yi He Yuan Lu 5, Hai
Hello Xavier,
Casperfpga is lacking a bit of documentation, but see Jason Manley's email
to the list from yesterday. It's got a bit of a primer, and it works
broadly similarly to Corr but with some added useful time-saving features.
It would be good to get around to writing a user manual for it at
Hello Anshu,
What version of katcp do you have installed? I have seen this issue when
the katcp library isn't up-to-date.
I think you can get this either from pip or directly from github.
Regards,
James
On Fri, Jul 7, 2017 at 7:39 AM, Anshu Singh wrote:
> Hello,
>
> While trying to link the
s[0] == katcp.Message.INVALID:
> 165 raise KatcpRequestInvalid(
>
> KatcpRequestFail: Request status on host 100.100.100.1 failed.
> Request: ?status
> Reply: !status fail program
>
>
>
> What could be the issue?
>
>
> On Fri, Jul 7
Hello Heystek,
Where is your Xilinx library installed? See if you can cd to the directory
that it refers to?
Regards,
James
On Fri, Aug 11, 2017 at 11:17 AM, Heystek Grobler
wrote:
> Hi Ryan
>
> Thanks for your help!
>
> I have added that slash but still get the same error.
>
> I also had to
re to which bin/lin64 matlab is referring because you can find
> them under
>
> /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
>
> and
>
>
> /opt/Xilinx/14.7/ISE_DS/common/bin/lin64
>
> Thanks for the help
>
> Heystek
>
> On Fri, Aug 11, 2017 at 11:18 AM, James Smith
Hello Mugundhan,
Please describe your context a bit more - what libraries are you using?
Please also paste the error that you get? (and perhaps the code you used to
generate the error.)
Regards,
James
On Thu, Oct 12, 2017 at 12:17 PM, Mugundhan vijayaraghavan <
v.vaishnav151...@gmail.com> wrote
gt;> I'm attaching the model files of the first and the second designs, along
>> with the bof and the fga files. I used the ipython terminal for programming
>> the fpga in both cases. The error I obtained is attached in a text file.
>>
>> Hope this helps,
>&
Siddharth,
ROACH1 is quite deprecated now, we don't recommend it for new projects.
There are still a number of them floating around, but no active development
on the libraries to support them.
I don't know of any ADCs with more than 2 inputs. You'd also be quite
pressed to fit a full 16-element c
rting with a smaller version of an
> interferometer, say a 4-element, 250 MHz bandwidth version. Is there any
> chance I might be able to borrow a ROACH1 for about 3 months, if anyone has
> an old board they aren't using anymore?
>
> Thanks,
> Siddharth
>
> On Fri, Oc
Hello Bela,
I second Andrew's suggestion, but note also that "Error due to multiple
causes" can often mean that somewhere in the design there's a name that
Matlab doesn't like. Avoid using any capital letters or spaces in block
names, and avoid using names that are too long - if the full file-path
t;>
>>> On Thu, Jan 18, 2018 at 12:34 PM, James Smith wrote:
>>>
>>>> Hello Bela,
>>>>
>>>> I second Andrew's suggestion, but note also that "Error due to multiple
>>>> causes" can often mean that somewhere in the
xit wrote:
> Hie James,
>
> I have waited around 7 to 9 hours, still I am getting same warnings.
>
> Thanks & Regards,
> Bela
>
>
> On Tue, Jan 30, 2018 at 12:22 PM, James Smith wrote:
>
>> Hello Bela,
>>
>> That looks fine - there are normally
sizing it stuck.
>
>
> Thanks & Regards,
> Bela
>
> Bela Dixit
> Electronics and Telecommunication engg(digital system)
>
>
> On Tue, Jan 30, 2018 at 1:07 PM, James Smith wrote:
>
>> Hello Bela,
>>
>> That is a bit long - what happens if you j
Hello Rolando,
You expect to see a DC bin, i.e. a large value in channel 0, and I have
often seen a large-ish value in bin 1 as well. After that it will drop off.
If you're seeing a peak in something other than 0, there may be something
wrong. Those spikes at the high end of your spectrum look a
Hello Karl,
How many antenna elements do you have? We've had simple two-antenna
interferometers with both F and X on a single ROACH-1. I'm still using one.
There's a tutorial on the wiki doing exactly this.
That being said, ROACH-1's biggest hassle is using CX4 Ethernet plugs,
which are finicky a
Hello Bela,
Depending on how you're reading your binary file on the computer, the
easiest thing to do would probably be to use the ROACH2's 10 GbE networking.
You can then use e.g. a python socket program to send the data to the
ROACH2 in chunks, receive and process it on the FPGA and then use th
ronics and Telecommunication engg(digital system)
>
>
> On Thu, Apr 19, 2018 at 11:42 AM, James Smith wrote:
>
>> Hello Bela,
>>
>> Depending on how you're reading your binary file on the computer, the
>> easiest thing to do would probably be to use the ROACH2&#
Hello Jonathan,
For what it's worth, I used to run CentOS - I forget which version now. It
worked just fine, possibly a little bit better than Ubuntu subsequently
works, but that was subjective and I don't have any hard facts to back that
up.
But when I needed to change computers, and start from
Hello David,
A little late to the party but I thought I'd throw in 2c from our
perspective.
The other thing we usually try to do with ADCs (this was an issue on the
ROACH1s) is to put in a bit of white noise with whatever test signal we
were using (sine wave usually). When you get actual sky, the
Hello Dale,
Do you have any existing, functioning ROACH2 boards? Are they booting from
an SD card or from network? If it's a network card then it's a simple
matter to copy the one to the other, if from network then the most you may
need to do is update your dnsmasq.conf to assign an IP address to
, so I
> will proceed with the old instructions.
>
> Thanks,
> Dale
>
> On Mon, Feb 4, 2019 at 5:37 AM James Smith wrote:
>
>> Hello Dale,
>>
>> Do you have any existing, functioning ROACH2 boards? Are they booting
>> from an SD card or from network? I
Hello Indrajit,
Why were you not able to interrupt the process? Connect to the ROACH via
the serial port then reset it - you should be able then to see the place to
interrupt and set netboot (or whatever else you need) quite easily.
Regards,
James
On Wed, Feb 13, 2019 at 1:31 PM indrajit wrote
from 10 and I am trying to interrupt but the
> keystrokes are not interrupting the boot menu.
>
> Even I changed the SD card which is logically nothing to do with the
> booting sequence.
>
> Thanks and regards
>
> Indrajit
>
>
>
> On Wednesday 13 February 2019
Hello Franco,
As I understand it, PTP wasn't terribly useful in our application (though I
wasn't involved with this directly). You can probably sync the little Linux
instance that runs on the ROACH2, but getting the time information onto
your FPGA may prove somewhat tricky.
Are you using an ADC c
0:50, Franco wrote:
>
>> Hi James,
>>
>> Thank you for your answer. Yes, I use and ADC for data acquisition. I
>> understand the general idea of your system. What I don't understand is
>> where you get the start time of the ROACH2. Is generated by the TRF? Is
>&
We use this tag in our repo for supporting ROACH1:
https://github.com/ska-sa/casperfpga/releases/tag/AVN_legacy
Note that you can't use upload_to_ram_and_program. It's a three-step
process.
fpga.system_info['program_filename'] = '%s.bof' % gateware #bof needs to be
on the roachfs for this to work
Zhang,
If your logic is small enough and both designs can fit onto the ROACH2, you
can combine them in Simulink and compile a new bof (or fpg) file and use
this instead.
Regards,
James
On Thu, Jul 11, 2019 at 2:16 PM Jack Hickish wrote:
> Hi Zhang,
>
> Alas, that is impossible!
>
> Cheers
> J
Hello Gonzalo,
Your Casperfpga version seems to be a bit too recent - I stand under
correction here but later versions might have broken backwards
compatibility with ROACH2.
Try checking out v0.4.3 or one of the other slightly older releases in your
casperfpga repo and reinstalling:
cd /path/to/
on your machine/server via the command below.
> >> - sudo rm -r
> /usr/local/lib/python2.7/dist-packages/casperfpga-.egg
> >> - You should also check if there are any other items laying around in
> the /dist-packages/ folder from this casperfpga install
> >>
> >
Thanks for a well-thought-out response, Jack. Just to add my 2c -
Depending on your install, there's sometimes a firewall which blocks
high-range UDP ports which we typically use by default. So if you can see
packets coming in with Wireshark / tcpdump, but for some reason your Python
sockets are h
Hello Sebastian,
Here's a snippet from one of our internal guides on how to set a ROACH1 up.
Check that you've got the baud rate set correctly, if you get absolutely
nothing on the serial port. You do need to configure the ROACH to boot from
the NFS.
If you get nothing on the serial port though,
Hello Kristen,
You're using rather out-of-date software there...
Could you try using casperfpga instead of corr, and upgrade your katcp to
at least version 0.6.2? (Do it in a virtual environment if you don't want
to clobber your install).
I use this particular casperfpga commit on ROACH2, but I
Hello Molly,
We have done something broadly similar using ROACH2 and katADC, but only
1024 channels:
https://github.com/ska-sa/AVNRoachGateware/tree/master/WideBandSpectrometer
What frequency are you looking at? The only thing I'm thinking is that you
might struggle to get the design to meet timi
Just to add to what Jason has said, older 100 Mbps switches are easy enough
to pick up secondhand on eBay and such, depending on where you are. They're
quite cheap.
On Fri, Apr 17, 2020 at 3:19 PM Jason Manley wrote:
>
> > Since we are running the ancient Debian Etch on this unit, I have no
> ac
~# mii-tool -F 100baseTx-HD eth0
> root@roach:~# mii-tool eth0
> eth0: 100 Mbit, half duplex, link ok
>
> And similar command on a server with spare eth3 (connected to the ROACH in
> question).
>
> Cheers,
> Ramesh
>
>
>
>
> On 17. Apr 2020, at 15:41, James Smith
Hello Heystek,
You can probably use a "to workspace" sink, then you'll be able to display
the data however you want in some matlab code once the simulation is
finished running.
Canonically, just applying an FFT to frequency-domain data will get you
back into the time domain, multiplied by some sc
ipt, the the FFT of an FFT
> gives me a time domain signal, but the result has a larges amplitude. When
> I do a 3rd FFT I get the frequency domain again, and it is also amplified.
>
> It is just something that I picked up.
>
> Heystek
>
> On 23 Apr 2020, at 11:51, James Smith
asperfpga is only supported with python 2.x
for now. We have been working on porting this to python3. I know
at SARAO we have a python3 compatible version, but I haven't
tested it fully yet.
You are welcome to try and let me/James Smith know:
https://github.com/ska-sa/ca
Hello Heystek,
Somewhere in your design, you are trying to use a Xilinx block as an input.
Replace it with one of the yellow blocks from the Casper tools, and you
should be okay. (Usually this will be a software register or a BRAM block.)
Regards,
James
On Tue, Aug 11, 2020 at 12:54 PM Heystek
ther use something else for the design?
>
> On 11 Aug 2020, at 15:03, James Smith wrote:
>
> Hello Heystek,
>
> Somewhere in your design, you are trying to use a Xilinx block as an
> input. Replace it with one of the yellow blocks from the Casper tools, and
> you should be oka
Hi Heystek,
Unfortunately not - I have had this in the past as well IIRC, some of the
more modern Linux distributions will give you something like "en0s1" or the
like. Matlab is stuck in the past, looking for eth0.
It's easy enough to change the name, but bear in mind that you may have
some funni
Hello Nitish,
So I'm going to play devil's advocate and say that while you could do the
byte swapping in the FPGA, it would be morally wrong ;-)
Ideally, all data that goes out on a network will be network order, and you
use the ntohl or htohs functions to get it in host format. That way the
code
ank you.
>
> Cheers,
> Dave
>
> On Aug 18, 2020, at 07:21, James Smith wrote:
>
>
> Hello Nitish,
>
> So I'm going to play devil's advocate and say that while you could do the
> byte swapping in the FPGA, it would be morally wrong ;-)
>
> Idea
Hello Heystek,
You will have to go through the timing reports and see which signal path is
failing timing, and by how much.
Once you have an idea, you will need to sprinkle delay blocks and / or
adjust latencies in your logic to get to a point where the place-and-route
can find a layout that sati
Hello Colm,
Yes, you're correct. That's how some of our narrowband designs work - you
use each PFB channel as a very narrow bandpass filter, and treat its output
as a complex time-series. So you can pass it through another PFB to get a
higher-resolution spectrum, at the expense of very much lower
Hello Idir,
It's been a while since I've played around with this, but it looks as
though you've chosen some fairly strange settings there.
We don't usually manipulate the settings in the Xilinx Sysgen block
directly - it's usually done through one of the CASPER yellow blocks -
depending on what F
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