[USRP-users] Re: Quick question about tuning USRP B210 for sweep spectrum

Something to note regarding the TwinRX is that changing frequency on one channel has an effect on the other channel of the same card. I ran into this a few years ago and never found a resolution. My goal was to sweep with one channel and stare with the other. The staring channel had too many

[USRP-users] Re: [RFNoC] "Could not find block with Noc-ID" even with LD_PRELOAD

On Thu, Mar 7, 2024 at 1:39 PM Xianglong Wang wrote: > Hi all, > > > I have created my OOT module with the temple located in uhd/host/examples. > However, I cannot find my OOT module in my usrp with > > > [WARNING] [RFNOC::BLOCK_FACTORY] Could not find block with Noc-ID 0x2d024, > 0x > >

[USRP-users] Re: Getting started with RFNoc block (adding an additional RFnoc block )

On Thu, Feb 22, 2024 at 3:02 PM wrote: > CRITICAL WARNING: [Route 35-39] The design did not meet timing > requirements. Please run report_timing_summary for detailed reports. > > [01:09:55] Current task: Routing +++ Current Phase: 22 Post Router Timing > > [01:09:55] Current task: Routing +++

Re: Python 3.12 - No module named 'gnuradio' or 'pmt'

On Tue, Feb 13, 2024 at 3:27 PM Elmore Family wrote: > I just installed Python 3.12 and I got the subject error when running a > script that has been successful under 3.9.2. > > What is happening? > Check your PYTHONPATH versus where gnuradio is installed. Brian >

[USRP-users] Re: Adding existing RFNOC blocks in GNU Radio GUI

On Tue, Feb 13, 2024 at 3:10 AM Dario Pennisi wrote: > Hi Brian, > thanks for the clarification, however, if i'm not mistaken, the commit you > mention is on main and that should be in gnuradio 3.10, whereas if you > stick with 3.8 that will still require gr-ettus, as also stated in here: >

[USRP-users] Re: Adding existing RFNOC blocks in GNU Radio GUI

On Mon, Feb 12, 2024 at 4:13 PM Dario Pennisi wrote: > Hi Brian, > The issue with not using gr-ettus is the lack of rfnocmodtool which is > very handy. Also, it is my understanding that unless you move to gnuradio > 3.10 even with uhd4.6 you still need gr-ettus. Am I wrong? > You're right that

[USRP-users] Re: Adding existing RFNOC blocks in GNU Radio GUI

On Mon, Feb 12, 2024 at 2:30 PM Chris wrote: > Do you recommend updating my Ubuntu to 22.04? > I use Ubuntu 22.04 and compile GNU Radio and UHD from source. I typically install it to a non-system directory (i.e. /opt or ~/opt) and add the PATH, LD_LIBRARY_PATH, and PYTHONPATH in my

[USRP-users] Re: Adding existing RFNOC blocks in GNU Radio GUI

On Mon, Feb 12, 2024 at 2:15 PM Dario Pennisi wrote: > You have to install gr-ettus which contains what's needed for compiling > OOT blocks and also installs rfnock blocks > My recommendation is to not start here and to start with newer software. Use the latest UHD and the latest GNU radio.

[USRP-users] Re: RFNOC Tutorial

On Sat, Feb 10, 2024 at 2:47 PM Chris wrote: > All, I am trying to offload some of my processing power onto my X310's > FPGA. I have the environment set up but still find myself confused on how > to build the out of tree block. I was able to add a block and I'm not sure > what to do next? > > >

Re: RFNOC tutorial

On Sat, Feb 10, 2024 at 2:14 PM Chris wrote: > All, I am trying to offload some of my processing power onto my X310's > FPGA. I have the environment set up but still find myself confused on how > to build the out of tree block. I was able to add a block and I'm not sure > what to do next? > > >

[USRP-users] Re: Pulse distortion of N320

On Fri, Sep 1, 2023 at 8:58 AM wrote: > I have an N320 that I am using. Currently UHD 4.4 is installed. When I > send a pulsed signal and choose the pulse amplitude between 0.9 and 1, the > beginning and end of the pulses are distorted with the same pattern. > This is most likely due to the

[USRP-users] Re: UHD4 segmentation fault on creating rx_streamer

On Tue, Aug 22, 2023 at 4:16 PM Andrew Fountain via USRP-users < usrp-users@lists.ettus.com> wrote: > Here is the output of that program with a debug build of UHD v4.4.0.0 . It > seems to point out this line > https://github.com/EttusResearch/uhd/blob/UHD-4.4/host/lib/rfnoc/rfnoc_graph.cpp#L393 >

[USRP-users] Re: How to have 10MHz on REF OUT with a master clock of 184.32 MHz

On Fri, Aug 4, 2023 at 3:52 AM wrote: > Dear all, > > I plan to use 2 USPRs to analyze LTE signal. One will use a GPSDO to have > a good clock and time reference. To have synchronization between them, the > second one will be set on external synchronization (ref out -> ref in, for > 10 MHz and

[USRP-users] Re: How to have 10MHz on REF OUT with a master clock of 184.32 MHz

On Thu, Aug 3, 2023 at 4:24 AM EVAN LAURANS wrote: > Hi all, > > I use the USRP X310 to analyze signal and i use the 10 MHz REF OUT for an > external device. I noticed that’s the REF OUT hasn’t a frequency of 10 MHz > when i am using a 184.32 MHz master clock rate but about 9.96 MHz, whereas >

[USRP-users] Re: how to run multiple jobs in rfnoc image build for usrp with xilinx....

On Tue, Aug 1, 2023 at 4:20 AM sp wrote: > in xilinx vivado and ise design suite in gui project when i want to build > project there is a option that we can select number of jobs for builds > how can we set number of job for building rfnoc blocks and image of usrp > > for building we use

Re: status of RFNoC Fosphor and build recommendations

On Thu, Jul 27, 2023 at 8:40 PM Clint Scarborough < clinton.scarboro...@gmail.com> wrote: > I'm trying to run GNURadio with the RFNoC Fosphor block. I first tried > building UHD 4.4 and GNURadio 3.10 or 3.11. I had read the Readme for > gr-ettus that said for GR3.10 to just use gr-uhd directly.

[USRP-users] Re: rfnoc_image_builder

n 29, 2023 at 2:41 PM Brian Padalino > wrote: > >> UHD seems to want to install to local/lib/python3.10-dist-packages/uhd - >> do you have that as part of your installation? >> >> I have an imgbuilder directory and image_builder.py inside there. >> >> Y

[USRP-users] Re: rfnoc_image_builder

UHD seems to want to install to local/lib/python3.10-dist-packages/uhd - do you have that as part of your installation? I have an imgbuilder directory and image_builder.py inside there. You have an issue with, specifically, from uhd.imgbuilder import image_builder? Brian On Thu, Jun 29, 2023

[USRP-users] Re: N320 - GPIO ATR output to TX output delay

On Tue, May 30, 2023 at 5:32 PM Mena Ghebranious wrote: > I apologize, I think I must be missing something. This is the filter > (Xilinx IP) I see implemented in the N320 master code: > > > https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v#L3431 > This HBF

[USRP-users] Re: N320 - GPIO ATR output to TX output delay

On Tue, May 30, 2023 at 4:42 PM Mena Ghebranious wrote: > I don't see any bypass logic in the FPGA code, but in any case, the N320 > only supports three master clock rates, none of which is our desired > sampling rate: > >

[USRP-users] Re: N320 - GPIO ATR output to TX output delay

On Tue, May 30, 2023 at 2:27 PM Mena Ghebranious wrote: > Yes, bypassing the DUC was discussed among our team, but as far as I can > tell, there is no way to configure the bypass via the UHD/USRP API - it > would require an FPGA mod. > If you set the input rate to the radio to be the master

[USRP-users] Re: N320 - GPIO ATR output to TX output delay

On Tue, May 30, 2023 at 11:15 AM Mena Ghebranious wrote: > If possible, I'd like to hear what the R team thinks - I have worked > with designs in the past where the TX timing lines up and there are no > samples cut off. > > On Tue, May 30, 2023 at 8:08 AM Marcus D. Leech > wrote: > >> On

[USRP-users] Re: RFNOC Block Not found

Mistype: uhd_usrp_probe --interactive-reg-iface 0/Block#0 ... also assuming 0/Block#0 and 0/Block#1 are the same and your own custom blocks. Unsure if this assumption is correct. Brian On Wed, May 3, 2023 at 4:21 PM Brian Padalino wrote: > Try doing: > > uhd_usrp_probe --intera

[USRP-users] Re: RFNOC Block Not found

Try doing: uhd_usrp_probe --interactive-ref-iface 0/Block#0 And inside there, try: peek32 0 What does it print out? Does it match your NOC_ID in your controller? Brian On Wed, May 3, 2023 at 4:03 PM wrote: > This is the output of uhd_usrp_probe > > > / > > | Device: N300-Series Device

[USRP-users] Re: RFNOC Block Not found

On Wed, May 3, 2023 at 2:07 PM wrote: > Hello, > > > I currently have a custom RFNOC module. When I try to initialize my block > however, I am unable to find it. I get an error that seems to match up with > the block id I set on my module, but it still seems that it cannot be > found. This is

[USRP-users] Re: Tail of every transmit trimmed

On Tue, May 2, 2023 at 3:25 PM wrote: > Try interpolating on the host to 200 Msps and see how things go. > > I’m not sure what you are suggesting. If I take the “bad” recorded file > and I interpolate from 25 to 200 Msps, it’s not going to make chopped tail > the appropriate width. > > I also

[USRP-users] Re: Tail of every transmit trimmed

On Tue, May 2, 2023 at 2:04 PM wrote: > What is the sample rate of your transmitted samples? If it isn't 200 Msps > for the X310, then you are using the DUC. > > I use a couple different sample rates. The plots I showed earlier were > taken at 25 MSPs. > Try interpolating on the host to 200

[USRP-users] Re: Tail of every transmit trimmed

On Tue, May 2, 2023 at 1:30 PM wrote: > Are you using any interpolation or is it going directly to the TX DAC? > > I’m using a base UHD FPGA image at the moment. I tune the frequency > directly using the analog LO. The DSP component of the tune request is set > to 0. Is there some other setting

[USRP-users] Re: Tail of every transmit trimmed

On Tue, May 2, 2023 at 1:01 PM wrote: > Hello, > > I have a C++ application I developed using x310s running on RHEL9 and UHD > 4.2 currently. I’ve noticed recently that the final ~25 samples of every > transmit are heavily distorted or nonexistent. I am able to replicate this > behavior using a

[USRP-users] Re: Split USRP (X310, N231) between two PCs

On Thu, Apr 27, 2023 at 1:47 PM Eugene Grayver wrote: > The hard part with raw UDP for samples is the flow control for the TX. > Flow control latency is very tight at 200 Msps. Not saying it can't be > done, but having 'native' support in the UHD would be better. I have fair > understanding of

[USRP-users] Re: Split USRP (X310, N231) between two PCs

On Wed, Apr 26, 2023 at 6:33 PM Eugene Grayver wrote: > How much would work would it take to allow two different PCs to each > control one of the channels on the X310? Would the work be mostly on the > host (software) side, or will some FPGA work be required? There is no > issue on the RX

[USRP-users] Re: Overflow using Keep One In N block

The X4_400 image has no decimation inline. That means that the block needs to be able to handle 491.52 or 500 Msps coming into it. That means more than 1 sample per clock being fed into the block. If you don't handle more than 1 sample per clock going into the block, then you will get overflows

[USRP-users] Re: X410 Overflow with Custom FPGA

On Wed, Mar 22, 2023 at 10:40 PM Wade Fife wrote: > Hi Brian, > > Unfortunately, the DSP inside the current RFNoC DDC block processes one > sample per clock cycle. So the maximum sample rate through the DDC is the > same as the rate of the clock you provide to the ce clock input. With the > 400

[USRP-users] X410 Overflow with Custom FPGA

I've built up a custom FPGA based on the 400 MHz image, and I have a bit of an asymmetric scenario going on here. The TX side of things has a custom block and it feeds the TX port at 491.52 MHz. The RX side I only need to receive at 30.72 Msps, so I instantiate a 2-channel DDC and connect it

[USRP-users] Re: Wideband IQ Daughterboard

for IQ. > > > > Eugene Grayver, Ph.D. > Aerospace Corp., Principal Engineer > Tel: 310.336.1274 > > > -- > *From:* Brian Padalino > *Sent:* Tuesday, March 21, 2023 3:18 PM > *To:* Eugene Grayver

[USRP-users] Re: Wideband IQ Daughterboard

On Tue, Mar 21, 2023 at 6:12 PM Eugene Grayver wrote: > Hello, > > I want to use an external IQ mixer with an external LO. My signal is 160 > MHz wide, which fits nicely into the nominal complex 200 MHz Nyquist of the > X310. Unfortunately the only daughterboards for direct access to the ADCs

[USRP-users] Re: RFNOC module sending back (or receiving) data in the wrong order

I've made some custom converters in the past for RFNoC devices. This page is supposed to be useful: https://files.ettus.com/manual/page_converters.html Attached is the relevant code to make a simple converter. Note it isn't performant, but it gets the job done. In my main(), I then call

[USRP-users] Re: [EXTERNAL]Re: What do I need to do to make uhd_usrp_probe see my custom RFNOC module?

On Fri, Mar 3, 2023 at 10:14 AM Kevin Williams wrote: > Hi Guys, > > > > Answering my own question also. > > > > I had a mismatch in the NOC_ID between the driver code and my firmware > block. > > > > After fixing that I could get uhd_usrp_probe and others, like gnuradio, to > recognize my

[USRP-users] Re: What do I need to do to make uhd_usrp_probe see my custom RFNOC module?

On Wed, Mar 1, 2023 at 8:59 AM Gwenhael Goavec-Merou wrote: > On Wed, 1 Mar 2023 07:20:22 -0500 > Brian Padalino wrote: > > > On Wed, Mar 1, 2023 at 5:40 AM Vermeulen, Bas (Consultant) via > USRP-users < > > usrp-users@lists.ettus.com> wrote: > >

[USRP-users] Re: What do I need to do to make uhd_usrp_probe see my custom RFNOC module?

On Wed, Mar 1, 2023 at 5:40 AM Vermeulen, Bas (Consultant) via USRP-users < usrp-users@lists.ettus.com> wrote: > Just to answer my own question: > > Run uhd_usrp_probe with LD_PRELOAD=/usr/lib/librfnoc-module.so > uhd_usrp_probe and it will be able to find the RFNOC modules. > The same for any

[USRP-users] X410 and RFNoC Clock Domains

I am trying to figure out the right way to use the clocks in RFNoC and the clock domains. Referencing here: https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0#Example:_Adding_an_FFT_Block The tutorial says the X3XX has a `ce` clock of 214. 286 MHz, a `rfnoc_chdr` clock of 200 MHz, and

[USRP-users] Re: Running "make xsim"

On Tue, Jan 17, 2023 at 5:53 PM wrote: > Hello, > > I am currently following the instructions listed at this link: > https://files.ettus.com/manual/md_usrp3_sim_running_testbenches.html > > I am currently having trouble making the testbench for the N321. I have > been able to successfully build

[USRP-users] Re: Starting FPGA development on Ettus N321

On Tue, Jan 17, 2023 at 11:04 AM wrote: > I have the vivado project saved now, thanks for your help! > Glad it worked out for you. For the simulator files, I am a bit lost as to how it should be created? > > I am following these instructions to build the simulator files >

[USRP-users] Re: Starting FPGA development on Ettus N321

Glad it worked out. It builds an in memory project only I believe. You can load up the GUI by adding GUI=1 to the make command. From there, you can save off the project if you like. You can also only check syntax with CHECK=1. Check the bottom of the Makefile for some other supported command

[USRP-users] Re: Starting FPGA development on Ettus N321

Your git output says there are local modifications and then you describe them but say it's all clean. Strange? Anyway, yes - you need to install a patch from Xilinx. Follow this: https://support.xilinx.com/s/article/76780?language=en_US Download the ZIP file linked there and follow the

[USRP-users] Re: Starting FPGA development on Ettus N321

Vivado locks IP if it's been targeted for the wrong device, or generated with the wrong version of the software. Did you receive any warnings about the wrong version of Vivado being used? Are you running in a clean UHD repo (git status shows no changes)? I've run into this issue when things were

[USRP-users] Re: Starting FPGA development on Ettus N321

I am assuming you also sourced setupenv.sh in the n3xx directory? If you remove the n3xx/build-ip/xc7z100ffg900-2/hb47_1to2 directory and try again, does it still fail? Brian On Thu, Jan 12, 2023 at 6:35 PM wrote: > Hello, > > > I am trying to create a Vivado environment for the ettus 321,

[USRP-users] X410 Temporary FPGA Loading

I am building some experimental/development FPGAs for an X410 and I am looking at loading them temporarily for a quick runtime test without committing to overwriting default images. With the X310 I am able to achieve this with a JTAG connection. With the X410, being an SoC, I think this would be

[USRP-users] Re: RFNoC 4.0 Generated NoC Shell

On Fri, Jan 6, 2023 at 2:56 PM Rob Kossler wrote: > On Fri, Jan 6, 2023 at 2:09 PM Brian Padalino wrote: > > > > On Fri, Jan 6, 2023 at 1:11 PM Rob Kossler wrote: > >> > >> On Thu, Jan 5, 2023 at 7:46 PM Brian Padalino > wrote: > >> >

[USRP-users] Re: RFNoC 4.0 Generated NoC Shell

On Fri, Jan 6, 2023 at 1:11 PM Rob Kossler wrote: > On Thu, Jan 5, 2023 at 7:46 PM Brian Padalino wrote: > > Before RFNoC 4.0, there was a generic NoC shell that was used instead of > one being generated for each of the blocks. > > > > I see there is a noc_shell_ge

[USRP-users] Re: RfNoc Equivalent of get/set_master_clock_rate

On Fri, Jan 6, 2023 at 3:20 AM Maximilian Matthé < maximilian.mat...@barkhauseninstitut.org> wrote: > Hello, > > the multi_usrp class has methods get_master_clock_rate, > set_master_clock_rate and get_master_clock_rate_range, see > >

[USRP-users] RFNoC 4.0 Generated NoC Shell

Before RFNoC 4.0, there was a generic NoC shell that was used instead of one being generated for each of the blocks. I see there is a noc_shell_generic_ctrlport_pyld_chdr, but it isn't used anywhere. Is there a reason that a generic one isn't utilized and that ones are being generated

[USRP-users] RFNoC OOT Xilinx IP not XCI Based

I really don't like using XCI files for IP projects since Vivado wants to target them specifically for a single device and a single version of Vivado. Instead, I like being able to define the IP in a tcl script. With that being said, is there a way to tell rfnoc_image_builder to source some set

[USRP-users] RFNoC Block Controller with Fractional Sample Rates

I am building some blocks that have some fractional rates for filtering, and I am trying to make sure I convey the fractional rates correctly on the controller block side. I am looking at the ddc_block_control.cpp as an example, but it has a few different functions: - get/set_input_rate -

[USRP-users] X410 Sample Rate

I understand Ettus will only support certain sample rates, and I am on my own if I experience issues after changing them. With that being said, I am looking at the X410 sampling and from my understanding it looks like the sample rates are fixed at 2949.12 MHz and generated externally. I don't

[USRP-users] Re: TwinRX Channel Isolation

Hey Wan, On Thu, Oct 27, 2022 at 10:53 PM Wan Liu wrote: > Hello Brian, > > I set up my HW and SW, but I'm having some trouble reproducing after some > initial playing around with UHD examples and gnuradio. I assume you have > some UHD program that records RX to file and while you repeated make

[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?

On Mon, Nov 7, 2022 at 6:29 PM Marcus Müller wrote: > Hi sp, > > That sounds like a bad idea. How are you planning to synchronize access to > that register? > > Generally, in almost *any* context, avoid global state. That makes things > complicated and > error prone; this is true for python as

[USRP-users] Re: TwinRX Channel Isolation

the "mute till lock detect" feature of the ADF5356 and ADF4351 PLLs. I modified gen_adf5356_regs.py and gen_adf4351_regs.py to default it to be on, and the ld_cyc_count to be the longest possible. Brian On Wed, Oct 26, 2022 at 9:38 AM Brian Padalino wrote: > Hey Wan, > > On Tue,

[USRP-users] Re: TwinRX Channel Isolation

Hey Wan, On Tue, Oct 25, 2022 at 10:53 PM Wan Liu wrote: > Hello Brian, > > Thank you for the additional information. > > Regarding #6, I meant that if you have two TwinRX daughterboards, see if > you get this problem when the fixed channel is on one daughterboard, and > the tuned channel is

[USRP-users] Re: TwinRX Channel Isolation

Hey Wan, Thanks for the quick response. On Tue, Oct 25, 2022 at 7:59 PM Wan Liu wrote: > Hello Brian, > > I'll see if I can reproduce with my TwinRX. Please provide some more > information to help me reproduce... > > 1. Center Frequency of fixed channel 0 > I tested at 915 MHz, but also 400

[USRP-users] TwinRX Channel Isolation

I have an application where I am using both channels of the TwinRX without using LO sharing. I am using channel 0 as a single frequency channel, and I am using channel 1 to tune to different frequencies. I am noticing that some transients happen on channel 0 - the fixed frequency channel - as I

[USRP-users] Re: Reset Timing Violation

On Tue, Sep 27, 2022 at 7:21 AM wrote: > Hi every one! > > > I am facing some problems with reset timing violations. This is is one for > example, and i have a fews. I tried to instantiate the reset signal but it > didn work. I don know how to fix it. On the other side, i have seen a reset >

[USRP-users] Re: tracing an overflow error

2022, 17:49 +0200, Brian Padalino , wrote: > > I believe the AXI spec says that data should be presented when valid, and > the tready signal just accepts that data. You can't rely on tready to be > asserted before asserting tvalid. > > With that being said, I have no idea if thi

[USRP-users] Re: tracing an overflow error

I believe the AXI spec says that data should be presented when valid, and the tready signal just accepts that data. You can't rely on tready to be asserted before asserting tvalid. With that being said, I have no idea if this is the source of any of your issues. Brian On Wed, Sep 14, 2022 at

Re: How can I split a periodic signal?

On Thu, Aug 25, 2022 at 1:55 PM James Wanga wrote: > I'm receiving a phase modulated signal representing a periodic pulsed byte > that looks something like this: > > > -|-|||--||-|||---|---|- > > I'm trying to understand how I might split

[USRP-users] Re: DDC and DUC timed command queue depth

On Tue, May 31, 2022 at 3:42 PM wrote: > Hi, > > I’m playing around with frequency hopping on a USRP x310 with a UBX 160 > daughterboard. In particular, I want to hop to a few different frequencies > that are integer multiples of my master clock rate and well within the > daughtercard bandwidth

[USRP-users] Re: X300 DDC - Filter Taps

On Thu, May 26, 2022 at 10:43 AM wrote: > Hi all! > > > I am starting to look through some of the FPGA code of the USRP X300 in > order to understand which is the DDC chain configuration in the default > image. > > > I have understood that in the DDC chain there is 1 CIC filter + 3 Halfband >

[USRP-users] Re: b200 mini LVDS Vs CMOS

On Wed, May 18, 2022 at 4:20 PM Marcus D. Leech wrote: > On 2022-05-18 15:42, ahamza1...@gmail.com wrote: > > > > Hi, > > > > > > I have b200 mini and by reading registers I figured out that it is > > using CMOS for digital interface between ad9361 and BBP. > > > > Is there a way to make it use

[USRP-users] Re: RFNoC DDC or DUC frequency change

On Wed, May 11, 2022 at 2:18 PM Marcus D. Leech wrote: > On 2022-05-11 14:10, rbl...@swri.org wrote: > > > > A question for anyone: when changing the frequency of a DUC (or DDC) > > would you expect the output of the block to be phase continuous > > through the change? Phase-continuous behavior

[USRP-users] Re: data corruption problems with high speed dual channel capturing on USRP E320 over 10 gbit ethernet

rrent design of the FPGA > interface doesn't. > > Wade > > On Thu, May 5, 2022 at 12:28 PM Brian Padalino > wrote: > >> On Thu, May 5, 2022 at 11:45 AM Wade Fife wrote: >> >>> It's a limitation of the FPGA interface to the RFIC. It doesn't support >>>

[USRP-users] Re: data corruption problems with high speed dual channel capturing on USRP E320 over 10 gbit ethernet

On Thu, May 5, 2022 at 11:45 AM Wade Fife wrote: > It's a limitation of the FPGA interface to the RFIC. It doesn't support > the tight setup/hold requirements for operation at the higher clock clock > rate required for 2 x 61.44 Msps. > > Wade > This sounds wrong to me unless you have some very

Re: Problem using volk_32fc_s32fc_multiply_32fc function with vector params

On Mon, May 2, 2022 at 11:26 PM George Edwards wrote: > Hello GNURadio Community, > > I am having a problem using the above function with vector parameters. If > I use an array say: > gr_complex my_val[240]; > volk_32fc_s32fc_multiply_32fc(my_val, my_val, scale, 240); > > It works! But if I

[USRP-users] Re: Default CHDR_W is 64 for a RFNOC blocks, How can increased samples buffer in RFNOC block to 4096...

On Mon, Mar 21, 2022 at 10:42 AM sp h wrote: > > But I need to add samples to a buffer. when 4096 sample is received for > block, do an operation like correlate and convolution, and so on. > > Can we use RAM in an RFNOC block that enables us to work with specific > count samples?? > It is

[USRP-users] Re: Question about external refclk into N320

On Fri, Feb 25, 2022 at 10:22 AM Marcus D. Leech wrote: > On 2022-02-25 10:17, David Raeman wrote: > > Hi all, I’d like to provide an external 10MHz sinusoidal clock to an > N320. The clock signal level is below the 10dBm max spec for this radio, > however it’s a bipolar sinewave (1.8Vpp,

[USRP-users] Re: Overflows "O" messages with USRP X300

On Wed, Feb 23, 2022 at 2:04 PM Brian Padalino wrote: > On Wed, Feb 23, 2022 at 1:03 PM Marcus D. Leech > wrote: > >> On 2022-02-23 12:00, zlika_...@hotmail.com wrote: >> > >> > Thanks for your answer. >> > >> > I tried to use benchmark_rat

[USRP-users] Re: Overflows "O" messages with USRP X300

On Wed, Feb 23, 2022 at 1:03 PM Marcus D. Leech wrote: > On 2022-02-23 12:00, zlika_...@hotmail.com wrote: > > > > Thanks for your answer. > > > > I tried to use benchmark_rate, and I don’t have any sample loss at > > 200MS/s. > > > > On GnuRadio with a very simple flowgraph (USRP Source -> Null

[USRP-users] Re: Could not find block with Noc-ID ...

On Fri, Feb 11, 2022 at 10:14 AM Lautaro Lorenzen < lorenzen.laut...@gmail.com> wrote: > Thanks for your prompt response (and to Rob for his response). > > You are right, my mistake, it is a warning. Besides its nature, it > prevents the gnu-radio flowgraph from working at all, and prevents >

[USRP-users] Re: Could not find block with Noc-ID ...

On Fri, Feb 11, 2022 at 8:16 AM Lautaro Lorenzen wrote: > Hi everyone, > > I'm trying to follow the RFNoC 4 workshop and I've come up with an error > when I'm trying to load the image to an ettus 312. I think my environment > is set up correctly but any help would be appreciated. > It is worth

[USRP-users] Re: [EXT] Re: RFNOC block name?

-as-needed in the target_link_libraries of > CMakeLists.txt did not resolve the issue either. > > > > Jeff > > > > *From:* Jeffrey P Long > *Sent:* Friday, May 14, 2021 5:30 PM > *To:* Brian Padalino > *Cc:* usrp-users@lists.ettus.com > *Subject:* [USRP-users] Re: [EXT

[USRP-users] Re: Too Many Samples in a Single Burst

On Tue, Aug 10, 2021 at 10:37 AM Marcus D. Leech wrote: > On 08/10/2021 12:01 AM, Brian Padalino wrote: > > On Mon, Aug 9, 2021 at 2:12 PM Jonathan Tobin > wrote: > >> Just as an additional update - I was able to test with UHD 4.1 and there >> is no issue - seems to

[USRP-users] Re: Too Many Samples in a Single Burst

On Tue, Aug 10, 2021 at 9:39 AM Jonathan Tobin wrote: > Hi Brian, > > No - only intention would be to receive for 10 seconds and save data. What > would you suggest? > Modify the program to write out to a file on a high performance drive and receive smaller parts at a time from UHD. Brian >

[USRP-users] Re: Too Many Samples in a Single Burst

On Mon, Aug 9, 2021 at 2:12 PM Jonathan Tobin wrote: > Just as an additional update - I was able to test with UHD 4.1 and there > is no issue - seems to be something with UHD 3.15 then. > Just chiming in here to ensure you understand that your test of receiving 625M samples using that

[USRP-users] Re: X310 RFNoc radio block question

On Mon, Aug 9, 2021 at 2:01 PM Black, Robert wrote: > In my case I could do all the processing that I need to do within a > 25MSample rate data stream, with definitely no need for “oversampling” > beyond what the 25MSamp rate provides. If it were possible to magically > change the initial

[USRP-users] Re: X310 RFNoc radio block question

On Mon, Aug 9, 2021 at 1:21 PM Black, Robert wrote: > Brian yes.- The Radio block is permanently running at a permanent 200 > MSamp rate. > > > > I would actually be useful to be able to change (reduce) the ADC sampling > clock, with appropriate analog anti-aliasing filtering in front of the >

[USRP-users] Re: X310 RFNoc radio block question

On Mon, Aug 9, 2021 at 1:03 PM wrote: > Ettus documentation suggests the radio can be configured for a 25 MS > sampling rate (The master 200M / 8). I’m wondering if it is possible to get > the RFNoc RX *Radio block *to do this without the DDC block. Is that > possible? Entering anything other

[USRP-users] Re: Disable N310's auto dc offset

On Wed, Jun 9, 2021 at 4:36 PM Marcus D Leech wrote: > The Ad9371 front-end chip has dc offset removal always on. The AD9371 API has a call to disable the digital DC offset correction:

[USRP-users] Re: Center frequency drift on USRP B-series even with Octoclock

On Fri, Jun 4, 2021 at 2:21 AM Viktor Erdelyi wrote: > You're right Marcus, 0.9GHz seems to be better indeed (see image). Also > thanks for the input on the B205 PLL. > > May I ask in what way phase noise can affect the signal's frequency? > According to an NI webpage [1], it "deals with very

[USRP-users] Re: [EXT] Re: RFNOC block name?

On Mon, May 17, 2021 at 5:30 PM Jeffrey P Long wrote: > Brian- > > > > OK just tried it and it does resolve the names now. In network mode the > .so is installed in /usr/local/lib so it throws a bunch of errors trying to > load everything else in that directory but when usrp probe does finally >

[USRP-users] Re: [EXT] Re: RFNOC block name?

On Mon, May 17, 2021 at 11:04 AM Jeffrey P Long wrote: > Brian- > > > > I think I am getting closer here. I actually just went back to using > network mode so I could debug my issues without the extra challenge of the > crossdev. That is a real nice thing about the E320. > > > > So I think the

[USRP-users] Re: [EXT] Re: RFNOC block name?

On Sat, May 15, 2021 at 7:17 PM Jeffrey P Long wrote: > Brian- > > > > As a further test I moved the whole OOT module directory over to the > device and cmake/make/install right on the device to see if it had some > special sauce but no luck. > > > > OK maybe this is a real problem that Ettus is

[USRP-users] Re: [EXT] Re: RFNOC block name?

On Fri, May 14, 2021 at 5:48 PM Jeffrey P Long wrote: > Ok I had it up in /usr/lib but I moved it down to the root folder and it > basically gave the same thing with additional errors: > > Kind of look like it is still not finding it. Did I set it wrong? > > > > root@ni-e320-31DCD15:/usr/lib#

[USRP-users] Re: RFNOC block name?

On Fri, May 14, 2021 at 4:22 PM Jeffrey P Long wrote: > I am going through the examples in > > > > Getting Started with RFNoC in UHD 4.0 - Ettus Knowledge Base > > > > > And I thought maybe I had messed something up but I noticed in

[USRP-users] Re: Bare metal development on X310

On Wed, Apr 28, 2021 at 5:38 PM Eugene Grayver wrote: > That's what I was afraid of. Note that I do not need any daughter cards > (just LFTX/LFRX), which reduces the number of configuration items. > My main concern is that I was going to take over the ethernet interface. > I guess I can take

[USRP-users] Re: Bare metal development on X310

On Wed, Apr 28, 2021 at 5:11 PM Eugene Grayver wrote: > Hello, > > I am planning to use an X310 (we have at least 50 of them around  ) for > an all-hdl project. Has anyone used it w/out RFNoC or UHD? How much setup > for on-board components is there? Can I do it w/out the software running >

[USRP-users] Re: RFNOC data_tready on AXI Bus

The producer should always be producing when it can so push tvalid as often as you want. The data is only accepted by the other side by tready. Don't wait for tready to push tvalid. Brian On Tue, Mar 30, 2021 at 5:51 PM Hodges, Jeff via USRP-users < usrp-users@lists.ettus.com> wrote: > On the

Re: [USRP-users] x300 latency over 10GigE

On Wed, Mar 10, 2021 at 12:39 PM Doug Blackburn wrote: > Brian, > > I've seen this using UHD-3.14 and UHD-3.15.LTS. > The DMA FIFO block default size is set here in the source code for UHD-3.15.LTS:

Re: [USRP-users] x300 latency over 10GigE

On Tue, Mar 9, 2021 at 10:03 PM Doug Blackburn via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello -- > > I've got some questions re: latency with the x300 over the 10GigE > interface. > > If I use the latency_test example operating at a rate of 50 MSPS, I have > no issues with a latency

Re: Resampling radio data

On Wed, Feb 17, 2021 at 12:02 PM Marcus Müller wrote: > Hi Brian, > > On 17.02.21 16:55, Brian Padalino wrote: > > On Wed, Feb 17, 2021 at 10:05 AM Marcus Müller muel...@kit.edu>> > > wrote: > > > > Oh, sorry, didn't mean to imply that! FFT interpola

Re: Resampling radio data

On Wed, Feb 17, 2021 at 10:05 AM Marcus Müller wrote: > Oh, sorry, didn't mean to imply that! FFT interpolation might work well > (if you can live > with the sinc sidelobes). > If the bandwidth is already constrained to 20MHz/23MHz, then there would be no sidelobes - correct? > > I do have a

Re: Resampling radio data

On Wed, Feb 17, 2021 at 8:01 AM Marcus Müller wrote: > Rough performance estimate: > > for a 1/10 transition width filter (which is sufficient to keep 20 of 25 > MHz Nyquist), you > need an expertly guesstimated [1] 24-ish taps, so go for 25 taps: that > happens to be > exactly the minimum

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