gem5-users

Messages by Date

2010/11/05 Re: [m5-users] Exiting @ cycle 4529915000 because all cpus halted sheng qiu
2010/11/05 Re: [m5-users] Exiting @ cycle 4529915000 because all cpus halted Ali Saidi
2010/11/05 Re: [m5-users] HELP: regarding : creating private l2 cache for multicore sunitha p
2010/11/05 [m5-users] Exiting @ cycle 4529915000 because all cpus halted sheng qiu
2010/11/04 Re: [m5-users] Simulation error Gabriel Michael Black
2010/11/04 Re: [m5-users] question about using stats Lide Duan
2010/11/04 Re: [m5-users] question about using stats Veydan Wu
2010/11/04 Re: [m5-users] question about using stats Lide Duan
2010/11/04 [m5-users] problems with l2cache in FS mode ziad abuowaimer
2010/11/04 [m5-users] question about using stats Veydan Wu
2010/11/04 Re: [m5-users] Simulation error omar kahwaji
2010/11/04 [m5-users] formula to find ipc in m5 biswabandan panda
2010/11/04 Re: [m5-users] M5 ALPHA_FS mode. Virtual-to-Physical address translation concern Gabe Black
2010/11/04 Re: [m5-users] How to write a configuration script about mutil-core processer! Gabe Black
2010/11/04 [m5-users] How to write a configuration script about mutil-core processer! Gdansk Amir
2010/11/03 Re: [m5-users] HELP: regarding : creating private l2 cache for multicore Lisa Hsu
2010/11/03 Re: [m5-users] How to use a local copy of gcc Gabriel Michael Black
2010/11/03 [m5-users] How to use a local copy of gcc Navid Farazmand
2010/11/03 Re: [m5-users] Hope for m5 API for Configuration a system. Gabriel Michael Black
2010/11/03 Re: [m5-users] Simulation error Gabriel Michael Black
2010/11/03 [m5-users] HELP: regarding : creating private l2 cache for multicore sunitha p
2010/11/03 Re: [m5-users] M5 Simulator Event Queue Ali Saidi
2010/11/03 [m5-users] Hope for m5 API for Configuration a system. Gdansk Amir
2010/11/02 Re: [m5-users] m5-users Digest, Vol 51, Issue 31 : Re: Error Creating a disk image using PTXDIST Omar Kahwwaji
2010/11/02 Re: [m5-users] Simulation error omar kahwaji
2010/11/02 Re: [m5-users] a question about using checkpoint Lide Duan
2010/11/02 Re: [m5-users] Simulation error Gabriel Michael Black
2010/11/02 Re: [m5-users] Simulation error Omar Kahwaji
2010/11/02 Re: [m5-users] Simulation error Omar Kahwaji
2010/11/02 Re: [m5-users] Simulation error Omar Kahwaji
2010/11/02 Re: [m5-users] Question about the "miss latency" in M5 simulation stats file Weixun Wang
2010/11/02 [m5-users] M5 ALPHA_FS mode. Virtual-to-Physical address translation concern reena panda
2010/11/02 Re: [m5-users] Simulation error Steve Reinhardt
2010/11/02 Re: [m5-users] Question about the "miss latency" in M5 simulation stats file Steve Reinhardt
2010/11/02 Re: [m5-users] a question about using checkpoint Lide Duan
2010/11/02 [m5-users] Question about the "miss latency" in M5 simulation stats file Weixun Wang
2010/11/02 Re: [m5-users] a question about using checkpoint Veydan Wu
2010/11/02 [m5-users] How to test simulator? wagner meneguzzi pinto
2010/11/01 Re: [m5-users] Simulation error Omar Kahwwaji
2010/11/01 Re: [m5-users] Simulation error Gabriel Michael Black
2010/11/01 [m5-users] Simulation error Omar Kahwwaji
2010/11/01 Re: [m5-users] HELP NEEDED ... about cache block status Weixun Wang
2010/11/01 Re: [m5-users] Possible cache coherence bug Steve Reinhardt
2010/11/01 [m5-users] Mailing list etiquette Gabe Black
2010/11/01 Re: [m5-users] Parameter of scons Gabe Black
2010/11/01 Re: [m5-users] a question about system call Gabe Black
2010/11/01 Re: [m5-users] Possible cache coherence bug Lesha Jolondz
2010/11/01 Re: [m5-users] a question about using checkpoint Lide Duan
2010/11/01 Re: [m5-users] Possible cache coherence bug Steve Reinhardt
2010/11/01 [m5-users] Possible cache coherence bug Lesha Jolondz
2010/11/01 [m5-users] a question about using checkpoint Veydan Wu
2010/11/01 [m5-users] a question about system call Veydan Wu
2010/11/01 Re: [m5-users] Parameter of scons wagner meneguzzi pinto
2010/10/31 Re: [m5-users] Parameter of scons Gabe Black
2010/10/31 [m5-users] Parameter of scons wagner meneguzzi pinto
2010/10/31 [m5-users] How to test simulator M5? wagner meneguzzi pinto
2010/10/31 Re: [m5-users] h/w locking mechanisms implemented in Ruby for X86 timing model Dibakar Gope
2010/10/31 [m5-users] Testing simulator M5 wagner meneguzzi pinto
2010/10/31 Re: [m5-users] Problems with m5.debug.bin Gabe Black
2010/10/31 Re: [m5-users] O3CPU branch predictor speculation level Ali Saidi
2010/10/31 Re: [m5-users] Problems with m5.debug.bin wagner meneguzzi pinto
2010/10/30 Re: [m5-users] m5threads Malek Musleh
2010/10/30 Re: [m5-users] m5threads Ali Saidi
2010/10/29 Re: [m5-users] Problems with m5.debug.bin Gabe Black
2010/10/29 Re: [m5-users] Running Splash2 in FS mode with multithreading Lide Duan
2010/10/29 Re: [m5-users] Running Splash2 in FS mode with multithreading ziad abuowaimer
2010/10/29 [m5-users] M5, sunitha p has invited you to open a Gmail account sunitha p
2010/10/29 [m5-users] cache partitioning sunitha p
2010/10/29 Re: [m5-users] Running Splash2 in FS mode with multithreading Lide Duan
2010/10/29 [m5-users] Running Splash2 in FS mode with multithreading ziad abuowaimer
2010/10/29 [m5-users] Problems with m5.debug.bin wagner meneguzzi pinto
2010/10/28 [m5-users] m5threads IC
2010/10/28 [m5-users] O3CPU branch predictor speculation level Glenn Ko
2010/10/26 Re: [m5-users] h/w locking mechanisms implemented in Ruby for X86 timing model Gabe Black
2010/10/26 [m5-users] Alpha cross-compiler fails to compile 483.xalancbmk zhanglunkai
2010/10/26 [m5-users] h/w locking mechanisms implemented in Ruby for X86 timing model dibakar gope
2010/10/26 [m5-users] DRAMSim integration with m5 Omar Kahwaji
2010/10/26 Re: [m5-users] about dramsim with M5 Omar Kahwaji
2010/10/26 [m5-users] about dramsim with M5 赵鹏
2010/10/26 Re: [m5-users] Identifying application instructions under ALPHA_FS Ali Saidi
2010/10/26 Re: [m5-users] Identifying application instructions under ALPHA_FS Lide Duan
2010/10/25 Re: [m5-users] Identifying application instructions under A LPHA_FS Ali Saidi
2010/10/25 Re: [m5-users] Identifying application instructions under ALPHA_FS George Tz.
2010/10/25 Re: [m5-users] Identifying application instructions under ALPHA_FS George Tz.
2010/10/25 Re: [m5-users] Identifying application instructions under ALPHA_FS Lide Duan
2010/10/25 Re: [m5-users] Identifying application instructions under ALPHA_FS Lide Duan
2010/10/24 Re: [m5-users] Identifying application instructions under ALPHA_FS Malek Musleh
2010/10/24 Re: [m5-users] Identifying application instructions under ALPHA_FS George Tz.
2010/10/24 [m5-users] Identifying application instructions under ALPHA_FS Lide Duan
2010/10/24 Re: [m5-users] spec2000 and spec2006 Ali Saidi
2010/10/24 [m5-users] spec2000 and spec2006 虞保忠
2010/10/24 Re: [m5-users] Re : Re: m5-users Digest, Vol 51, Issue 31 : Re: Error Creating a disk image using PTXDIST Ali Saidi
2010/10/24 [m5-users] Re : Re: m5-users Digest, Vol 51, Issue 31 : Re: Error Creating a disk image using PTXDIST Ong Wen Jian
2010/10/23 [m5-users] SPEC20000, SPEC2006 20921187
2010/10/23 Re: [m5-users] SurgeStandard never end Ali Saidi
2010/10/23 Re: [m5-users] how to build ALPHA_SE pthread based program by myself? Steve Reinhardt
2010/10/23 [m5-users] Help sunitha p
2010/10/23 Re: [m5-users] how to build ALPHA_SE pthread based program by myself? sunitha p
2010/10/22 [m5-users] how to build ALPHA_SE pthread based program by myself? Dave
2010/10/22 Re: [m5-users] Need Help Building M5 Gabriel Michael Black
2010/10/22 [m5-users] Need Help Building M5 Simran Basi
2010/10/22 Re: [m5-users] Changing O3CPU pipeline depth Steve Reinhardt
2010/10/22 Re: [m5-users] HELP NEEDED ... about cache block status Steve Reinhardt
2010/10/22 [m5-users] SurgeStandard never end Ying Zhang
2010/10/22 Re: [m5-users] Changing O3CPU pipeline depth Glenn Ko
2010/10/22 [m5-users] Fwd: Cache memory access patterns sunitha p
2010/10/22 Re: [m5-users] HELP NEEDED ... about cache block status Weixun Wang
2010/10/21 [m5-users] Cache memory access patterns sunitha p
2010/10/21 Re: [m5-users] Multiple-system simulation Steve Reinhardt
2010/10/21 Re: [m5-users] modeling a small network in M5 Gabe Black
2010/10/21 [m5-users] modeling a small network in M5 Ying Zhang
2010/10/21 [m5-users] Multiple-system simulation Lide Duan
2010/10/21 Re: [m5-users] Error Creating a disk image using PTXDIST Ali Saidi
2010/10/20 Re: [m5-users] Error Creating a disk image using PTXDIST Omar Kahwaji
2010/10/19 Re: [m5-users] error helpme Ali Saidi
2010/10/19 Re: [m5-users] m5-users Digest, Vol 51, Issue 31 : Re: Error Creating a disk image using PTXDIST Ali Saidi
2010/10/19 [m5-users] error helpme Sudhanshu Bodawala
2010/10/19 [m5-users] m5-users Digest, Vol 51, Issue 31 : Re: Error Creating a disk image using PTXDIST Ong Wen Jian
2010/10/19 Re: [m5-users] Slow build - a scons issue? nathan binkert
2010/10/19 [m5-users] Slow build - a scons issue? Matthew Horsnell
2010/10/18 Re: [m5-users] Error Creating a disk image using PTXDIST Ali Saidi
2010/10/18 [m5-users] Error Creating a disk image using PTXDIST Omar Kahwaji
2010/10/18 [m5-users] dramsim with m5 biswabandan panda
2010/10/17 Re: [m5-users] StoreCond Assertion Error with 4 CPU and L3 Cache Joe Gross
2010/10/17 [m5-users] stats of moesi coherence protocol biswabandan panda
2010/10/17 Re: [m5-users] Possible bug with LLSC instructions and coherence protocol? Lesha Jolondz
2010/10/16 Re: [m5-users] How to actually change the cache config Gabriel Michael Black
2010/10/16 [m5-users] How to actually change the cache config Yu Licheng
2010/10/15 Re: [m5-users] getting zeros in multicores with splash biswabandan panda
2010/10/15 Re: [m5-users] getting zeros in multicores with splash Steve Reinhardt
2010/10/15 Re: [m5-users] getting zeros in multicores with splash Ali Saidi
2010/10/15 Re: [m5-users] getting zeros in multicores with splash biswabandan panda
2010/10/15 Re: [m5-users] getting zeros in multicores with splash Steve Reinhardt
2010/10/15 Re: [m5-users] getting zeros in multicores with splash biswabandan panda
2010/10/15 Re: [m5-users] getting zeros in multicores with splash Steve Reinhardt
2010/10/15 [m5-users] HELP NEEDED ... about cache block status Weixun Wang
2010/10/15 Re: [m5-users] getting zeros in multicores with splash biswabandan panda
2010/10/15 Re: [m5-users] getting zeros in multicores with splash Steve Reinhardt
2010/10/15 Re: [m5-users] Changing O3CPU pipeline depth Steve Reinhardt
2010/10/15 Re: [m5-users] getting zeros in multicores with splash biswabandan panda
2010/10/15 Re: [m5-users] StoreCond Assertion Error with 4 CPU and L3 Cache Steve Reinhardt
2010/10/15 Re: [m5-users] getting zeros in multicores with splash Steve Reinhardt
2010/10/15 Re: [m5-users] Question about cache miss statistics for spec 2006 benchmarks Steve Reinhardt
2010/10/15 [m5-users] getting zeros in multicores with splash biswabandan panda
2010/10/15 Re: [m5-users] splash2 with m5beta6 biswabandan panda
2010/10/15 Re: [m5-users] splash2 with m5beta6 Lide Duan
2010/10/15 Re: [m5-users] splash2 with m5beta6 biswabandan panda
2010/10/15 Re: [m5-users] splash2 with m5beta6 Lide Duan
2010/10/15 Re: [m5-users] splash2 with m5beta6 biswabandan panda
2010/10/15 Re: [m5-users] splash2 with m5beta6 Lide Duan
2010/10/15 Re: [m5-users] splash2 with m5beta6 biswabandan panda
2010/10/15 Re: [m5-users] splash2 with m5beta6 Gabe Black
2010/10/15 Re: [m5-users] splash2 with m5beta6 biswabandan panda
2010/10/15 Re: [m5-users] splash2 with m5beta6 Gabe Black
2010/10/15 [m5-users] splash2 with m5beta6 biswabandan panda
2010/10/14 Re: [m5-users] Potential deadlock in O3CPU lead some of the benchmark running without termination. Liang Wang
2010/10/13 Re: [m5-users] Potential deadlock in O3CPU lead some of the benchmark running without termination. Ali Saidi
2010/10/13 Re: [m5-users] What is a reasonable size for memory under ALPHA_FS? Joel Hestness
2010/10/13 Re: [m5-users] What is a reasonable size for memory under ALPHA_FS? Steve Reinhardt
2010/10/13 Re: [m5-users] What is a reasonable size for memory under ALPHA_FS? Gabriel Michael Black
2010/10/13 [m5-users] What is a reasonable size for memory under ALPHA_FS? Lide Duan
2010/10/13 Re: [m5-users] NoopMachInst error in m5.opt build for O3CPU model (X86_FS) Gabe Black
2010/10/13 [m5-users] NoopMachInst error in m5.opt build for O3CPU model (X86_FS) dibakar gope
2010/10/12 Re: [m5-users] page table fault during splash2 Gabe Black
2010/10/12 [m5-users] page table fault during splash2 biswabandan panda
2010/10/11 [m5-users] segmentation fault in m5 biswabandan panda
2010/10/11 [m5-users] StoreCond Assertion Error with 4 CPU and L3 Cache Joe Gross
2010/10/11 [m5-users] Changing O3CPU pipeline depth Glenn Ko
2010/10/10 Re: [m5-users] Error with dcache block size = 4 Glenn Ko
2010/10/10 [m5-users] want to assign different workload to different cpu biswabandan panda
2010/10/09 [m5-users] Question about cache miss statistics for spec 2006 benchmarks Zhe Wang
2010/10/09 [m5-users] different workloads to different cpus in run.py of splash2 biswabandan panda
2010/10/08 Re: [m5-users] Unimplemented trap to OS Gustavo Henrique Nihei
2010/10/08 Re: [m5-users] Unimplemented trap to OS Gabe Black
2010/10/08 [m5-users] Unimplemented trap to OS Gustavo Henrique Nihei
2010/10/08 Re: [m5-users] Error with dcache block size = 4 Gabe Black
2010/10/07 Re: [m5-users] Some of PARSEC benchmarks never end. Joel Hestness
2010/10/07 Re: [m5-users] Error with dcache block size = 4 Glenn Ko
2010/10/07 [m5-users] question about cache and bus Zhe Wang
2010/10/07 Re: [m5-users] How to make a checkpoint before the region o f interest (FS mode)? Ali Saidi
2010/10/07 [m5-users] Boot linux kernel with M5 simulator on X86 platform Ong Wen Jian
2010/10/07 Re: [m5-users] How to make a checkpoint before the region of interest (FS mode)? Lide Duan
2010/10/07 Re: [m5-users] How to make a checkpoint before the region o f interest (FS mode)? Ali Saidi
2010/10/07 Re: [m5-users] How to make a checkpoint before the region of interest (FS mode)? Lide Duan
2010/10/07 [m5-users] coherence protocol statistics biswabandan panda
2010/10/07 [m5-users] How to make a checkpoint before the region of interest (FS mode)? Lide Duan
2010/10/07 Re: [m5-users] Error with dcache block size = 4 Gabe Black
2010/10/07 Re: [m5-users] Error with dcache block size = 4 Steve Reinhardt
2010/10/07 Re: [m5-users] Compile My Own Linux Kernel and boot with M5 simulator Gabe Black
2010/10/07 Re: [m5-users] Error with dcache block size = 4 Gabe Black
2010/10/07 Re: [m5-users] Error with dcache block size = 4 Steve Reinhardt
2010/10/07 Re: [m5-users] Compile My Own Linux Kernel and boot with M5 simulator Ong Wen JIan
2010/10/07 [m5-users] Error with dcache block size = 4 Glenn Ko
2010/10/06 Re: [m5-users] Signals nathan binkert
2010/10/06 [m5-users] (no subject) Richard Strong
2010/10/06 Re: [m5-users] Signals Joe Gross
2010/10/06 Re: [m5-users] Signals Gabe Black
2010/10/05 [m5-users] Signals Joe Gross
2010/10/05 [m5-users] segmentation fault biswabandan panda
2010/10/04 [m5-users] cache configuration in m5 b.3 biswabandan panda